JPH02100325A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To achieve low impedance and prevent noise by performing wiring, overlapping a powder supply wiring on the positive side and one on the negative side and by forming a capacitor of the power supply wiring on the positive side and the one on the negative side through an insulating layer. CONSTITUTION:A power supply wiring 4 on the negative side and a power supply wiring 5 on the positive side are wired while they are overlapped partially and a power supply wiring 6 on the negative side and a power supply wiring 7 on the positive side are insulated using an insulating layer 8 such as a silicon oxide. This structure forms a capacitor where two electrodes (wiring layers) are opposed to each other through an insulating substance. By overlapping and wiring the power supply wiring on the positive side and the power supply wiring at the negative side, wiring region can be shared, the chip size of a semiconductor integrated device can be reduced by sharing the wiring region, and the low impedance of the power supply wiring can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to wiring arrangement of power supply wiring within a semiconductor integrated device.

[Prior Art] Generally, it is desirable that the impedance of power supply wiring for electronic devices be as low as possible in order to prevent power supply noise such as power drop due to load fluctuations. Furthermore, in order to deal with instantaneous power supply noise, a method has been adopted in which a bypass capacitor is added between the power supplies and the power supply noise is absorbed by the capacitance component of the bypass capacitor.

BACKGROUND ART Conventionally, power supply wiring in a semiconductor integrated device, which is a type of electronic device, has been made as wide as possible due to the need for low impedance in order to prevent power supply noise.

[The problem that the invention attempts to solve] However, the conventional example described above has the following problems.

In order to achieve low impedance, the wiring width is made as wide as possible, but this results in a thicker chip size, leading to higher costs.For example, when dealing with high frequency loads, In the case of driving, the wiring width of the power supply wiring in the semiconductor integrated circuit needs to be about 100 μm, which means that for a semiconductor integrated device with a size of several millimeters square or less, the width of the power supply wiring in the semiconductor integrated circuit is approximately 3 In some cases, it even accounts for a large percentage of the total.

The present invention solves the above-mentioned problems, and its purpose is to provide a power supply wiring arrangement for semiconductor integrated devices that has low impedance and also functions as a bypass capacitor inserted between the power supplies to prevent noise. It provides:

[Means for Solving Labor Problems] In order to solve the above-mentioned problems, the present invention provides a semiconductor integrated device having two or more wiring layers. The whole or a part of the second wiring layer of one of the wiring layers is overlapped with each other, and one wiring layer of the first wiring layer and the second wiring layer is used as a power supply wiring on the device side, A feature is that the other wiring layer is a negative power supply wiring.

[Function] According to the present invention, the positive power supply wiring and the negative power supply wiring are wired in an overlapping manner, so that the wiring area can be shared by the positive power supply wiring and the negative power supply wiring. Further, the plus side power supply wiring and the minus side power supply wiring form a capacitor with the insulating layer interposed therebetween.

[Example] Examples of the present invention will be described below. FIG. 1 is a layout diagram showing an embodiment of the present invention. The dashed line 1 indicates the outer periphery of the semiconductor integrated device. 2 is plus! The pad for I power supply is shown. 5 indicates a pad for the negative side power supply. 4
is a negative power supply wiring wired inside a semiconductor integrated device, and uses a second wiring layer. Reference numeral 5 denotes a positive power supply wiring wired within the semiconductor integrated device, using the first wiring layer. The negative power supply wiring 4 and the positive power supply wiring 5
The wires are partially overlapped.

Here, FIG. 2 shows a cross-sectional state of a portion where the negative power supply wiring 4 and the positive power supply wiring 5 overlap. 7
uses the first wiring layer for the positive power supply wiring. 6
uses the second wiring layer for the negative power supply wiring.

Reference numeral 8 is an insulating layer made of silicon oxide (Sin, etc.), which insulates the negative power supply wiring 6 and the positive power supply wiring 7. This structure is a capacitor in which two electrodes (in this embodiment, two wiring layers) face each other with an insulating material in between. Therefore, if the overlapping area of the negative power wiring 6 and the positive power wiring 70 is 81, and the distance i49 between the negative power wiring 6 and the positive power wiring 7 is ε, which is the dielectric constant of the insulating layer 8, then the negative power wiring 6 A capacitance component having a value of 0 as shown in the following equation is attached between and the positive power supply wiring 7.

In this embodiment, an example was shown in which the first wiring layer was the positive side power supply wiring and the second wiring layer was the negative side FLL source wiring, but the first wiring layer was the negative side ILT source wiring and the second The wiring layer may be used as a positive power supply wiring.

In addition, the layout diagram in Figure 1 is drawn narrowly so that the first and second wiring layers fit within the size of the first wiring layer in order to make the drawing easier to read. The layer may be wider than the first wiring layer, or the first wiring layer and the second wiring layer may have the same width.

[Effects of the Invention] As described above, according to the present invention, since the positive side power supply wiring and the negative tlllt source wiring are wired in an overlapping manner, the wiring area can be shared, and since the wiring area is shared, the semiconductor integrated device can be improved. Chip size can be reduced and manufacturing costs can be reduced.

It is also possible to make the power supply wiring even wider by taking advantage of the fact that the wiring area is reduced by overlapping the wiring.
The impedance of the power supply wiring can be reduced and it can be used as a power supply wiring suitable for high frequency applications.

Furthermore, by overlapping the glass side power supply wiring and the negative side power supply wiring, a capacitance component is attached between the positive side power supply wiring and the negative side power supply wiring, forming a bypass capacitor.

Therefore, the power supply wiring can easily absorb power supply noise.

[Brief explanation of drawings]

FIG. 1 is a layout diagram showing an embodiment of the present invention. FIG. 2 is a sectional view showing an embodiment of the present invention. 1......Outer periphery of semiconductor integrated device 2.
......Pass side power pad 3...
...Minus III! l Power pad 4.6
...Minus llI! I power supply wiring 5.7...
・・・Glass side power supply wiring 8・・・・・・・・・Insulating layer or higher

Claims (1)

[Claims] In a semiconductor integrated device having two or more wiring layers, the first
The whole or part of a second wiring layer of at least one of the other wiring layers is superimposed on the wiring layer of the wiring layer, and one of the first wiring layer and the second wiring layer is wired. A semiconductor integrated device characterized in that one wiring layer is used as a positive side power supply wiring, and the other wiring layer is used as a negative side power supply wiring.