JPH02284467A - Gate-array type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase the types of the constituting circuits of a gate-array type semiconductor integrated circuit and improve the performance by a method wherein a plurality of polycrystalline silicon layers are provided under an outer gate part in parallel with the respective sides of chips and utilized as resistors or capacitors. CONSTITUTION:An inner gate part 4 in which basic cells are arranged and outer gate part 5 in which I/O circuits are arranged are provided on a semiconductor substrate 1. An outer polycrystalline silicon wiring part 2 and an inner polycrystalline silicon wiring part 3 are provided under the outer gate part 5 and the inner gate part 4 as polycrystalline silicon layers. The wiring part 2 is composed of Al pads 7, wirings 6, wirings 8 and 9 interconnecting them and contacts 10 and is buried in an insulating layer 14 and can generate capacitances and can be utilized as large capacity bus capacitors. The wiring part 3 is composed of inner polycrystalline silicon wirings 11, interconnection wirings 12 and contacts 10 and can be utilized as bus capacitors of an electric source and resistors like the wiring part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to a gate array type semiconductor integrated circuit, and particularly relates to a gate array type semiconductor integrated circuit that makes effective use of chips.

〔overview〕

The present invention provides a gate array type semiconductor integrated circuit in which a plurality of polycrystalline silicon layers are provided in parallel to each side of the chip under an external gate section and under an internal gate section and an external gate section, and these layers are used as resistors or capacitors. By using it, it is possible to increase the types of circuits that can be configured and improve their performance.

[Conventional technology]

Conventionally, this type of gate array type semiconductor integrated circuit has a fifth
As shown in the figure, it has a structure in which an internal gate section 4 and an external gate section 5 are arranged on a semiconductor substrate 1, and a polysilicon layer made of polycrystalline silicon (hereinafter referred to as polysilicon) is formed on the internal gate section 4 and external gate section. Generally, it is used as the gate of the transistor No. 5, and other than that, it is only used as a protective resistor of the human-powered Hanofa.

Therefore, mainly the areas where only metal wiring is formed, that is, the spaces under the pads around the chip and between the internal gates are not effectively utilized.

Furthermore, this type of gate array type semiconductor integrated circuit cannot achieve large resistance and capacitance values due to space limitations. In order to obtain a large resistance value, the channel resistance of a transistor with a channel length is used, which has the drawback of temperature characteristics.

[Problem that the invention seeks to solve]

The conventional gate array type semiconductor integrated circuit described above uses only metal wiring as the wiring. Furthermore, the area under the pads around the chip and between the internal and external gate parts is not effectively utilized. Furthermore, large stable resistances and capacitances cannot be obtained.

Therefore, there is a drawback that the circuits that can be configured on the gate array and the performance thereof are limited.

An object of the present invention is to provide a gate array type semiconductor integrated circuit which can realize large and stable resistance and capacitance without increasing the chip size by eliminating the above-mentioned drawbacks, and which can increase the types of circuits that can be configured and improve their performance. The purpose is to provide circuits.

[Failure to solve the problem]

The present invention provides a gate array type semiconductor integrated circuit comprising an internal gate section in which basic cells are arranged and an external gate section in which input/output circuits are arranged. It is characterized by having a plurality of polycrystalline silicon layers provided in the region parallel to each side of the chip.

[Effect]

The present invention has a polygon layer that is provided in parallel to each side of the chip at the lower part of the outer gate part around the chip and between the inner gate part and the outer gate part in a grounding process. and,
The polysilicon layer can be used as a resistor or as a capacitor added to a pad of an external gate portion, depending on the circuit to be constructed.

Therefore, even circuits requiring large resistances and capacitances can be configured without particularly increasing the chip area, and it is possible to increase the types of circuits that can be configured and improve their characteristics.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a layout diagram showing the first embodiment of the present invention, and FIG.
FIG. 2(a) is a top view showing a part of the external polysilicon wiring portion, and FIG. 2(b) is a sectional view taken along the line xx'.

According to FIG. 1, in the present embodiment, on a semiconductor substrate 1,
In a gate array type semiconductor integrated circuit comprising an internal gate section 4 in which basic cells are arranged and an external gate section 5 in which input/output circuits are arranged, the external gate section is 5, and an internal polysilicon wiring section 3 provided below between the internal gate section 4 and the external gate section 5.

As shown in FIGS. 2(a) and 2(b), the external polysilicon wiring portion 2 includes each pad 7 made of aluminum.
External polyurethane wiring 6 is disposed intermittently at the bottom of the circuit, and according to circuit requirements, contact is established between each external polyurethane wiring 6 and between the external polyurethane wiring 6 and the punt 7 by connecting aluminum wirings 8 and 9 made of aluminum, respectively. Connected via eye 0.

Further, the internal polysilicon wiring section 3 is made up of two internal polysilicon wirings 11 that are continuously provided. In addition, in FIG. 2(b), 14 is an insulating layer.

External polygonal wiring 6 shown in FIGS. 2(a) and (b)
is discontinuous between each pad 7, and the connection between the pad 7 and the external polysilicon wiring 6, and the mutual connection between the external polysilicon wiring 6 and the external polysilicon wiring 6, is made freely in the contact process in the ground process. Can be set to

Therefore, the external polysilicon wiring 6 can generate a capacitance between the pads 7, or can be used as a large-capacity bus capacitor with the semiconductor substrate 1 by connecting all the external polysilicon wirings 6.

The internal polysilicon wiring 11 can also be used as a bus capacitor between power supplies, a delay capacitor for the oscillation circuit, and a resistor.

At the pad 7 location, the capacitance with the semiconductor substrate 1 is approximately 0.
8 pF is obtained, and the capacitance between the electrically non-conductive pads 7 is approximately 0.6 pF. Further, the capacitance of the entire chip with respect to the semiconductor substrate 1 is approximately 100 pF.

However, the above values are based on pad 7 having a size of 120 μm square, a dielectric constant of 5102 of 3, and a thickness of 0.6 mm.
This value is calculated assuming that am and the side of Jinpu are 5n+m.

3 is a top view showing a part of the external polysilicon part of the second embodiment of the present invention, FIG. 4(a) is a top view showing a part of the internal polysilicon part, and FIG. 4(b) is a top view of the -Y'
FIG.

In the second embodiment, the external polysilicon wiring section 2 in FIG.
A continuous external polysilicon wiring 6 as shown in FIG. 3 is provided, and the internal polysilicon wiring section 3 is as shown in FIGS.
) is provided with intermittent polysilicon wiring as shown in FIG. The internal poly-silicon wiring 11 is arbitrarily connected via the contact line O by the connecting aluminum wiring 12 in accordance with the requirements of the circuit in a contact process in the overlay process.

In the second embodiment, compared to the first embodiment, the external polysilicon wiring 6 is connected without a contact, so the capacitance between the chip and the circumference is larger than in the first embodiment, so it is used as a bypass capacitor between the power supplies. This will result in stable operation.

Further, in the second embodiment, since the internal polysilicon wiring 11 is discontinuous, it can be used as one wiring within the circuit. If the internal polysilicon wiring 11 is connected in series and used as a feedback resistor of the oscillation circuit, good oscillation can be obtained since polysilicon is a stable resistor.

For polysilicon with a width of 3 μm and a length of 3000 μm, the resistance is 20Ω.
It is a resistor of 70Ω to 70Ω, and acts as an inter-substrate capacitance of about 0.4pF.

〔Effect of the invention〕

As explained above, the present invention provides various advantages by disposing the polysilicon layer, which was not formed in the base process in the conventional gate array type semiconductor device, under the butt around the chip and between the internal gate part and the external gate part. Since it is possible to form a resistance and capacitance with a size of This has the effect of improving the types of circuits that can be constructed and their characteristics, such as by providing stable oscillation, without increasing the chip area.

Further, by providing a polysilicon layer under the band, it acts as a cushion during wire bonding, and has the effect of preventing destruction of portions with low strength such as the diffusion layer and gate oxide film around the bonding ink pad.

[Brief explanation of drawings]

FIG. 1 is a layout diagram showing a first embodiment of the present invention. FIG. 2(a) is a two-sided view showing a part of the external polysilicon wiring section. FIG. 2(b) is its xx' cross-sectional view. FIG. 3 is a top view showing a portion of the external polysilicon wiring section of the second embodiment of the present invention. FIG. 4(a) is a top view showing a part of the internal polysilicon wiring section. FIG. 4(b) is a sectional view taken along the Y-Y' line. FIG. 5 is a layout diagram of a conventional example. 1... Semiconductor substrate, 2... External polysilicon wiring part, 3
...Internal polysilicon wiring part, 4...Internal gate part, 5
... External gate section, 6... External polysilicon wiring, 7.
・Band, 8.9.12... Connection aluminum wiring, 10.
...Contact, 11...Internal polysilicon wiring, 13...
Inter-gate region, 14...insulating layer.

Claims (1)

[Claims] 1. A gate array type semiconductor integrated circuit comprising an internal gate section in which basic cells are arranged and an external gate section in which input/output circuits are arranged, comprising: A gate array type semiconductor device comprising a plurality of polycrystalline silicon layers provided in a region outside an internal gate section in parallel with each side of a chip.