JPH03248440A - High output gaas field effect transistor - Google Patents

Abstract

PURPOSE:To correct phase deviation among cells and to acquire high output in accordance with the number of cells by mutually connecting drain electrodes and gate electrodes, respectively which are divided among cells connected in parallel through a resistor which is composed of a GaAs active layer connected to an ohmic electrode provided to each of them. CONSTITUTION:A drain electrode D and a gate electrode G are divided among cells and formed. The drain electrode D of each cell is provided with an ohmic electrode 4 and connected mutually through a resistance layer 3 composed of a GaAs active layer connected to the ohmic electrode 4. The gate electrode of each cell is provided with an ohmic electrode 1 and connected mutually through a resistance layer 2 which consists of a GaAs active layer connected thereto. According to this constitution, each cell connected in parallel operates in the same phase or nearly in the same phase, thereby uniforming phase of output of each cell and acquire high output in accordance with the number of cells.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high power potassium arsenic field effect transistor (
(GaAsFET) structure, especially FET structure in which a large number of cells operate in the same phase.

[Prior Art] As shown in FIG. 2, a conventional high-output GaAsFET is constructed by arranging a unit FET, for example, a plurality of four cells 11 (two in the figure) in parallel, and increasing the gate width to increase the height. The gate electrode G, drain electrode, and source electrode S are integrally formed between the cells in order to make the operating phase of these cells the same.

[Problem to be solved by the invention] In this conventional high-power GaAsFET, when increasing the frequency or connecting a large number of cells in parallel to increase the output, the width of the electrode and the wavelength (λ) of the frequency used are 1/1/2. 2 (in/2
) become the same level, and if the phases of cells on both sides of the FET are extreme, they will be shifted by π, resulting in a situation where the outputs cancel each other out when combined. As a result, there was a problem in that even if the number of cells was increased, the output did not increase in proportion to the number of cells.

[Means for Solving the Problems] A high-power GaAsFET according to the present invention is a high-power GaAs field effect transistor in which a plurality of cells are connected in parallel, and an ohmic electrode is provided on a drain electrode and a gate electrode divided between each cell. and the drain electrode and the gate electrode are connected to the ohmic electrode.
s are characterized in that they are connected to each other via a resistor consisting of an active layer.

[Example code] Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows a high-power GaAsFET according to an embodiment of the present invention.
FIG.

As shown in the figure, the drain electrode and the gate electrode G are divided and formed between cells. Ohmic electrodes 4 are provided on the drain electrodes of each cell, and a resistance layer 3 made of a GaAs active layer is connected to these ohmic electrodes 4.
The drain electrodes of each cell are connected to each other. Further, an ohmic electrode 1 is provided on the gate electrode of each cell, and the gate electrodes G of each cell are connected to each other by a resistance layer 2 made of a GaAs active layer connected to these ohmic electrodes 1. Note that the source electrodes S are normally short-circuited to the ground plane without any inductance, so they are usually in the same phase, so it is only necessary to use the same electrodes formed integrally. In addition, the electrode G is connected to the GaAS active N2,4.
, D would result in a Schottky contact if they were directly connected, so ohmic electrodes 1, 4 are interposed between the active layers 2, 4 and the electrodes G, D. Incidentally, since an ohmic electrode is usually formed in the active layer region 5 that performs FET operation, the drain electrode may be provided with an ohmic electrode over the entire region to form the ohmic electrode 4.

As mentioned above, the FET of this example has a resistive layer 2 between the cells,
These resistance layers 2 and 4 are arranged in such a way that each cell connected in parallel operates in the same phase or close to the same phase, depending on the electrode width, frequency used, etc. Set to value.

According to the above configuration, each cell connected in parallel operates in the same phase or in a phase very close to the same phase, and by aligning the output phases of each cell, a high output corresponding to the number of cells can be obtained.

[Effects of the Invention] As explained above, in the present invention, the cells are connected by resistors and the phase shift between each cell is corrected, so it is possible to obtain a high output corresponding to the number of cells connected in parallel. .

[Brief explanation of drawings]

FIG. 1 is a plan view showing an embodiment of the present invention, and the figure is a plan view showing a conventional example. D...Drain electrode, S...Source electrode, G...Gate electrode, 1.4...Ohmic junction electrode, 2 .3...
...GaAs active layer, 5... Active layer. Second

Claims (1)

[Claims] In a high-power GaAs field effect transistor in which multiple cells are connected in parallel, ohmic electrodes are provided on the drain electrode and gate electrode divided between each cell, respectively.
A high power GaAs field effect transistor characterized in that the drain electrode and the gate electrode are connected to the ohmic electrode through a resistor made of a GaAs active layer.