JPH07111271A - High power field-effect transistor - Google Patents

High power field-effect transistor

Info

Publication number
JPH07111271A
JPH07111271A JP27788493A JP27788493A JPH07111271A JP H07111271 A JPH07111271 A JP H07111271A JP 27788493 A JP27788493 A JP 27788493A JP 27788493 A JP27788493 A JP 27788493A JP H07111271 A JPH07111271 A JP H07111271A
Authority
JP
Japan
Prior art keywords
unit
electrodes
bus bar
resistor
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27788493A
Other languages
Japanese (ja)
Inventor
Shigeru Saito
茂 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27788493A priority Critical patent/JPH07111271A/en
Publication of JPH07111271A publication Critical patent/JPH07111271A/en
Pending legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To suppress an oscillation caused by the signal fed back between the unit field-effect transistors connected in parallel with each other in order to obtain a high output power. CONSTITUTION:A high power transistor module is composed of a number of unit field-effect transistors. A plurality of unit gate electrodes 3 or a plurality of unit drain electrodes 5 are connected to each other with bus-bar electrode 2 or 8 so as to form a comb shape to constitute a unit cell 9. The respective bus-bar electrodes of the same electrodes of both unit cells adjacent to each other are connected to each other with a resistance element 4 composed of an ohmic resistor 4a or a thin film metal resistor 4b. With this constitution, the integrated gain of a loop produced by the fed-back signals between the unit transistors 3a and 3b can be reduced and an unnecessary oscillation can be suppressed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数の単位ゲート電極
及び単位ドレイン電極を櫛型状に配置した電界効果トラ
ンジスタに関し、特にマイクロ波帯以上の高周波帯で高
出力を得る電界効果トランジスタに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor having a plurality of unit gate electrodes and unit drain electrodes arranged in a comb shape, and more particularly to a field effect transistor capable of obtaining a high output in a high frequency band higher than a microwave band.

【0002】[0002]

【従来の技術】従来の電界効果トランジスタは、図2に
示すように複数本の単位ゲート電極(3)を櫛型に配列
した第1バスバー電極(12)と、ボンディング電極
(7)につながる第2バスバー電極(16)とを絶縁膜
(14)を介して積層するとともに、この絶縁膜(1
4)に設けたスルーホール(15)を介して両者を相互
に電気接続している。そして、このスルーホール(1
5)は各単位ゲート電極(3)とボンディング電極
(7)との幾何学的な距離がそれぞれ等しくなる位置に
配設している(例えば、特開平3−58435号公
報)。この構成により各単位ゲート電極(3)とボンデ
ィング電極(7)との距離は等しくなる。したがって、
ボンディング電極(7)を給電点とする周波数信号に対
して各単位ゲート電極(3)間での位相差が最少とな
り、マイクロ波帯等の高周波信号に対する位相差を緩和
し、単位電界効果トランジスタ間での不均一動作を解消
することができる。
2. Description of the Related Art As shown in FIG. 2, a conventional field effect transistor has a first bus bar electrode (12) in which a plurality of unit gate electrodes (3) are arranged in a comb shape, and a first electrode connected to a bonding electrode (7). The two bus bar electrodes (16) are laminated via the insulating film (14), and the insulating film (1
Both are electrically connected to each other through a through hole (15) provided in 4). And this through hole (1
5) is arranged at a position where the geometrical distances between the unit gate electrodes (3) and the bonding electrodes (7) are equal to each other (for example, JP-A-3-58435). With this configuration, the distance between each unit gate electrode (3) and the bonding electrode (7) becomes equal. Therefore,
The phase difference between the unit gate electrodes (3) is minimized with respect to the frequency signal using the bonding electrode (7) as a feeding point, and the phase difference for a high frequency signal such as a microwave band is mitigated. It is possible to eliminate the non-uniform operation in.

【0003】[0003]

【発明が解決しようとする課題】上述した電界効果トラ
ンジスタは各単位トランジスタを通過する位相差は緩和
する。しかし単位トランジスタの性能が向上して非常に
高い周波数まで動作するようになると各単位トランジス
タ間の電気的遅延時間が半周期となる周波数で利得が1
以上の場合発振が生じる場合がある。例えば、図2にお
いて一番左端の単位トランジスタ(3a)と一番右端の
単位トランジスタ(3b)とでは物理的な距離がある。
この距離は遅延時間を生じ単位トランジスタ(3a)→
バスバー電極(8)→単位トランジスタ(3b)→第1
バスバー(12)→単位トランジスタ(3b)のループ
(図中矢印)で位相が2nπ、nは、1,2,3……と
なり総合利得が1以上となると発振が起こる。単位トラ
ンジスタの動作周波数が高くなるほど小さなループで発
振が起こりやすくなり、多数の単位トランジスタを並列
動作する高出力電界効果トランジスタは上記した発振の
可能性が大きくなるという問題がある。
The field effect transistor described above alleviates the phase difference passing through each unit transistor. However, if the performance of the unit transistors is improved to operate at a very high frequency, the gain becomes 1 at the frequency where the electrical delay time between the unit transistors becomes a half cycle.
In the above case, oscillation may occur. For example, there is a physical distance between the leftmost unit transistor (3a) and the rightmost unit transistor (3b) in FIG.
This distance causes a delay time, and the unit transistor (3a) →
Bus bar electrode (8) → unit transistor (3b) → first
In the loop (arrow in the figure) of the bus bar (12) → unit transistor (3b), the phase becomes 2nπ, n becomes 1, 2, 3, ... And oscillation occurs when the total gain becomes 1 or more. The higher the operating frequency of the unit transistor, the more easily the small loop oscillates, and the high-output field-effect transistor in which a large number of unit transistors operate in parallel has a problem that the above-mentioned possibility of oscillation increases.

【0004】[0004]

【課題を解決するための手段】本発明の高出力電界トラ
ンジスタは、複数本の単位ゲート電極または単位ドレイ
ン電極を櫛型にバスバー電極で接続した単位セルと、同
様に構成した隣り合う単位セルの両方の同じ電極どうし
のバスバー電極を抵抗体で電気的に接続したことを備え
ているものである。
A high output electric field transistor of the present invention includes a unit cell in which a plurality of unit gate electrodes or unit drain electrodes are connected in a comb shape by bus bar electrodes, and an adjacent unit cell having the same configuration. The bus bar electrodes of both the same electrodes are electrically connected by a resistor.

【0005】[0005]

【作用】本発明においては、複数本の単位ゲート電極ま
たは単位ドレイン電極を櫛型にバスバー電極で接続した
単位セルと、同様に構成した隣り合う単位セルの両方の
同じ電極どうしのバスバー電極の中間に抵抗性の導体を
配置して、同一チップ(単位トランジスタ)上の高周波
に対するアンバランスを抵抗体により吸収し、同一チッ
プ内による高周波信号の回り込みを減衰させるもので、
同一チップ内の回り込みによる発振がなくなるものであ
る。
According to the present invention, a unit cell in which a plurality of unit gate electrodes or unit drain electrodes are connected in a comb shape by bus bar electrodes and an intermediate bus bar electrode between the same electrodes of adjacent unit cells having the same structure are provided. By disposing a resistive conductor in, the resistor absorbs unbalance against high frequencies on the same chip (unit transistor), and attenuates the sneak of high frequency signals in the same chip.
Oscillation due to wraparound in the same chip is eliminated.

【0006】[0006]

【実施例】次に本発明の実施例について図面を参照して
説明する。図1は本発明の一実施例である。(a)は平
面図、(b)(c)は(a)のB−Bの断面図である。
半導体基板(1)上に複数の単位ゲート電極(3)、単
位ドレイン電極(5)、単位ソース電極(6)が形成さ
れ、単位ドレイン電極(5)はバスバー電極(8)によ
り櫛形に接続されている。単位ゲート電極は、バスバー
電極(2)により櫛形に接続され単位トランジスタの集
りである単位セル(9)を構成している。隣り合う単位
セル(9)のバスバー電極(2)は、抵抗体(4)によ
り電気的に接続されている。抵抗体(4)は、半導体基
板を用いてオーミック抵抗(4a)、または薄膜金属等
による抵抗(4b)により形成する。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention. (A) is a plan view, (b) and (c) are sectional views taken along the line BB of (a).
A plurality of unit gate electrodes (3), unit drain electrodes (5) and unit source electrodes (6) are formed on a semiconductor substrate (1), and the unit drain electrodes (5) are connected in a comb shape by a bus bar electrode (8). ing. The unit gate electrodes are connected in a comb shape by the bus bar electrodes (2) to form a unit cell (9) which is a group of unit transistors. The bus bar electrodes (2) of adjacent unit cells (9) are electrically connected by a resistor (4). The resistor (4) is formed of an ohmic resistor (4a) using a semiconductor substrate or a resistor (4b) of thin film metal or the like.

【0007】この構成によれば、単位トランジスタ(3
a)→バスバー電極(8)→単位トランジスタ(3b)
→バスバー電極(2)→抵抗体(4)→バスバー電極
(2)→単位トランジスタ(3a)のループの場合、総
合利得は抵抗体(4)により減少し、従来例で示したル
ープの総合利得よりも本発明の総合利得は低くなる。従
ってループによる発振を抑制することが可能となる。抵
抗体(4)を通らない単位セル内(9)のループも考え
られるが、単位セル(9)内のループ長を短くなるよう
に構成することにより発振する位相条件(最少でループ
位相が2π)が成立する周波数を高くすることが可能で
ある。その周波数で利得が1以下であればよい。単位セ
ル(9)を半分の大きさにすれば発振周波数は約倍にな
る。
According to this structure, the unit transistor (3
a) → bus bar electrode (8) → unit transistor (3b)
→ bus bar electrode (2) → resistor (4) → bus bar electrode (2) → unit transistor (3a) loop, the total gain is reduced by the resistor (4), the total gain of the loop shown in the conventional example The total gain of the present invention is lower than that. Therefore, it becomes possible to suppress oscillation due to the loop. A loop in the unit cell (9) that does not pass through the resistor (4) is also conceivable, but a phase condition for oscillating by configuring the loop length in the unit cell (9) to be short (minimum loop phase is 2π It is possible to increase the frequency at which It is sufficient that the gain is 1 or less at that frequency. If the unit cell (9) is halved in size, the oscillation frequency will be doubled.

【0008】従って単位セル(9)のループ位相を単位
トランジスタの最大発振周波数の周期よりも短くするこ
とにより発振を抑止することが可能となる。抵抗体
(4)は上記説明ではゲートのバスバー電極に設けて説
明したが、ドレインのバスバー電極に設けても同じ効果
がある。さらにドレインとゲートの各バスバー電極にそ
れぞれ抵抗体を設ければさらに効果が増大する。さらに
単位セル(9)は小さく区切ったほうが効果が増大す
る。
Therefore, the oscillation can be suppressed by making the loop phase of the unit cell (9) shorter than the cycle of the maximum oscillation frequency of the unit transistor. In the above description, the resistor (4) is provided on the bus bar electrode of the gate, but the same effect can be obtained by providing it on the bus bar electrode of the drain. Further, if a resistor is provided on each of the drain and gate bus bar electrodes, the effect is further enhanced. Furthermore, the effect is enhanced when the unit cell (9) is divided into smaller parts.

【0009】[0009]

【発明の効果】以上説明したように、本発明によれば、
複数本の単位ゲート電極または単位ドレイン電極を櫛形
にバスバー電極で接続した単位セルと、同様に構成した
隣り合う単位セルの相方の同じ電極どうしのバスバー電
極を抵抗体で電気的に接続することにより、単位トラン
ジスタ間の回り込みによるループの総合利得を低くする
ことが可能となり、不用な発振を抑止できる効果を有す
る。
As described above, according to the present invention,
By electrically connecting a unit cell in which a plurality of unit gate electrodes or unit drain electrodes are connected to each other in a comb shape by bus bar electrodes and a bus bar electrode of the same electrode on the opposite sides of adjacent unit cells that are similarly configured by a resistor. The total gain of the loop due to the sneak between the unit transistors can be lowered, and there is an effect that unnecessary oscillation can be suppressed.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例で、(a)は平面図、(b)
(c)は(a)のB−B断面図
FIG. 1 is a plan view of an embodiment of the present invention, and FIG.
(C) is BB sectional drawing of (a).

【図2】従来の技術で、(a)は平面図、(b)は
(a)のA−A断面図
2A is a plan view of the related art, and FIG. 2B is a sectional view taken along line AA of FIG.

【符号の説明】[Explanation of symbols]

1 半導体基板 2,8 バスバー電極 3 単位ゲート電極 4,4a,4b 抵抗体 5 単位ドレイン電極 6 単位ソース電極 3a,3b 単位トランジスタ 7 ボンディング電極 9 単位セル 12 第1バスバー電極 14 絶縁膜 15 スルーホール 16 第2バスバー電極 1 Semiconductor Substrate 2,8 Bus Bar Electrode 3 Unit Gate Electrode 4,4a, 4b Resistor 5 Unit Drain Electrode 6 Unit Source Electrode 3a, 3b Unit Transistor 7 Bonding Electrode 9 Unit Cell 12 First Bus Bar Electrode 14 Insulating Film 15 Through Hole 16 Second bus bar electrode

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成6年3月29日[Submission date] March 29, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】特許請求の範囲[Name of item to be amended] Claims

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【特許請求の範囲】[Claims]

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0004[Correction target item name] 0004

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【0004】[0004]

【課題を解決するための手段】本発明の高出力電界トラ
ンジスタは、複数本の単位ゲート電極または単位ドレイ
ン電極を櫛型にバスバー電極で接続した単位セルと、同
様に構成した隣り合う単位セルの両方の同じ電極どうし
のバスバー電極を抵抗体で電気的に接続したことを備え
ているものであり、また、複数本の単位ゲート電極を櫛
型にバスバー電極で接続した単位セルと、同様に構成し
た隣り合う単位セルの相方の同じ電極どうしのバスバー
電極を低抗体で電気的に接続し、かつ単位ドレイン電極
を櫛型に接続しているバスバー電極を抵抗体で電気的に
接続したことを特徴とするものである。
A high output electric field transistor of the present invention includes a unit cell in which a plurality of unit gate electrodes or unit drain electrodes are connected in a comb shape by bus bar electrodes, and an adjacent unit cell having the same configuration. It is provided with electrically connecting the busbar electrodes of both the same electrodes with a resistor, and also has the same configuration as a unit cell in which a plurality of unit gate electrodes are connected in a comb shape by busbar electrodes. The bus bar electrodes of the same electrodes on the opposite sides of the adjacent unit cells are electrically connected with a low antibody, and the bus bar electrodes with the unit drain electrodes connected in a comb shape are electrically connected with a resistor. It is what

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数本の単位ゲート電極または単位ドレ
イン電極を櫛型にバスバー電極で接続した単位セルと、
同様に構成した隣り合う単位セルの相方の同じ電極どう
しのバスバー電極を抵抗体で電気的に接続したことを特
徴とする高出力電界効果トランジスタ。
1. A unit cell in which a plurality of unit gate electrodes or unit drain electrodes are comb-shaped connected to each other by bus bar electrodes,
A high output field effect transistor, characterized in that bus bar electrodes of the same electrodes on opposite sides of adjacent unit cells having the same structure are electrically connected by a resistor.
JP27788493A 1993-10-08 1993-10-08 High power field-effect transistor Pending JPH07111271A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27788493A JPH07111271A (en) 1993-10-08 1993-10-08 High power field-effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27788493A JPH07111271A (en) 1993-10-08 1993-10-08 High power field-effect transistor

Publications (1)

Publication Number Publication Date
JPH07111271A true JPH07111271A (en) 1995-04-25

Family

ID=17589636

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27788493A Pending JPH07111271A (en) 1993-10-08 1993-10-08 High power field-effect transistor

Country Status (1)

Country Link
JP (1) JPH07111271A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0936669A1 (en) * 1998-02-16 1999-08-18 NEC Corporation Semiconductor device and method of manufacturing the same
WO1999052129A2 (en) * 1998-04-03 1999-10-14 Ericsson Inc. Resistive interconnect of transistor cells
JP2010080815A (en) * 2008-09-29 2010-04-08 Toshiba Corp Semiconductor device
JP2011124365A (en) * 2009-12-10 2011-06-23 Toshiba Corp Method for manufacturing semiconductor device, and semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60200547A (en) * 1984-03-23 1985-10-11 Fujitsu Ltd Semiconductor device
JPH01181574A (en) * 1988-01-12 1989-07-19 Fujitsu Ltd Semiconductor device
JPH03248440A (en) * 1990-02-26 1991-11-06 Nec Corp High output gaas field effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60200547A (en) * 1984-03-23 1985-10-11 Fujitsu Ltd Semiconductor device
JPH01181574A (en) * 1988-01-12 1989-07-19 Fujitsu Ltd Semiconductor device
JPH03248440A (en) * 1990-02-26 1991-11-06 Nec Corp High output gaas field effect transistor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0936669A1 (en) * 1998-02-16 1999-08-18 NEC Corporation Semiconductor device and method of manufacturing the same
US6346728B1 (en) 1998-02-16 2002-02-12 Nec Corporation Plural transistor device with multi-finger structure
US6566185B2 (en) 1998-02-16 2003-05-20 Nec Compound Semiconductor Devices, Ltd. Method of manufacturing a plural unit high frequency transistor
WO1999052129A2 (en) * 1998-04-03 1999-10-14 Ericsson Inc. Resistive interconnect of transistor cells
WO1999052129A3 (en) * 1998-04-03 2000-04-27 Ericsson Inc Resistive interconnect of transistor cells
JP2010080815A (en) * 2008-09-29 2010-04-08 Toshiba Corp Semiconductor device
US8169035B2 (en) 2008-09-29 2012-05-01 Kabushiki Kaisha Toshiba Semiconductor device
JP2011124365A (en) * 2009-12-10 2011-06-23 Toshiba Corp Method for manufacturing semiconductor device, and semiconductor device

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