JP3111969B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, it relates to the structure of a high-output field effect transistor (FET).

[0002]

2. Description of the Related Art Hitherto, such a high-output FET has been known, for example, from Japanese Patent Application Laid-Open No. 8-274116.

FIGS. 5 (a) and 5 (b) are a plan view of a high-power FET for explaining one example of the prior art and its A, respectively.
It is a sectional view taken on the line -A ', BB'. First, as shown in FIG. 5A, a plurality of unit FETs each including a source finger electrode 41, a gate finger electrode 51, and a drain finger electrode 31 are provided in an active region 101 formed on the surface of a semiconductor substrate 100. I have. This semiconductor substrate 1
00 is, for example, n-type GaAs on a semi-insulating GaAs substrate.
What formed the layer is used.

The arrangement of each finger electrode in these unit FETs has a repeating structure. The drain finger electrode 31 is followed by the gate finger electrode 51 and the source finger electrode 41, and further, the gate finger electrode 51 and the drain finger electrode 31 are arranged. Are arranged in a cycle such as Each drain finger electrode 31 is connected via a drain bus bar 32 to a drain electrode pad 33 for connecting a bonding line (not shown). Each source finger electrode 41 is connected to a source electrode pad 43. These drain finger electrodes 31
The source finger electrode 41 is connected to the pads 33 and 43, respectively, thereby forming a comb-like structure and facing each other. On the other hand, the gate finger electrodes 51 are connected by a gate bus bar 52, and are connected to the same number of gate electrode pads 53 as the drain electrode pads 33 through the gate lead lines 54. The source electrode pad 43 is connected to the semiconductor substrate 1.
In order to connect the front surface portion and the backside conductor layer, the metal layer 62 in the via hole 61 penetrating the substrate is connected to the backside conductor layer and grounded.

In short, in the electrode structure of such a high-output FET, the position of the gate lead line 54 is arranged so as to face the center position of the drain electrode pad 33 with the active region 101 interposed therebetween (one-to-one correspondence). Further, the position of the gate lead line 54 is arranged at a position facing the drain finger electrode 31.

Next, as shown in FIG. 5 (b), the cross section of the high-power FET shows the semiconductor substrate 10 described above.
N provided on a semi-insulating GaAs substrate 103 for forming 0
The source finger electrode 41 formed on the GaAs layer 104 is an actual ground plane via the source electrode pad 43, the via hole 61 formed in the substrate, and the second metal layer 62 provided therein. It is connected to the first metal layer 70 on the back surface of the substrate.

When the distance from the first metal layer 70 is large, the electrode 41 has a sufficient source inductance to cause parasitic oscillation in the millimeter wave band. For this reason, in the above-mentioned Japanese Patent Application Laid-Open No. Hei 8-274116, in order to reduce the source inductance,
Source electrode pad 43 is arranged between gate electrode pad 53 and active region 101. Thus, the source inductance is sufficiently reduced, the amount of series feedback due to the source inductance of the unit FET is reduced, and the parasitic oscillation is suppressed.

However, in a high output FET,
In addition to the above-described modes, there is a mode in which a large number of unit FETs are arranged in parallel in order to obtain a large output, so that a synchronization phenomenon between the FETs causes millimeter wave oscillation.

FIG. 6 is a schematic diagram for explaining the mechanism of millimeter wave parasitic oscillation in a conventional high-output FET. As shown in FIG. 6, a high-output FET schematically shown is:
A plurality of unit FETs 201 are connected in parallel by a source bus bar 242, a drain bus bar 232, and a gate bus bar 252.

Here, for millimeter waves, each unit FET
Since the phase difference between them becomes sufficiently large, one unit FET 2
The oscillation signal at the drain electrode of No. 01 has a phase at the oscillation frequency, and is Fπ apart by nπ (n = 1, 2, 3,...).
Between the ETs, the phases are reversed or in-phase, and are synchronized. That is, as compared with the unit FET, the threshold value of the oscillation is lowered by the incident signal from another FET. Therefore, since a large number of unit FETs are regularly distributed, the whole FET group connected in parallel eventually synchronizes to form a standing wave. Since the end of each bus bar is open, usually the outermost unit F
Oscillation will occur under the condition that ET is an antinode and n = 1, 2, 3,...

The oscillation frequency at this time depends on the size of the FETs connected in parallel, and is determined by the connection pitch and the capacitance of the unit FET for one finger connected. That is, the fundamental frequency is determined by the size of the electrode of the FET and the gate width that determines the capacitance of the FET.

FIGS. 7A and 7B show conventional Ga.
It is a characteristic diagram of the number of gate fingers and an oscillation frequency, and a characteristic diagram of a gate finger length and an oscillation frequency in an AsMESFET. As shown in FIG. 7A, in a GaAs MESFET having a gate length of 0.5 μm and a gate pitch of 20 μm, when the gate finger length is fixed to two types of 80 μm and 125 μm, the basic oscillation The measured value of the frequency (lowest frequency) GHz dependence on the number of gate fingers is shown. This indicates that the oscillation frequency changes in inverse proportion to the square root of the total gate width, that is, the number of gate fingers, corresponding to the change in the capacitance value described above.

Next, as shown in FIG. 7B, this characteristic is a fundamental oscillation frequency characteristic when the number of gate fingers is fixed to 12 and the gate finger length is changed. Similarly to 7 (a), it changes in inverse proportion to the square root of the total gate width, that is, the gate finger length.

FIGS. 8A and 8B respectively show FIGS.
FIG. 2 is an enlarged plan view of a gate lead line and an equivalent circuit diagram thereof. As shown in FIG. 8A, a gate lead line (length L1) 54 is connected to the gate bus bar on the A side, and a gate electrode pad (length L2, width W) 53 on the opposite side. And intersects with the source electrode pad 43 in an air bridge structure.

As shown in FIG. 8B, the equivalent circuit viewed from the side A connected to the gate bus bar has a lead line portion divided into two areas, and the capacitance value of the air bridge portion is 30 fF (femto・ Farad).

FIG. 9 is a characteristic diagram of the length of the lead line and the short-circuit frequency when the length and width of the gate electrode pad in FIG. 8 are fixed. As shown in FIG. 9, this characteristic is such that the length L2 of the gate electrode pad 53 is 80 μm (μm), the width W is 80 μm, the capacitance value of the air bridge is 30 fF, and the thickness of the GaAs substrate forming the semiconductor substrate is When L is set to 50 microns, the L1 (lead line length) dependence of the frequency at which a short-circuit occurs when viewed from the plane A in FIG. In particular, when the frequency at which a short circuit occurs in the electrode structure composed of the lead line and the gate electrode pad is close to the spatial period of oscillation determined by the interval between the gate lead lines shown in FIG. 6, the oscillation threshold is low, that is, Oscillation is likely to occur.

However, since a normal high-output FET has an optimal pattern design with respect to the fundamental wave, the position of the gate lead line is not optimized with respect to oscillation. This will lower the threshold value of the parasitic oscillation.

As described with reference to FIG. 5, in the ordinary high-output FET, the position of the gate lead line 54 is set to the active region 101 with respect to the center position of the drain electrode pad 33.
Are arranged so as to directly oppose each other (corresponding to one-to-one), and the position of the gate lead line 54 is located just opposite to the drain finger electrode 31. The number of the gate finger electrodes 51 is [4n-2] (n = 1, 2, 3,...).
・), And restrictions on the pattern arrangement have also arisen.

[0019]

In the above-mentioned conventional high-output FET, a plurality of unit finger electrodes are connected in parallel in the lateral direction, and the drain electrode pad and the gate lead line are completely opposed to each other in one-to-one correspondence. Therefore, there is a disadvantage that the oscillations between a plurality of FETs connected in parallel are synchronized. In other words, because a large number of other FETs connected in parallel in the horizontal direction are regularly distributed, a standing wave that oscillates using the entire FET pattern as a resonator is generated. In addition, the structure of the gate electrode pad and the gate lead line works to further enhance the oscillation conditions.

Further, in the conventional high-output FET, the position of the gate lead line is adjusted to the center position of the drain electrode pad and the position of the drain finger electrode.

An object of the present invention is to provide a semiconductor device capable of improving reliability by suppressing the above-described millimeter wave parasitic oscillation and improving the design of a gate lead line.

[0022]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor substrate for forming an active region on a front surface portion and forming a first conductor layer on a back surface, and connecting the front surface portion and the back surface via holes, and alternately on the active region of the semiconductor substrate; A plurality of drain finger electrodes and a plurality of source finger electrodes arranged one by one, and one each of the plurality of drain finger electrodes and the plurality of source finger electrodes are arranged between adjacent drain finger electrodes and the source finger electrodes. A plurality of gate finger electrodes, a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes, and the plurality of drain electrode pads opposite to each other across the active region. Gate bus bar arranged on the side and connecting the plurality of gate finger electrodes And a plurality of source electrode pads arranged farther from the active region than the gate bus bar and connecting the plurality of source finger electrodes, and separated from the gate bus bar so as to sandwich the plurality of source electrode pads therebetween. A plurality of gate electrode pads arranged,
In connecting the gate bus bar and the plurality of gate electrode pads, the plurality of gate electrode lines have a plurality of gate lead lines connected in a number different from the number of the plurality of drain electrode pads, and the plurality of source electrode pads and the plurality of The semiconductor substrate is configured by connecting the first conductor layer with a second conductor layer formed in the via hole.

Each of the plurality of gate lead lines in the semiconductor device is connected to one or more gate electrode pads, and a distance between the one or more gate electrode pads is different from a distance between the plurality of drain electrode pads. Formed.

In addition, the semiconductor device of the present invention has a semiconductor substrate in which an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via a via hole. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the active region of the semiconductor substrate, and an adjacent drain finger electrode among the plurality of drain finger electrodes and the plurality of source finger electrodes And a plurality of gate finger electrodes each arranged between the source finger electrodes, a plurality of drain electrode pads disposed outside the active region and connecting the plurality of drain finger electrodes, and the active region. Are arranged on the opposite side of the plurality of drain electrode pads with the A gate bus bar connecting the finger fingers; a plurality of source electrode pads arranged farther from the active region than the gate bus bar and connecting the plurality of source finger electrodes; A plurality of gate electrode pads disposed apart from the gate bus bar, and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads, the plurality of source electrode pads and the semiconductor The first conductor layer of the substrate is connected by a second conductor layer formed in the via hole, and a connection position of the plurality of gate leads to the gate bus bar is determined by the plurality of drain finger electrodes and the plurality of drain finger electrodes. It is configured differently from the position facing the gate bus bar.

Further, the semiconductor device of the present invention has a semiconductor substrate in which an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via a via hole. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the active region of the semiconductor substrate, and an adjacent drain finger electrode among the plurality of drain finger electrodes and the plurality of source finger electrodes And a plurality of gate finger electrodes each arranged between the source finger electrodes, a plurality of drain electrode pads disposed outside the active region and connecting the plurality of drain finger electrodes, and the active region. Are arranged on the opposite side of the plurality of drain electrode pads with the A gate bus bar connecting the plurality of source finger electrodes, a plurality of source electrode pads arranged farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and the plurality of source electrode pads interposed therebetween. A plurality of gate electrode pads disposed apart from the gate bus bar, and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads, and having a gate width of Wg (m
m), the basics determined by the gate width
The oscillation frequency [68 × (square root of Wg) GHz], the plurality of gate lead lines and the plurality of gate electrode pads;
Frequency impedance is ing and short as seen from the joint location <br/> of said gate bus bar electrode structure consisting of soil one
It is configured to prevent millimeter wave parasitic oscillation .

The semiconductor device according to the present invention may further comprise a semiconductor substrate having an active region formed on a front surface portion and a first conductor layer formed on a back surface, and connecting the front surface portion and the back surface via a via hole. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the active region of the semiconductor substrate, and an adjacent drain finger electrode among the plurality of drain finger electrodes and the plurality of source finger electrodes And a plurality of gate finger electrodes each arranged between the source finger electrodes, a plurality of drain electrode pads disposed outside the active region and connecting the plurality of drain finger electrodes, and the active region. Are arranged on the opposite side of the plurality of drain electrode pads with the A gate bus bar connecting the finger fingers; a plurality of source electrode pads arranged farther from the active region than the gate bus bar and connecting the plurality of source finger electrodes; A plurality of gate electrode pads arranged apart from the gate bus bar, and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads. The frequency at which the impedance of the electrode portion formed of each of the gate electrode pads becomes short when viewed from the junction with the gate bus bar is determined as the fundamental oscillation frequency determined from the gate width Wg (mm) per gate lead line [ 68 × nature of (the square root of the Wg) GHz]
The frequency is configured to be different from a multiple of the square root of the number .

The semiconductor device according to the present invention may further comprise a semiconductor substrate having an active region formed on a front surface portion and a first conductor layer formed on a back surface, and connecting the front surface portion and the back surface via a via hole. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the active region of the semiconductor substrate, and an adjacent drain finger electrode among the plurality of drain finger electrodes and the plurality of source finger electrodes And a plurality of gate finger electrodes each arranged between the source finger electrodes, a plurality of drain electrode pads disposed outside the active region and connecting the plurality of drain finger electrodes, and the active region. Are arranged on the opposite side of the plurality of drain electrode pads with the A gate bus bar connecting the finger fingers; a plurality of source electrode pads arranged farther from the active region than the gate bus bar and connecting the plurality of source finger electrodes; A plurality of gate electrode pads arranged apart from the gate bus bar, and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads, and a gate width per gate lead line Is defined as wg (mm) , the frequency at which the impedance of the electrode portion composed of each of the plurality of gate lead lines and the plurality of gate electrode pads is short-circuited when viewed from the connection surface with the gate bus bar is 10
It is configured to be 0 / (square root of wg) GHz or more.

[0028]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of an electrode portion on a substrate in a high-output FET for explaining an embodiment of the present invention. As shown in FIG. 1, this embodiment mainly shows an electrode portion on a substrate, and the substrate and its cross-sectional structure are the same as those in FIGS. 5A and 5B of the conventional example described above. The display is omitted. Therefore, also in the present embodiment, the active region 101 is formed on the surface of the GaAs substrate.
And a GaAs MESFET composed of a drain finger electrode, a source finger electrode, and a gate finger electrode for forming the first conductor layer 70 on the back surface and connecting the front surface portion and the back surface via the via hole 61.

On the active region 101, a plurality of drain finger electrodes 31 and a plurality of source finger electrodes 41 are provided.
A gate finger electrode 51 is provided between the drain finger electrode 31 and the source finger electrode 41, which are adjacent to each other. Further, the drain bus bar 32 is provided outside the active region 101.
A plurality of drain electrode pads 33 for connecting the drain finger electrodes 41 through the holes are formed. In the drain electrode pad 33, one for every six gate finger electrodes 51 is formed. Further, active region 1
A gate bus bar 52 for connecting a gate finger electrode 51 on the opposite side of the drain electrode pad 33 with respect to the gate bus bar 01, and the active region 10
1 and a source finger electrode 4
1 and a plurality of source electrode pads 43 for connecting the gate busbars 5 with the source electrode pad 43 interposed therebetween.
A plurality of gate electrode pads 53 distant from 2 are arranged. The gate bus bar 52 and the gate electrode pad 53
Are connected by the number of gate lead lines 54 different from the number of the drain electrode pads 33.

The above-described high-output FET has such electrode structures and arrangements, and the source electrode pad 4
3 and a first metal layer formed on the back surface of the semiconductor substrate are connected by a second metal layer 62 in a via hole 61 formed in the substrate, and the first metal layer is grounded.

Here, the high output FE in the present embodiment
The difference between T and the conventional example of FIG. 5 described above is as follows. In this embodiment, the gate lead line 54 is
3 is a point which is not formed so as to correspond, and which is not paired. In the present embodiment, the gate lead line 54 is not located at a position corresponding to the drain finger electrode 31.

FIG. 2 is an enlarged plan view of the electrode portion on the substrate in which the drain electrode pad side is omitted from the central portion on the active region in FIG. As shown in FIG. 2, the distance between the adjacent gate lead lines 54 is formed independently of the repetition period of the gate electrode pad 53 and the repetition period of the drain finger electrode 31, and is set under the condition that the millimeter wave parasitic oscillation frequency does not occur. It is arbitrarily changed. That is, the distance between the gate lead lines 54 is important, and two gate electrode pads 53 may be provided for one gate lead line 54. Hereinafter, the distance (interval) between the gate lead lines 54 will be described with reference to FIG.

FIG. 3 is an enlarged plan view of the electrode portion on the substrate, similar to FIG. 2, for explaining the method of determining the lead line interval in FIG. As shown in FIG. 3, this electrode portion is an example in which the position and the interval of the gate lead line 54 are changed as compared with the above-described electrode portion of FIG. 2, and the interval between the gate electrodes 53 is also different. Here, the impedance of the electrode structure composed of the gate lead line 54 and the gate electrode pad 53 as viewed from the A side is considered.

In determining the length L1 of the lead line in FIG.
80 μm × formed on a GaAs substrate having a thickness of 0 μm
For a gate pad electrode 53 having a size of 100 μm, 20
The relationship between the length L1 of the gate lead line 54 having a width of μm and the frequency at which the impedance appears to be short-circuited is shown. From this relationship, it can be seen that, in the present embodiment, when the length L1 of the gate lead-out line 54 is 150 μm, the frequency becomes short at 71 GHz.

The equivalent circuit is as shown in FIG.

FIG. 4 is a characteristic diagram showing the relationship between the fundamental oscillation frequency and the gate width when the lead line spacing is determined in FIG. As shown in FIG. 4, this characteristic indicates the relationship between the fundamental oscillation frequency and the gate width. At the gate width of 0.92 mm, the short-circuit frequency f described above occurs. At this time, when the length of the gate finger electrode 51 is 90 μm, for example, if one gate lead line 54 is formed for every ten gate finger electrodes 51, the oscillation threshold value is lowered, and the millimeter wave transmission is easily performed. Occur. Also, when the period is selected as an integral multiple of the gate width of 0.92 mm,
The oscillation threshold will be reduced.

In such a case, in order to suppress the oscillation, the interval between the gate lead lines 54 is changed, and the gate width per one of the gate lead lines 54 is set to a period different from an integral multiple of 0.92 mm. There is a need. However, according to the structure of the present embodiment, the position of the gate lead line 54 can be arbitrarily selected, so that the parasitic oscillation of the millimeter wave can be easily suppressed.

Next, another embodiment of the present invention will be described.
This will be described with reference to FIGS. 3 and 4 described above. In the above-described embodiment, the main focus has been to prevent the fundamental oscillation frequency based on the gate width from coincident with the frequency at which the impedance viewed from the A side of the gate lead line becomes short-circuited.

However, as described above, there is a possibility that oscillation may actually occur at a different number of nodes from the fundamental oscillation frequency.
That is, in such a case, since the oscillation frequency is inversely proportional to the square root of the gate width, there is a possibility that a frequency which is square root times n (n = 1, 2, 3,...) With respect to the basic oscillation frequency of the unit gate width is generated. There is. However, since there is a limit to the frequency at which the high-output FET can amplify, normally, if the gate lead line is designed to have a frequency of twice or more, the oscillation threshold will not be significantly reduced.

That is, in FIG. 3, the frequency at which the impedance viewed from the A side is short-circuited to the fundamental oscillation frequency corresponding to the total gate width of the gate finger electrode 51 covered by one gate lead line 54 is 2 The gate lead line length L1 may be shortened so that the frequency becomes equal to or more than the square root of, and preferably equal to or more than the square root of 3.

As is clear from FIG. 4 described above, f =
From the equation of 68 × (Wg) -0.5, to make the frequency at the unit gate width twice or more cycle, about 100 (Wg) -0.5 (G
Hz) or more than three times the period,
(Wg) -0.5 (GHz) or more.

Based on these facts, referring to FIG. 4 and the relationship between the frequency at which the lead line 54 becomes short-circuited and the lead line length L1 (see FIG. 9 described above), when the unit gate width Wg is 1.2 mm, , The basic oscillation frequency is 91G
Hz or more, that is, the gate lead line length L1 is 91 μm
It is necessary to: If possible, this frequency should be 109
GHz or more, that is, the gate lead line length L1 is 60 μm.
m or less.

In short, in the above-described two embodiments, the position of the gate lead line is set to a distance different from the spatial distance of the oscillation standing wave pattern. The gate lead line is arranged at a position different from the positional relationship of FIG. Another object of the present invention is to make the frequency at which the electrode pattern including the gate lead line and the gate electrode pad is short-circuited a sufficiently large value as compared with the oscillating frequency determined by the gate width per lead line. .

That is, in the present invention, by forming the position of the gate lead line irrespective of the position of the drain electrode pad, it is easy to suppress the millimeter wave parasitic oscillation.

However, as shown in FIGS. 7A and 7B, the oscillation frequency of the millimeter wave of the FET is almost determined by the entire gate width and can be measured. Also, the unique fundamental oscillation frequency is a frequency similarly determined from FIGS. 7A and 7B with respect to the gate width per gate lead line, and thus the electrode composed of the gate lead line and the gate electrode pad is used. When the frequency at which the impedance is short-circuited as viewed from the surface A of the pattern is close to the fundamental oscillation frequency, or n (n = 1, 2, 3) of the fundamental oscillation frequency
..), The oscillation threshold is significantly reduced.

However, in the present invention, since the gate lead-out line is provided at a distance different from the spatial distance of the steady oscillation pattern, the oscillation standing wave can be suppressed without lowering the oscillation threshold.

[0048]

As described above, according to the present invention, since the position of the gate lead line can be freely selected, a structure capable of suppressing the parasitic oscillation can be easily realized, and the reliability can be improved. There is.

According to the present invention, the electrical characteristics of the gate lead lines and the gate electrode pads can be set without lowering the threshold value of the millimeter wave parasitic oscillation, so that the degree of freedom in design can be improved. This has the effect.

[Brief description of the drawings]

FIG. 1 is a plan view of an electrode portion on a substrate in a high-output FET for explaining an embodiment of the present invention.

FIG. 2 is an enlarged plan view of an electrode portion on a substrate in which a drain electrode pad side is omitted from a center portion on an active region in FIG. 1;

FIG. 3 is an enlarged plan view of an on-substrate electrode portion similar to FIG. 2 for explaining a method of determining a lead line interval in FIG. 1;

FIG. 4 is a characteristic diagram showing a relationship between a fundamental oscillation frequency and a gate width in determining a lead line interval in FIG.

FIG. 5 is a diagram illustrating a plane of a high-output FET and a cross section taken along line AA ′ and BB ′ thereof for explaining an example of the related art.

FIG. 6 is a schematic diagram for explaining a mechanism of parasitic oscillation of a millimeter wave in a conventional high-output FET.

FIG. 7 is a diagram showing characteristics of the number of gate fingers and an oscillation frequency, and characteristics of a gate finger length and an oscillation frequency in a conventional GaAs MESFET.

8 is a diagram illustrating an enlarged plane of a gate lead line in FIG. 5 and an equivalent circuit thereof.

FIG. 9 is a characteristic diagram showing the relationship between the length of a lead line and the frequency of a short circuit when the length and width of a gate electrode pad are fixed in FIG.

[Explanation of symbols]

 Reference Signs List 31 drain finger electrode 32 drain bus bar 33 drain electrode pad 41 source finger electrode 43 source electrode pad 51 gate finger electrode 52 gate bus bar 53 gate electrode pad 54 gate lead line 61 via hole 62 second metal layer 70 first metal layer 100 Semiconductor substrate 101 active region

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/337 H01L 21/338 H01L 27/095 H01L 29/778 H01L 29/80 H01L 29/808 H01L 29 / 812

Claims (6)

(57) [Claims] A semiconductor substrate for forming an active region on a front surface portion and forming a first conductor layer on a back surface, and connecting the front surface portion and the back surface via a via hole; A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the region, and a plurality of drain finger electrodes and a plurality of source finger electrodes, respectively, between the adjacent drain finger electrodes and the source finger electrodes among the plurality of drain finger electrodes and the plurality of source finger electrodes; A plurality of gate finger electrodes arranged to one; a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes; and the plurality of drains sandwiching the active region. An electrode pad is disposed on the opposite side and connects the plurality of gate finger electrodes. A gate bus bar, a plurality of source electrode pads disposed farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and a plurality of source electrode pads from the gate bus bar so as to sandwich the plurality of source electrode pads. A plurality of gate electrode pads arranged apart from each other, and a plurality of gate lead lines connected by a number different from the number of the plurality of drain electrode pads in connecting the gate bus bar and the plurality of gate electrode pads. Wherein the plurality of source electrode pads and the first conductor layer of the semiconductor substrate are connected by a second conductor layer formed in the via hole. 2. Each of the plurality of gate leads is
2. The semiconductor device according to claim 1, wherein said semiconductor device is connected to one or more gate electrode pads, and an interval between said one or more gate electrode pads is different from an interval between said plurality of drain electrode pads. 3. A semiconductor substrate, wherein an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via via holes. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the region, and a plurality of drain finger electrodes and a plurality of source finger electrodes, respectively, between the adjacent drain finger electrodes and the source finger electrodes among the plurality of drain finger electrodes and the plurality of source finger electrodes; A plurality of gate finger electrodes arranged to one; a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes; and the plurality of drains sandwiching the active region. An electrode pad is disposed on the opposite side and connects the plurality of gate finger electrodes. A gate bus bar, a plurality of source electrode pads disposed farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and a plurality of source electrode pads from the gate bus bar so as to sandwich the plurality of source electrode pads. A plurality of gate electrode pads arranged apart from each other, and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads, wherein the plurality of source electrode pads and the first of the semiconductor substrate are provided. A second conductor layer formed in the via hole;
And the connecting position of the plurality of gate leads to the gate bus bar is different from the position facing the plurality of drain finger electrodes and the gate bus bar. Characteristic semiconductor device. 4. A semiconductor substrate, wherein an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via via holes. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the region, and a plurality of drain finger electrodes and a plurality of source finger electrodes, respectively, between the adjacent drain finger electrodes and the source finger electrodes among the plurality of drain finger electrodes and the plurality of source finger electrodes; A plurality of gate finger electrodes arranged to one; a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes; and the plurality of drains sandwiching the active region. An electrode pad is disposed on the opposite side and connects the plurality of gate finger electrodes. A gate bus bar, a plurality of source electrode pads disposed farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and a plurality of source electrode pads from the gate bus bar so as to sandwich the plurality of source electrode pads. A plurality of gate electrode pads spaced apart from each other, and a plurality of gate lead lines connecting the gate bus bars and the plurality of gate electrode pads, wherein the gate width is Wg (mm);
[68 × (Wg flat)
GHz), the plurality of gate lead lines and the front
Serial impedance as viewed from the junction location and a plurality of said gate bus bar electrode structure composed of the gate electrode pad so as not to match the short and ing frequency, millimeter Namiyose
A semiconductor device for preventing raw oscillation . 5. A semiconductor substrate, wherein an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via via holes. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the region, and a plurality of drain finger electrodes and a plurality of source finger electrodes, respectively, between the adjacent drain finger electrodes and the source finger electrodes among the plurality of drain finger electrodes and the plurality of source finger electrodes; A plurality of gate finger electrodes arranged to one; a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes; and the plurality of drains sandwiching the active region. An electrode pad is disposed on the opposite side and connects the plurality of gate finger electrodes. A gate bus bar, a plurality of source electrode pads disposed farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and a plurality of source electrode pads from the gate bus bar so as to sandwich the plurality of source electrode pads. A plurality of gate electrode pads disposed apart from each other; and a plurality of gate lead lines connecting the gate bus bar and the plurality of gate electrode pads, each of the plurality of gate lead lines and the plurality of gate electrode pads being provided. The frequency at which the impedance, as viewed from the junction of the electrode portion consisting of the gate bus bar and the gate bus bar, becomes short is determined by the gate width Wg per gate lead line.
(Mm), the fundamental oscillation frequency [68 × (Wg
A frequency which is different from a multiple of the square root of a natural number of [square root of GHz] . 6. A semiconductor substrate, wherein an active region is formed on a front surface portion and a first conductor layer is formed on a back surface, and the front surface portion and the back surface are connected via via holes. A plurality of drain finger electrodes and a plurality of source finger electrodes alternately arranged on the region, and a plurality of drain finger electrodes and a plurality of source finger electrodes, respectively, between the adjacent drain finger electrodes and the source finger electrodes among the plurality of drain finger electrodes and the plurality of source finger electrodes; A plurality of gate finger electrodes arranged to one; a plurality of drain electrode pads arranged outside the active region and connecting the plurality of drain finger electrodes; and the plurality of drains sandwiching the active region. An electrode pad is disposed on the opposite side and connects the plurality of gate finger electrodes. A gate bus bar, a plurality of source electrode pads disposed farther from the active region than the gate bus bar, and connecting the plurality of source finger electrodes, and a plurality of source electrode pads from the gate bus bar so as to sandwich the plurality of source electrode pads. A plurality of gate electrode pads disposed apart from each other, and a plurality of gate lead lines connecting the gate bus bar and the gate electrode pads, and a gate width per gate lead line is defined as wg (m
m) , the frequency at which the impedance of the electrode portion formed of each of the plurality of gate lead lines and the plurality of gate electrode pads is short-circuited when viewed from the connection surface with the gate bus bar is 100 / (square root of wg). ) GHz
A semiconductor device characterized by the above.