JPS629661A - Monolithic integrated circuit - Google Patents
Monolithic integrated circuitInfo
- Publication number
- JPS629661A JPS629661A JP14862385A JP14862385A JPS629661A JP S629661 A JPS629661 A JP S629661A JP 14862385 A JP14862385 A JP 14862385A JP 14862385 A JP14862385 A JP 14862385A JP S629661 A JPS629661 A JP S629661A
- Authority
- JP
- Japan
- Prior art keywords
- conductive layer
- monolithic integrated
- integrated circuit
- output terminal
- inductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はモノリシック集積回路に関し、特にマイクロ波
用のモノリシック集積回路に関するＯ〔従来の技術〕
−
従来、この種のモノリシック集積回路は、第５図に示す
ように、２個のＦＥＴ３１．３２と、ＦＥＴ３１．３２
それぞれの負荷抵抗３３．３４と、ＦＥＴ３１の帰還抵
抗３５と、２個の直流カット用のキャパシタ３６．３７
と、ピーキング用のインダクタ３８とを備える。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to monolithic integrated circuits, and in particular to monolithic integrated circuits for microwave applications. [Prior Art]
- Traditionally, this type of monolithic integrated circuit has two FETs 31.32 and 31.32, as shown in FIG.
Each load resistance 33.34, feedback resistance 35 of FET 31, and two DC cut capacitors 36.37
and an inductor 38 for peaking.
従来のモノリシック集積回路では、通常キャノ（シタ３
６．３７は酸化シリコン又は窒化シリコンを絶縁体とし
た平行平板キャノ（シタによシ構成される。また、イン
ダクタ３８は大きなインダクタンスを得るため螺旋状に
形成されるＯ
このようなモノリシック集積回路を低周波まで動作させ
るためには、キャパシタ３６．３７の容量値を大きくす
る必要があシ、これらの形成に大面積を要する。In conventional monolithic integrated circuits, it is usually
6.37 is composed of a parallel flat plate made of silicon oxide or silicon nitride as an insulator. Also, the inductor 38 is formed in a spiral shape to obtain a large inductance. In order to operate at low frequencies, it is necessary to increase the capacitance value of the capacitors 36 and 37, and a large area is required to form them.
さらに、インダクタ３８の占める面積も大難くなり、通
常この糧のモノリシック集積回路のテ。Furthermore, the area occupied by the inductor 38 becomes very difficult, which is usually the case for monolithic integrated circuits.
プ面積の大部分はキャパシタとインダクタとで占められ
る。Most of the tap area is occupied by capacitors and inductors.
上述した従来のモノリシック集積回路は、チップ面積が
大きくなるので、高価になるという欠点がある。The above-mentioned conventional monolithic integrated circuit has the disadvantage of being expensive due to its large chip area.
本発明の目的は、低価格のモノリシック集積回路を提供
することにある０
〔問題点を解決するだめの手段〕
本発明の第１の発明のモノリシック集積回路は、基板上
に設ける螺旋状の第１の導電層と、該第１の導電層の上
ＫＭける絶縁体層と、該絶縁体層を介して前記第１の導
電層の上部に設ける螺旋状の第２の導電層と、前記第１
の導電層の両端に設ける入力端子および出力端子と、前
記第２の導電層の両端に設ける入力端子および出力端子
とを含んで構成される。SUMMARY OF THE INVENTION An object of the present invention is to provide a low-cost monolithic integrated circuit. a second conductive layer, an insulating layer disposed above the first conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer; 1
The second conductive layer includes an input terminal and an output terminal provided at both ends of the conductive layer and an input terminal and an output terminal provided at both ends of the second conductive layer.
本発明の第２の発明のモノリシック集積回路は、基板上
に設ける螺旋状の＠１の導電層と、該Ｊ＠１の導電層の
上に設ける絶縁体層と、該絶縁体層を介して前記第１の
導電層の上部に設ける螺旋状の第２の導電層と、前記第
１の導電層の両端に設ける入力端子および出力端子と、
前記第２の導電層の両端に設ける入力端子および出力端
子と、少なくとも１個のトランジスタとを含んで構成さ
れる◎〔実施例〕
久に１本発明の実施例について図面を参照して説明する
〇
第１図は本発明の第１の発明の一実施例を示す平面図、
第２図は第１図に示す実施例のＡ−Ａ’線断面図である
。A monolithic integrated circuit according to a second aspect of the present invention includes a spiral conductive layer @1 provided on a substrate, an insulator layer provided on the conductive layer J@1, and a spiral second conductive layer provided above the first conductive layer; an input terminal and an output terminal provided at both ends of the first conductive layer;
◎ [Embodiment] The first embodiment of the present invention will be described with reference to the drawings. 〇Figure 1 is a plan view showing an embodiment of the first invention of the present invention,
FIG. 2 is a sectional view taken along line AA' of the embodiment shown in FIG.
第１図および第２図に示すように、サファイア等の誘電
体またはＧａＡｓ等の半絶縁性化合物の基板１３上に、
螺旋状の第１の導電層１２を形成し、次に酸化シリコン
又は窒化シリコンの絶縁体層１４を介して導電層１２上
に＠２の導電層１１を形成する。As shown in FIGS. 1 and 2, on a substrate 13 made of a dielectric material such as sapphire or a semi-insulating compound such as GaAs,
A spiral first conductive layer 12 is formed, and then a @2 conductive layer 11 is formed on the conductive layer 12 via an insulating layer 14 of silicon oxide or silicon nitride.
導電層１２と導電層１１とは直流的に分離されていて、
導電層１１の両端にはそれぞれ入力端子１１、Ｎおよび
出力端子１１０Ｕ’ｒが設けられ、導電層１２の両端に
はそれぞれ入力端子１２□、および出力端子１２０ＵＴ
が設けられる。The conductive layer 12 and the conductive layer 11 are separated in terms of direct current,
An input terminal 11, N and an output terminal 110U'r are provided at both ends of the conductive layer 11, and an input terminal 12□ and an output terminal 120UT are provided at both ends of the conductive layer 12, respectively.
will be provided.
このように構成することによシ、導電層１１と導電層１
２とで形成さｎるインダクタの導体の単位長さ当シのイ
ンダクタンスが大きくとれることは良く知られている＠
なお、Ｆ］４Ｔ等の素子を形成する場合には、２層以上
の導電層が用いられるため、本発明の回路素子を形成す
るために特別に工程を増加することなく、通常の工程内
でこのインダクタを形成することが可能でるる。By configuring in this way, the conductive layer 11 and the conductive layer 1
It is well known that the inductance per unit length of the conductor of an inductor formed with 2 and 2 can be large. Since this inductor is used, it is possible to form this inductor within a normal process without adding a special process to form the circuit element of the present invention.
第３図は第１図に示す実施例の等価回路図でめるＯ
第３図に示すように、導電層１１の単位長さ当りのイン
ダクタンス２１、導電層１２０単位長さ当シのインダク
タンス２２、および４ｔＩＥ層１１と導電層１２との層
間の単位良さ当シのキャパシタンス２３によシ、直列の
インダクタンスと直列の中ヤパシタンスとをＭする複合
回路が構成される〇従って、この複合回路の４合インダ
クタンスおよび総合キャパシタンスを所要の値に設定す
ることによシ、前述した従来の回路と同等の特注が得ら
れる。3 is an equivalent circuit diagram of the embodiment shown in FIG. 1. As shown in FIG. 3, the inductance 21 per unit length of the conductive layer 11 and the inductance 22 per unit length of the conductive layer 120 , and a capacitance 23 of the unit thickness between the IE layer 11 and the conductive layer 12, a composite circuit is constructed in which the inductance in series and the capacitance in series are M. Therefore, 4 of this composite circuit By setting the total inductance and total capacitance to the required values, customization equivalent to the conventional circuit described above can be obtained.
第４図は本発明の第２の発明の一実施例を示す回路図で
ｂる。FIG. 4 is a circuit diagram showing an embodiment of the second aspect of the present invention.
第４図において、３９は上記した複合回路を示し、直流
力、ト用のキャパシタを設ける必要がないので、チップ
面積を小さくできる。In FIG. 4, numeral 39 indicates the above-mentioned composite circuit, and since there is no need to provide a capacitor for DC power, the chip area can be reduced.
このキャパシタとインダクタとの複合回路は。This is a composite circuit of a capacitor and an inductor.
本実施例の如く２段増幅器の股間回路に便用されるばか
りでなく、入力回路に用いて整合回路の１部として用い
、入力信号の直流カットを兼ねることもム丁能である。Not only can it be conveniently used in the crotch circuit of a two-stage amplifier as in the present embodiment, but it can also be used in the input circuit as part of a matching circuit to also serve as a DC cut for the input signal.
〔発明の効果〕
以上説明したように本発明のモノリシック集積回路は、
直列にキャパシタを有するインダクタを形成することに
よシ、マイクロ波用のモノリフ。[Effects of the Invention] As explained above, the monolithic integrated circuit of the present invention has the following effects:
Monoriff for microwaves by forming an inductor with a capacitor in series.
り集積回路のチャ１面積を小さくできるので、価格を低
減できるという効果がある０Since the area of the integrated circuit can be reduced, the cost can be reduced.
第１図は本発明の第１の発明の一実施例を示す平面図、
第２図は第１図に示す実施例のＡ−Ａ’線断面図、第３
図は第１図に示す実施例の等価回路図、第４図は禾発明
のｇ２の発明の一実施例を示す回路図、第５図は従来の
モノリフ、り集積回路の一例を示す回路図である。
１１．１２・・・・・・導電層、１３・・・・・・基板
、１４・・・・・・絶縁体層、２１．２２・・・・・・
インダクタンス、２３・・・・・・キャパシタンス、３
１．３２・・・・・・ＦＥＴ、３３゜３４・・・・・・
負荷抵抗、３５・・・・・・湯速抵抗、３６．３７・・
・・・・キャパシタ。
第 １ 図
茅 ＪＩ！ＩFIG. 1 is a plan view showing an embodiment of the first invention of the present invention;
Figure 2 is a sectional view taken along line A-A' of the embodiment shown in Figure 1;
The figure is an equivalent circuit diagram of the embodiment shown in Fig. 1, Fig. 4 is a circuit diagram showing an embodiment of the invention of g2 of the invention, and Fig. 5 is a circuit diagram showing an example of a conventional monoriff integrated circuit. It is. 11.12... Conductive layer, 13... Substrate, 14... Insulator layer, 21.22...
Inductance, 23... Capacitance, 3
1.32...FET, 33°34...
Load resistance, 35... Hot water speed resistance, 36.37...
...Capacitor. Figure 1 Kaya JI! I
Claims (2)
の導電層の上に設ける絶縁体層と、該絶縁体層を介して
前記第１の導電層の上部に設ける螺旋状の第２の導電層
と、前記第１の導電層の両端に設ける入力端子および出
力端子と、前記第２の導電層の両端に設ける入力端子お
よび出力端子とを含むことを特徴とするモノリシック集
積回路。(1) A spiral first conductive layer provided on a substrate;
an insulating layer provided on the conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer, and an input provided at both ends of the first conductive layer. A monolithic integrated circuit comprising a terminal, an output terminal, and an input terminal and an output terminal provided at both ends of the second conductive layer.
の導電層の上に設ける絶縁体層と、該絶縁体層を介して
前記第１の導電層の上部に設ける螺旋状の第２の導電層
と、前記第１の導電層の両端に設ける入力端子および出
力端子と、前記第２の導電層の両端に設ける入力端子お
よび出力端子と、少なくとも１個のトランジスタとを含
むことを特徴とするモノリシック集積回路。(2) a spiral first conductive layer provided on the substrate;
an insulating layer provided on the conductive layer, a spiral second conductive layer provided on top of the first conductive layer via the insulating layer, and an input provided at both ends of the first conductive layer. A monolithic integrated circuit comprising: a terminal and an output terminal; an input terminal and an output terminal provided at both ends of the second conductive layer; and at least one transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14862385A JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14862385A JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS629661A true JPS629661A (en) | 1987-01-17 |
| JPH0569311B2 JPH0569311B2 (en) | 1993-09-30 |
Family
ID=15456924
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14862385A Granted JPS629661A (en) | 1985-07-05 | 1985-07-05 | Monolithic integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS629661A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5384274A (en) * | 1992-04-06 | 1995-01-24 | Nippon Precision Circuits Inc. | Method of making a combined semiconductor device and inductor |
| US5557138A (en) * | 1993-11-01 | 1996-09-17 | Ikeda; Takeshi | LC element and semiconductor device |
-
1985
- 1985-07-05 JP JP14862385A patent/JPS629661A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5384274A (en) * | 1992-04-06 | 1995-01-24 | Nippon Precision Circuits Inc. | Method of making a combined semiconductor device and inductor |
| US5557138A (en) * | 1993-11-01 | 1996-09-17 | Ikeda; Takeshi | LC element and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0569311B2 (en) | 1993-09-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |