JPH0774185A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having an excellent high frequency characteristic and a smaller chip area by forming a first and a second control electrode between a first common electrode and a first output/input electrode and between a second common electrode and a second output/input electrode. CONSTITUTION:One input/output signal and two output/input signals are switched on external signals. In such a semiconductor device, a first common electrode 21 wherein an input/output signal is input/output, a first and a second output/input electrode 24, 25 wherein two output/input signals are output/input, and second common electrodes 22, 23 which are adjacent to the first and the second output/input electrodes 24, 25 respectively are formed on a semiconductor. This semiconductor device also has first control electrodes 27, 28 formed between the first common electrode 21 and the first output/input electrode 24 and between the first common electrode 21 and the second output/input electrode 25 and second control electrodes 26, 29 formed between the second common electrode 22 and the first output/input electrode 24 and between the second common electrode 23 and the second output/input electrode 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device integrated on a semiconductor, and more particularly to a semiconductor device used as a high frequency switch.

[0002]

2. Description of the Related Art Conventionally, this type of high frequency switch has been
For example, a field-effect transistor used as a switching element of a circuit, which is used for switching an antenna of a transceiver in mobile communication in the UHF band to 2 GHz, is 1 GHz.
In order to obtain good high-frequency characteristics such as ensuring low loss at z or more, and considering the withstand pressure in the UHF band, a GaAs-based MESFET (metal is bonded to the gate formation surface and the Schottky barrier is used as the gate electrode). Is often used. Further, as the FET, a FET having a large total gate width is superior in power resistance and distortion resistance as a switch.
ET is mainly used.

FIG. 3 is a conventional circuit diagram showing the structure of this type of high frequency switch.

This high-frequency switch is provided as a monolithic integrated circuit inside the above-mentioned transceiver and has an input / output terminal 1 to which an antenna 3 connected to an external terminal 2 is connected. A high frequency signal is supplied. Further, since the input / output terminal 1 is grounded, for example, via the coil 4, it has a DC ground potential.

Further, the input / output terminal 1 is connected to each source of the MESFETs 5 and 6 provided inside the chip, and the gate of the FET 5 is connected to the control terminal 9 via the resistor 7 and the gate of the FET 6 is connected to the resistor. They are connected to the control terminals 10 via 8, respectively. on the other hand,
The drains of the FETs 5 and 6 are MESFETs 11 and 12 respectively.
Connected to each drain of the
Each gate of 2 is connected to control terminals 10 and 9 via resistors 13 and 14, respectively. FET11,
Each of the 12 sources is grounded.

Also, the drains of the FETs 5 and 6 are turned on / off.
Via output terminals 15 and 16, they are connected to capacitors 17 and 18 for cutting DC components provided outside the chip, respectively, and a receiving section (not shown) is provided on the capacitor 17 side.
However, a transmitter (not shown) is connected to each of the capacitors 18 side.

At the time of reception, the control terminals 9 and 10 are set to "H" level and "L" level, respectively, and
T5 and 12 are turned on, and FETs 6 and 11 are turned off. As a result, the high frequency signal from the antenna 3 is
It is supplied to the receiving unit via the FET 5 and the capacitor 17 via the output terminal 1.

On the other hand, at the time of transmission, the control terminals 9 and 10 are set to the "L" level and the "H" level, respectively, and the FETs 5 and 12 are turned off and the FETs 6 and 11 are turned on. As a result, the high-frequency signal from the transmitter passes through the capacitor 18 and the FET 6 and the input / output terminal 1
To the antenna 3.

The FETs 5, 6, 11, and 12 have low resistance when in the on state and high resistance when in the off state. Among them, the FETs 5 and 6 (hereinafter, referred to as series FETs) that are inserted in series with respect to the transmission path of the high frequency signal allow the high frequency signal to pass in the on state and reflect the signal in the off state. However, since the FET usually has a parasitic capacitance between the source and the drain, when the frequency of the signal increases, the signal passes to some extent by the coupling due to the parasitic capacitance.

FETs 11 and 12 (hereinafter referred to as parallel FETs) inserted in parallel for a high frequency signal.
Is turned on, and the signal is reflected by setting the potential of the signal transmission path to approximately the ground potential. Parallel FET 11,1
When 2 is off, it has almost no effect on the signal.

When the above high-frequency switches are integrated on the same substrate (monolithic integrated circuit), individual FETs are used.
It is possible to achieve overall miniaturization and improvement of high-frequency characteristics, as compared with the case of the above configuration.

[0012]

However, when the high frequency switch is composed of a monolithic integrated circuit,
FETs 5, 6, 11, 12 and resistors 7, 8, 13, 14
And the wiring between the FETs are separately arranged for layout design. Therefore, there is a problem that the chip area is not reduced and the cost is increased. In particular, when a comb-gate FET is used as the series FET and the number of gates is an even number, the problem becomes remarkable.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a semiconductor device having excellent high frequency characteristics and a reduced chip area.

[0014]

In order to achieve the above object, a feature of the present invention resides in a semiconductor device which switches one input / output signal and two output / input signals by an external signal. / First output / input signal
Common electrode and first and second adjacent to the first common electrode, the two output / input signals being respectively output / input.
Output / input electrode, a second common electrode adjacent to each of the first and second output / input electrodes, and between the first common electrode and the first and second output / input electrodes. A first control electrode provided on the semiconductor, and a second control electrode provided between the second common electrode and the first and second output / input electrodes on a semiconductor. .

[0015]

According to the above-described structure, the electrodes (the first common electrode and the first and second output / input electrodes) can be shared by the plurality of FETs forming the semiconductor device.
The chip area can be reduced, and since it can be configured monolithically on a semiconductor, it has excellent high frequency characteristics.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a pattern layout view of a high-frequency switch (semiconductor device) embodying the present invention, and shows the pattern layout of the circuit shown in FIG. 3 described above. The same elements as those in FIG. 3 are designated by the same reference numerals.

The present embodiment is characterized in that the chip area is reduced by adopting a structure in which one FET is divided as follows when a monolithic high frequency switch is manufactured.

This high frequency switch has a semi-insulating Ga
An active layer in which Si is ion-implanted on the As substrate (not shown)
Is provided, and the electrode pattern is arranged on the active layer as follows.

In FIG. 1, a series F is provided at the center of the chip.
Each source electrode (first common electrode) 21 of ET5, 6 is 3
The book is divided into combs and arranged integrally. Part 3
The central part of the comb-shaped book shares both source electrodes 21 in the series FETs 5 and 6, and the upper end of the comb-shaped central part is turned on / off.
The output terminal 1 is configured.

Further, parallel FEs are provided on both sides of the chip.
Source electrodes (second common electrode) 22 of T11 and T12,
23 is a predetermined distance from the source electrode 21 of the series FETs 5 and 6 (dimensions about the same as the comb-shaped distance of the source electrode 21).
Are placed on each side. This parallel FET1
The source electrodes 22 and 23 of 1 and 12 are each divided into two comb shapes, and the outside of each of the two comb shapes is grounded.

Source electrodes 21, 22, 2 of the series FETs 5, 6 and the parallel FETs 11, 12 arranged in this way
Drain electrodes (first and second output / input electrodes) 24 and 25 of the series FETs 5 and 6 and the parallel FETs 11 and 12 are arranged in the six spaced portions of the same size formed by 3. . That is, the drain electrodes 24 and 25 are
Each of them is divided into three comb shapes and integrally formed, and the width dimension thereof is set to be smaller than the interval portion. Of these, the comb-shaped portions of the drain electrode 24 are arranged on the left three of the six spaced portions of the same size formed by the source electrodes 21, 22, and 23, and the drain electrodes are on the right three. There are 25 comb-shaped portions arranged. here,
Source electrodes 21, 22, 23 and drain electrodes 24, 25
The respective gaps formed between and are set to have the same dimensions so that a gate electrode described later can be arranged.

At this time, the source electrode 21 of the FET 5 and the FE
The comb-shaped portion of the drain electrode 24 arranged in the space formed between the source electrode 22 of T11 and the source electrode 22 is
The drain electrode of ET11 is shared. Similarly, FET6
The comb-shaped portion of the drain electrode 25 arranged in the space formed between the source electrode 21 of the FET 12 and the source electrode 23 of the FET 12 shares the drain electrodes of the FET 6 and the FET 12. Then, the drain electrodes 2 formed integrally with each other
Input / output terminals 15 and 16 are provided at the upper ends of 4, 25, respectively.
Make up.

The series FETs 5 and 6 and the parallel FE are
The source electrodes 21, 22, 23 and the drain electrodes 24, 25 of T11, 12 are made of, for example, AuGe / Au layers and have ohmic contacts.

The four FETs 5 arranged as described above
In the gaps formed between the source electrodes 21, 22 and 23 and the drain electrodes 24 and 25 in 6, 11, and 12, gate electrodes (first and second gate electrodes) integrally formed in three comb shapes are formed. Control electrodes) 26, 27, 28, 29 are respectively arranged. Here, the gate electrode 2
6, 27, 28 and 29 are made of, for example, a Ti / Al layer and have a gate width of 1.2 mm per FET,
Moreover, the length of one comb-shaped portion is set to 400 μm. With this, the electric power resistance becomes about 20 dBm.

The resistors 13, 7, 8 and 14 are formed by being connected to the lower end portions of the gate electrodes 26 to 29, respectively. A control terminal 10 is connected to the resistors 13 and 8 and a control terminal 9 is connected to the resistors 7 and 14, respectively, and these control terminals 9 and 10 are arranged at the bottom of the chip.

As described above, in this embodiment, the source electrode 2
The central portion of the comb-shaped portion of 1 shares the source electrodes in the series FETs 5 and 6, and the central portion of the comb-shaped portion of the drain electrode 24 shares the drain electrodes of FET 5 and FET 11,
In addition, the central portion of the comb-shaped portion of the drain electrode 25 shares the drain electrodes of the FET 6 and the FET 12. Therefore, as in the conventional case, the series FETs 5 and 6 and the parallel FETs 11 and 12 are
Then, the chip area can be made considerably smaller than in the case where the resistors 7, 8, 13, 14 and the wiring between the FETs are separately arranged. The chip area according to this embodiment is 2.6 m.
It will be about m ² . Thereby, a low-cost high-frequency switch having excellent high-frequency characteristics can be realized.

As a comparative example of the present invention, without applying the present invention, four FETs 5, 6, 11, 12 and resistors 7, 8,
FIG. 2 shows a pattern layout diagram of the high-frequency switch when the layout is performed by separately arranging the wirings 13 and 14 and the wiring between the FETs.

As shown in the figure, since there is no common portion of the electrodes described in the above embodiment, when the gate width is the same as that of the above embodiment, the chip area is about 3.9 mm ^2, which is the same as that of this embodiment. It is about 1.5 times. For simplification of description, the same elements as those in the above embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

The present invention is not limited to the illustrated embodiment, and various modifications can be made. For example, each electrode may be further divided into combs, and in that case, the number of comb-shaped portions of the gate electrode is odd. And In addition, the source electrode 2 of the parallel FET 11
Although 2 is grounded, it does not have to be grounded.

[0030]

As described above, the first common electrode to which input / output signals are input / output, and the two output / input signals which are adjacent to the first common electrode are respectively output / input. First and second output / input electrodes, a second common electrode adjacent to each of the first and second output / input electrodes, the first common electrode, and the first and second A first control electrode provided between the output / input electrode and a second control electrode provided between the second common electrode and the first and second output / input electrodes. Since it is included on the semiconductor,
The chip area can be significantly reduced, and good high frequency characteristics can be secured. As a result, for example, it is possible to realize a high-frequency switch that is low in cost and has excellent high-frequency characteristics.

[Brief description of drawings]

FIG. 1 is a pattern layout diagram of a high-frequency switch embodying the present invention.

FIG. 2 is a diagram showing a comparative example of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a conventional high frequency switch.

[Explanation of symbols]

 1,15,16 Terminals 5,6 Series FETs 9,10 Control Terminals 11,12 Parallel FETs 21,22,23 Source Electrodes 24,25 Drain Electrodes 26,27,28,29 Gate Electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03K 17/693 A 9473-5J

Claims (1)

[Claims] 1. A semiconductor device for switching one input / output signal and two output / input signals by an external signal, comprising: a first common electrode to which the input / output signal is input / output; A first and a second output / input electrode adjacent to one common electrode and receiving / outputting the two output / input signals; and a first and a second output / input electrode adjacent to the first and second output / input electrodes, respectively. Two common electrodes, a first control electrode provided between the first common electrode and the first and second output / input electrodes, the second common electrode, and the first and second A semiconductor device comprising a second control electrode provided between the two output / input electrodes on a semiconductor.