JPS63193299U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an outline of a memory board according to this invention, Fig. 2 is a circuit diagram showing a specific example of a memory board according to this invention, Fig. 3 is a block diagram showing an outline of a conventional memory board, and Fig. 4 is a block diagram showing an outline of a conventional memory board. The figure is a circuit diagram specifically showing a conventional memory board.

Claims (1)

[Claim for Utility Model Registration] An EPROM, an address buffer, a data buffer, and a control logic circuit are mounted on a board, and an address signal from outside the board is transmitted through the address buffer and further through an address bus. The data applied to the EPROMs and read from these EPROMs is outputted to the outside of the board through the data bus and further through the data buffer,
In a memory board in which a control signal from outside the board is supplied to the control logic circuit and a control signal for selecting the EPROM is supplied through a chip enable line, a write circuit is directly connected to the address bus and led out of the board. an address bus; a write data bus directly connected to the data bus and led out of the board; a write control line directly connected to the chip enable line and led out of the board; An external output enable terminal led out from the output enable terminal to the outside of the board, an external mode control terminal led out to the outside of the board from the mode control terminal of the EPROM, and an address buffer led out to the outside of the board. and a write/read switching terminal that enables each output side of the control logic circuit to be controlled to a high impedance state.