JPS6020658U - information processing equipment - Google Patents
information processing equipmentInfo
- Publication number
- JPS6020658U JPS6020658U JP11001783U JP11001783U JPS6020658U JP S6020658 U JPS6020658 U JP S6020658U JP 11001783 U JP11001783 U JP 11001783U JP 11001783 U JP11001783 U JP 11001783U JP S6020658 U JPS6020658 U JP S6020658U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- circuits
- circuit
- input
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図は本考案実施例装置のブロック構成図。 The figure is a block configuration diagram of an apparatus according to an embodiment of the present invention.
Claims (1)
およびデータ・バスと、 このアドレス・バス上の下位バイトがアドレス入力に接
続され、上記データ・バスがデータ入出力端子に接続さ
れ上記マイクロ・プロセッサによりアドレス指定されて
データ読出しまたは書込みを行うように構成された複数
ｎ個のチップ回路と、上記アドレス・バスの上位バイト
が入力に接続され、上記複数ｎ個のチップ回路の選択信
号を出力するアドレス・デコーダと を備えた情報処理装置において、 上記アドレス・デコーダは、 上記バイトのうちの特定ビットの情報に対応する第一の
制御信号を送出する回路と、 上記上位バイトの全てのビットが「０」であるときに第
二の制御信号を送出する回路と、上記上位バイトのどれ
か１ビツトでも「１」であるときに第三の制御信号を送
出する回路とを備え、 さらに、上記第一の制御信号の反転信号と上記第三の制
御信号を入力とする第一のアンド回路と、上記選択信号
がそれぞれの入力に与えられ、上記第一のアンド回路の
出力がタイミング入力に与えられた複数ｎ個のフリップ
・フロップ回路と、上記選択信号と上記第二の制御信号
とをそれぞれ入力とする複数ｎ個の第一′のオア回路と
、上記フリップ・フロップ回路の出力と上記第一の制御
信号とを入力する複数ｎ個の第二のオア回路と、 上記第一のオア回路の出力と上記第二のオア回路の出力
とをそれぞれの入力とし、それぞれの出力が上記複数ｎ
個のチップ回路の選択信号入力に接続された複数ｎ個の
第二回路と を備えたことを特徴とする情報処理装置。[Claims for Utility Model Registration] A microprocessor, an address bus and a data bus connected to the microprocessor, a lower byte on the address bus being connected to an address input, and a data bus connected to the microprocessor; A plurality of n chip circuits connected to data input/output terminals and configured to read or write data by being addressed by the microprocessor, and an upper byte of the address bus connected to the input, and an address decoder that outputs selection signals for n chip circuits, wherein the address decoder is a circuit that outputs a first control signal corresponding to information of a specific bit of the byte. and a circuit that sends out a second control signal when all bits of the upper byte are "0", and a circuit that sends out a third control signal when any one bit of the upper byte is "1". a first AND circuit which receives the inverted signal of the first control signal and the third control signal; the selection signal is applied to each input; a plurality of n flip-flop circuits whose timing inputs are supplied with the outputs of the AND circuits; and a plurality of n first' OR circuits whose inputs are the selection signal and the second control signal, respectively; a plurality of n second OR circuits inputting the output of the flip-flop circuit and the first control signal; input, and each output is the above plurality n
An information processing device comprising a plurality of n second circuits connected to selection signal inputs of the n chip circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001783U JPS6020658U (en) | 1983-07-15 | 1983-07-15 | information processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11001783U JPS6020658U (en) | 1983-07-15 | 1983-07-15 | information processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6020658U true JPS6020658U (en) | 1985-02-13 |
Family
ID=30256050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11001783U Pending JPS6020658U (en) | 1983-07-15 | 1983-07-15 | information processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6020658U (en) |
-
1983
- 1983-07-15 JP JP11001783U patent/JPS6020658U/en active Pending
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