JPS6319093B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a pulse counting device that counts and displays pulse signals generated in relation to changes in measured quantities such as the running speed and engine speed of vehicles such as automobiles and motorcycles. It is something. [Prior art and its problems] Generally, when displaying a measured quantity using pulses proportional to the measured quantity, pulses proportional to the measured quantity are counted at a gate time set by a reference clock signal, and this counted value is There is known a device that latches and displays a sequentially updated display. In such devices, the updateable time is determined by setting the gate time using the reference clock signal, and the measurement accuracy depends on the density of the number of pulses input within this gate time, but in general, changes in the measured quantity are Increasing the density of pulses proportional to
Not only is the pulse generator quite expensive, but even if it could be provided at a low price, the number of pulses generated within a clock cycle at high speeds would be extremely large, and the capacity of the counter would have to be increased. Overall, the disadvantage was that the device was extremely large and expensive. Another possible method is to lengthen the gate time and relatively increase the number of pulses input within this gate time, but this method has the drawback of not being able to follow sudden changes in the measured quantity. Therefore, generally, as shown in Fig. 1, when a pulse proportional to a change in the measured quantity is input to input terminal 1, counting is performed by counter 2 connected to input terminal 1 and having a counting period. When the counter 2 finishes counting, a plurality of registers, for example, four registers 3a, 3
The count values of the counter 2 are sequentially stored in registers 3a to 3d, and the count values stored in these registers 3a to 3d are added by an adder 4, and a value corresponding to this added value is displayed. To explain the operation of the device shown in Fig. 1 with reference to Fig. 2, when a pulse P proportional to a change in a measured quantity, for example, the running speed, is input, when the counter 2 finishes counting,
At t ₁ , t ₂ , t ₃ , and t ₄ , the numbers of pulses P ₁ , P ₂ , P ₃ , and P ₄ counted in each display switching time, for example, 1 second, are stored in registers 3d, 3c, 3b, and 3a, The stored pulse numbers P ₁ to P ₄ are added by an adder 4, and a display 5 displays a running speed corresponding to the value of (P ₁ +P ₂ +P ₃ +P ₄ ). Here, if the traveling speed suddenly decreases and reaches 0 km/h at _t4 , at the end of counting by counter 2 at _t5 , the number of pulses counted during the new display switching time _t4 to _t5 is _P5 = 0 newly enters the register 3a, and the pulse numbers P ₄ , P ₃ , P ₂ previously stored in the registers 3a, 3b, 3c are sequentially shifted to the registers 3b, 3c, 3d, and the oldest display switching is performed. The number of pulses P ₁ counted from time t ₀ to t ₁ is shifted out of the register, and the running speed corresponding to the value (P ₂ +P ₃ +P ₄ +0) added by the adder 4 is displayed on the display. 5, and the display will show a certain speed value even though the traveling speed has reached 0 km/h. Furthermore, at the end of the next counting, _t6 , the number of pulses P6 = 0 counted during the new display switching time _t5 to _t6 is newly entered into the register 3a, and until then the pulse number _P6 = 0 is entered in the register 3a,
Number of pulses P ₅ , P ₄ , P ₃ stored in b and 3c
are sequentially shifted to registers 3b, 3c, and 3d, and the number of pulses _P2 counted during the oldest display switching time _t1 to _t2 is shifted out of the register.
The display 5 shows the traveling speed according to the value of (P ₃ +P ₄ +0+0) added by the adder 4, and the display continues to show a certain speed value even though the traveling speed is 0 km/h. . Thereafter, at the end of counting _t7 , the pulse numbers _P3 to _P6 stored in the registers 3a to 3d are shifted in the same manner as described above, and the pulse numbers counted at the oldest display switching time _t2 to _t3 are shifted. Instead of P ₃ being shifted out of the register, the number of pulses P ₇ = 0 counted during the new display switching time t ₆ to _{t 7} enters the register 3a, and the value of (P ₄ +0+0+0) is added by the adder 4. The display 5 shows the traveling speed corresponding to the current speed, and the displayed value has not yet reached 0 km/h. Then, at the end of counting _t8 , the number of pulses _P4 to _P7 stored in the registers 3a to 3d is shifted, and the number of pulses _P4 counted at the oldest display switching time _t3 to _t4 is stored in the register. Number of pulses counted in the new display switching time _t7 to _t8 instead of being shifted out
When P ₈ =0 enters register 3a, register 3a
The sum of ~3d is (0+0+0+0), and the traveling speed displayed for the first time on the display 5 is 0km/
h. As described above, the conventional speedometer using a pulse counting device has the disadvantage that it takes 4 seconds from the time the vehicle actually stops until the display shows 0 km/h, and the tracking performance is poor. [Purpose] The present invention has been made by focusing on the above-mentioned problems, and is to improve the reliability of visual display in a pulse counting device, that is, to
The purpose is to speed up the response to sudden changes in the number of pulses. [Means for Solving the Problems] In order to achieve the above object, the present invention divides the gate time for counting pulses generated in response to changes in the measured quantity into multiple divisions, and divides the gate time into multiple divisions for each elapsed counting time. The number of pulses counted is stored in the first register of the storage unit consisting of a plurality of registers, and thereafter, the new number of pulses counted each time the counting time elapses is stored in the first register.
At the same time, the number of pulses stored in each register is sequentially shifted to the next register, the number of pulses stored in the last register is erased from the memory, and the number of pulses stored in each register is sequentially shifted to the next register. In the pulse counting device configured to display a numerical value, a first comparison is performed to compare a value stored in a first register of the storage unit and a value stored in a second register one stage subsequent to the first register. and the first
A determination unit is configured by at least two comparators including a second comparator that compares the stored value of the register with the stored value of a third register one stage after the second register, and the determination unit Based on the determination, the stored value in the register of the storage section is rewritten with a value corresponding to the stored value of the first register, and the stored value in the storage section is rewritten as a measured quantity corresponding to the latest number of pulses within the divided counting time. It displays a numerical value according to the output value. [Function] The gate time is divided into multiple parts, the pulses generated according to the measured quantity are counted, the change in the number of pulses within the gate time is determined, and based on this determination, the pulses are counted within the gate time and registered as necessary. The memory value stored in the first register is forcibly rewritten and corrected with the value corresponding to the memory value of the first register, and the value corresponding to the corrected result is displayed. The output value of will be a value close to the current pulse generation condition. [Embodiment] FIG. 3 is a block diagram of an embodiment of the present invention, in which 6 is an input terminal for inputting a pulse generated according to the amount measured by a detection section (not shown), and 7 is an input terminal 6. This is a timer that sets the counting time of input pulses, and the counting time is a value obtained by dividing the gate time by an arbitrary integer, and in this embodiment, the time is selected to be 1/4 of the gate time. 8 is a counter that counts the pulses inputted at the input terminal 6 during a set counting time; 9 is a storage unit consisting of a plurality of registers that stores the number of pulses counted by the counter 8; The number is the value of the quotient when the gate time is divided by the counting time, and in this embodiment, four pulses are used. The number is input to the register 9a that stores the number, and the registers 9a, 9b,
The number of pulses stored in 9c is sequentially stored in register 9.
b, 9c, and 9d, and the number of pulses stored in the register 9d is erased from the storage section 9. Reference numeral 10 denotes a determination unit consisting of at least one comparator that determines the change in the number of pulses within the gate time, that is, the state of increase or decrease. In this embodiment, two comparators 10a and 10b are used, and one comparator 10a is The number of pulses stored in the registers 9a and 9b of the storage section 9 is compared, and the other comparator 10
b is designed to compare the numbers of pulses stored in registers 9a and 9c of storage section 9. 11
is an arithmetic unit that rewrites the contents of the pulse number stored in the storage unit 9 as necessary based on the judgment of the judgment unit 10, and rewrites the contents of at least one or all of the registers 9a to 9d of the storage unit 9. The register to be rewritten may be selected each time based on the above judgment or may be set in advance. In this embodiment, register 9 is rewritten.
The determination unit 10 determines the number of pulses stored in b to 9d.
It is set in advance to be rewritten based on the determination. Reference numeral 12 denotes an addition unit that adds the values stored in the registers 9a to 9d of the storage unit 9 to obtain the sum total, that is, the output value of the storage unit 9. Reference numeral 13 displays a numerical value corresponding to the output value of the storage unit 9 determined by the addition unit 12. This is a drive unit that causes display in section 14. Next, the operation of this embodiment will be explained. First, pulses input from the input terminal 6 are counted by the counter 8, and the pulses are sequentially counted by the register 9a of the storage section 9.
Enter. Then, at 1/4 of the gate time,
The latest input pulse count (value stored in register 9a) and the input pulse count counted 1/4 period ago (until then stored in register 9a, but shifted to register 9b at the same time as the input of the latest input pulse count) If the difference between the two is within the range
+1/4 (second counting time) Compare with the number of input pulses counted before the period (the stored value that was previously stored in register 9b, but was shifted to register 9c at the same time as the input of the latest input pulse number) When the difference between the two is within the range Y (Y=X or Y≠X), the registers 9a to 9d are compared.
The adding unit 12 adds the stored values stored in
A numerical value corresponding to this is displayed on the display unit 14 (Case 1). Next, the comparison by one comparator 10a shows that the difference between the stored values of registers 9a and 9b is within the range X, and the comparison by the other comparator 10b shows that
If the difference between the stored values of a and 9c is not within a certain range Y and the number of input pulses is increasing, register 9
"1" from the latest input pulse number stored in a
The value obtained by subtracting the value is input to the registers 9b to 9d to rewrite the stored value, and the value stored in the registers 9a to 9d is added by the adding section 12, and the corresponding numerical value is displayed on the display section 1.
4 (Case 2). Next, the comparison by one comparator 10a shows that the difference between the stored values of registers 9a and 9b is within the range X, and the comparison by the other comparator 10b shows that
If the difference between the stored values of a and 9c is not within a certain range Y and the number of input pulses is decreasing, "1" is added to the latest input pulse number stored in register 9a.
is input into the registers 9b to 9d to rewrite the stored values, the storage values in the registers 9a to 9d are added by the adder 12, and the corresponding numerical value is displayed on the display 1.
4 (Case 3). Next, when the comparison by one comparator 10a shows that the difference between the values stored in the registers 9a and 9b is not within the range The number obtained by subtracting "1" from the number is input into the registers 9b to 9d to rewrite the stored values, the stored values in the registers 9a to 9d are added by the addition section 12, and the corresponding numerical value is displayed on the display section 14. (Case 4). Then, when the comparison by one comparator 10a shows that the difference between the values stored in the registers 9a and 9b is not within the range X and the number of input pulses is decreasing, the latest input pulse number stored in the register 9a A number obtained by adding "1" to the registers 9b to 9d is input to rewrite the stored values, and the stored values in the registers 9a to 9b are added by the adding unit 12, and a corresponding value is displayed on the display unit 14. (Case 5). Next, this specific operation will be explained with reference to the table below and FIG. 4. The table shows the latest number of input pulses counted every 1/4 of the gate time (value stored in register 9a).
A, the difference between the latest input pulse number A and the input pulse number B counted 1/4 period earlier (the value stored in register 9b), the difference between the latest input pulse number A and 1/4 (the first counting time) + 1/4 (second counting time)
Based on the difference from the number of input pulses counted before the period (value stored in the register 9c) C, the stored content of the stored value 9 before rewriting, the stored content of the storage unit 9 after rewriting, and the determination by the determining unit 10. Registers 9a~ of storage unit 9
4 shows the sum total of the values stored in the registers 9a to 9d, that is, the output value E of the storage unit 9 after the value of the register 9d is rewritten with a value corresponding to the value stored in the first register 9a, and FIG. , the sum of the values stored in the registers 9a to 9d before rewriting, that is, the output value D of the storage section 9, the output value E, and the value stored in the register 9a, which is considered to be the current state of pulse generation, is multiplied by 4. The relationship with the value F is shown. In the initial state _t0 , registers 9a to 9 of the storage section 9
"0" is stored in d, and the sum of the values stored in the registers 9a to 9d, that is, the output value E of the storage section 9 is also "0". At counting time t ₁ , register 9 is input as the number of input pulses.
When "10" is input to a, the output value E becomes "10". However, in reality, the value obtained by multiplying the memory value "10" of register 9a, where the latest number of pulses is input, by 4, that is, "40" or a value close to it, is close to the current state of pulse generation, and the corresponding value is displayed. However, in the conventional example, a numerical value corresponding to "10" is displayed, and an accurate numerical value corresponding to the current state of pulse generation is not displayed. Therefore, in this embodiment, the registers 9a, which are compared by the comparator 10a,
Find the difference (A-B) between the memorized values of 9b and select a certain range
For example, if the difference between the two is set to "1" and it is determined that the difference between the two is "10" is outside the range, it is determined that the number of input pulses is increasing because the value stored in register 9a is larger than the value stored in register 9b. and arithmetic unit 11
rewrites the stored values in registers 9b to 9d with the value "9" obtained by subtracting "1" from the stored value "10" in register 9a. Therefore, the output value E of the storage section 9 is "37", and by displaying a value corresponding to this, it is possible to display an accurate value according to the current state of pulse generation (in the case described above). (see 4). At counting time _t2 , when "10" is input as the number of input pulses to register 9a, the values stored in registers 9a to 9c until then are "10・9・9", and the new number of input pulses is input to register 9a. The stored values in the register 9d are sequentially shifted at the time of input and are erased from the storage unit 9, so the stored values in the registers 9a to 9d of the storage unit 9 are “10・10・9・9”.
becomes. At this time, since the comparator 10a determines that the difference (A-B) between the values stored in registers 9a and 9b is "0" and is within the range X, that is, "1", the comparator 10b . By displaying the numerical value corresponding to "38" as is, it is possible to display an accurate numerical value according to the current state of pulse generation (see Case 1 above). Thereafter, when "10" is input as the number of input pulses to the register 9a during counting times _t3 to _t5 , the stored values in the registers 9a to 9d are not rewritten as described above, and the output value E of the storage section 9 is changed. "39""40"
By displaying a numerical value corresponding to "40", it is possible to display an accurate numerical value according to the current state of pulse generation (see Case 1 above). At counting time _t6 , when "5" is input as the number of input pulses to register 9a, registers 9b to 9d
Since the stored values of are all "10", the output value D of the storage section 9 is "35". However, in reality, the value obtained by multiplying the memory value "5" of the register 9a into which the latest pulse number is input, that is, "20" or a value close to it, is close to the current pulse generation.
It is desirable to display numerical values accordingly, but
In the conventional example, a numerical value corresponding to "35" is displayed, and an accurate numerical value corresponding to the current state of pulse generation is not displayed. Therefore, in this embodiment, when the comparator 10a calculates the difference (A-B) between the values stored in the registers 9a and 9b, and it is determined that the difference between the two, "5", is outside the range X, that is, "1", Since the value stored in the register 9a is smaller than the value stored in the register 9b, it is determined that the number of input pulses is decreasing, and the calculation unit 11 calculates the value "6", which is the value "5" stored in the register 9a plus "1". ” to rewrite the stored values in registers 9b to 9d. Therefore, the output value E of the storage section 9 is "23"
Therefore, by displaying a numerical value corresponding to this, it is possible to display an accurate numerical value according to the current state of pulse generation (see Case 5 above). At counting time _t7 , when "4" is input as the number of input pulses to register 9a, the values stored in registers 9a to 9c up to that point are "5, 6, 6", and the new number of input pulses is input to register 9a. The stored values in the register 9d are sequentially shifted at the time of input and are erased from the storage unit 9, so the stored values in the registers 9a to 9d of the storage unit 9 are “4, 5, 6, 6”.
becomes. At this time, since the comparator 10a determines that the difference (A-B) between the values stored in the registers 9a and 9b is "1" and is within the range X, that is, the range of "1", the comparator 10b , 9c, and the difference "2" between the two is in the range Y.
In other words, if it is determined that it is outside the range of "1",
Since the value stored in the register 9a is smaller than the value stored in the register 9c, it is determined that the number of input pulses is decreasing, and the arithmetic unit 11 adds "1" to the value stored in the register 9a, ``5''. and register 9b~
Rewrite the stored value of 9d. Therefore, the output value E of the storage unit 9 is "19", and by displaying a value corresponding to this, it is possible to display an accurate value according to the current state of pulse generation (in the case described above). (See 3). Even when "3" is input as the number of input pulses to the register 9a at counting time _t8 , the counting time _t7
As in the case of , the stored values in the registers 9a to 9d are rewritten, and by displaying a value corresponding to the output value E "15" of the memory section 9, an accurate value corresponding to the current pulse generation condition is displayed. can be displayed (see Case 3 above). At counting time _t9 , when "4" is input as the number of input pulses to register 9a, the values stored in registers 9a to 9c up until then are "3, 4, 4", and the new number of input pulses is input to register 9a. The stored values in the register 9d are sequentially shifted at the time of input and are erased from the storage section 9, so the stored values in the registers 9a to 9d of the storage section 9 are "4, 3, 4, 4".
becomes. At this time, registers 9a, 9b and register 9 determined by comparators 10a, 10b
The difference between a and 9c (A-B and A-C) is "1",
Since the value is "0" and is within the respective ranges X and Y, by displaying the numerical value corresponding to the output value E "15" of the storage section 9 as it is, it is possible to (See Case 1 above). At counting time _t10 , when "5" is input as the number of input pulses to register 9a, the values stored in registers 9a to 9c up to that point are "4, 3, 4", and the new number of input pulses is input to register 9a. The stored values in the register 9d are sequentially shifted at the time of input and are erased from the storage unit 9, so the stored values in the registers 9a to 9d of the storage unit 9 are “5, 4, 3,
4". At this time, the difference (A-B) between the stored values of the registers 9a and 9b determined by the comparator 10a is "1" and is within the range X, but the comparator 10b
The difference (A-C) between the stored values of registers 9a and 9c determined by is "2", which is outside the range Y, and since the stored value of register 9a is larger than the stored value of register 9c, the number of input pulses is is on an increasing trend, and the arithmetic unit 11 sets the value "4" in the register 9a by subtracting "1" from the stored value "5" in the register 9a.
Rewrite the stored values of b to 9d. Therefore, the output value E of the storage unit 9 is "17", and by displaying a value corresponding to this, it is possible to display an accurate value according to the current state of pulse generation (in the case described above). (see 2). In this embodiment, since the stored value of the storage unit 9 is corrected in this way, as is clear from FIG. 4, the output value E after rewriting is higher than the output value D before rewriting, so that As the occurrence degree approaches F, the display response to rapid changes in the number of pulses within the gate time becomes faster. Note that the ranges X and Y (both "1" in the above embodiment) set by the comparators 10a and 10b, which serve as the reference for knowing the change in the number of pulses within the gate time, can be set arbitrarily, and can be set to a large value. If you select a smaller value, the timing for rewriting the stored value in the storage section 9 will be delayed, and if you select a smaller value, the timing for rewriting the value will be faster, and this can be freely selected depending on the purpose of use of this pulse counting device. Furthermore, when rewriting the stored value in the storage unit 9, a certain number ("1" in the above embodiment) is added to the latest input pulse number entered into the register 9a when the value is decreased (cases 3 and 5) and when the number is increased. Time (cases 2 and 4 above)
Make adjustments such as subtracting it to register 9.
Although the value was set according to the stored value of a, the adjustment is made to prevent undershoot when the output value E of the storage section 9 after rewriting is decreased or overshoot when it is increased (both due to excessive rewriting). This was done to prevent the output value E from becoming too small or too large compared to the current pulse count F, and the value can be changed freely according to the purpose of use of this pulse counting device. If you have a choice and you don't have to worry about undershoot or overshoot,
Without performing the adjustment, the determination unit 10 also
A configuration having at least two comparators 10a and 10b is sufficient, and a configuration including another comparator for comparing registers 9a and 9d may also be used.

【table】

〔effect〕

This invention divides a gate time for counting pulses generated in response to changes in a measured quantity into multiple parts, and stores the number of pulses counted each time the divided counting time elapses in a first memory section consisting of a plurality of registers. After that, each time the counting time elapses, a new number of pulses counted is stored in the first register, and the number of pulses stored in each register up to that point is sequentially shifted to the register of the next stage, and the number of pulses counted is stored in the first register. Delete the number of pulses in the register from the memory,
In a pulse counting device configured to display a numerical value according to an output value of a storage section, a stored value of a first register of the storage section and a stored value of a second register one stage subsequent to this first register are provided. 1st to compare
and a second comparator that compares the stored value of the first register with the stored value of a third register one stage after the second register. and rewrites the stored value of the register of the storage section with a value corresponding to the stored value of the first register based on the determination of the determining section, and rewrites the stored value of the register of the storage section with a value corresponding to the stored value of the first register, and corresponds to the latest pulse number within the divided counting time. The device displays a numerical value corresponding to the output value of the storage section as the measured quantity, and determines the change in the number of pulses within the gate time, and based on this determination, the pulse count is counted within the gate time and stored in the register. The current stored value is forcibly rewritten and corrected with a value corresponding to the stored value of the first register, and a numerical value corresponding to the corrected result is displayed. The value is close to the current number of pulses generated, and it is possible to obtain a pulse counting device with quick display response to sudden changes in input pulses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the conventional example, FIG. 2 is an explanatory diagram of the same operation as above, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is an explanatory diagram of specific operation of the same. 6...Input terminal, 8...Counter, 9...Storage section, 9a to 9d...Register, 10...Judgment section,
10a-10b... Comparator, 11... Arithmetic unit, 1
4...Display section.

Claims (1)

[Claims] 1 Divide the gate time for counting pulses generated in response to changes in the measured quantity into multiple parts, and store the number of pulses counted each time the multi-divided counting time elapses in the first register of the storage unit consisting of multiple registers. After that, the new number of pulses counted each time the counting time elapses is stored in the first register, and the number of pulses stored in each register up until then is sequentially shifted to the subsequent registers and stored in the last register. In a pulse counting device that erases the number of pulses that were on from a storage section and displays a numerical value corresponding to an output value of the storage section, the stored value of a first register of the storage section and this first register are matched. 2nd stage
a first comparator that compares the stored value of the register, and a second comparison that compares the stored value of the first register with the stored value of a third register one stage after the second register. A determination unit is constituted by at least two comparators with a device, and based on the determination of the determination unit, the stored value of the register of the storage unit is rewritten with a value corresponding to the stored value of the first register, and the A pulse counting device characterized in that a numerical value corresponding to an output value of the storage section is displayed as a measured quantity corresponding to the latest number of pulses within a divided counting time.