JPS626116A - Integrating meter - Google Patents

Abstract

PURPOSE:To make it unnecessary to provide a memory of a large capacity by executing an integrating operation by dividing it into the upper digit and the lower digit, and correcting a fraction by the lower digit. CONSTITUTION:A lower digit adder 2 is constituted of an addend register which has stored a running distance of each one piece of pulse generated from a distance sensor 1, an adder 2b, an operation register 2c, and an OR circuit 2d. Also, an upper digit adder 3 is constituted of a comparator 3a, a reference value register 3b, a subtracter 3c, and a counter 3d. According to said constitution, when an integrating value of the lower digit has exceeded a prescribed value, count-up of the upper digit is executed, and a prescribed number is subtracted from the integrating value of the lower digit. In this way, it becomes unnecessary to use a memory having such a large capacity as before.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a totalizer that repeatedly adds a predetermined number of times.

[Conventional technology]

Generally, the mileage of an automobile is displayed by integrating the number of rotations of a speedometer cable that is rotationally driven by a transmission output shaft. A unified standard has been established for the number of revolutions of the speedometer cable to be 637 revolutions per 1b.

The number of rotations of the speedometer cable is measured by detecting that nine magnets attached to it repeatedly rotate to the same position and generating a pulse signal.

If this pulse signal is set to be generated 4 times per revolution of the speedometer cable, the traveling distance per pulse will be approximately 0.392rn, and with 3 pulses it will be 1.176m, resulting in a fraction. Therefore, conventionally, processing has been done using a table as shown in the table below.

That is, the number of pulses when the running distance increases by 1 m is stored in a table in advance, and when the difference in the number of generated pulses reaches a value determined in the table, the running distance is counted up. In the case of this table, the pulse length is 1 m when the first 3 pulses occur, 2 m when the next 3 pulses occur, 3 m when the next 2 pulses occur, and so on. The distance is counted up for each integer value.

[Problem that the invention seeks to solve]

However, in this conventional method, the distance without fractions for an integer number of pulses is 392 m, and the same table must be used for each distance.
This method has the disadvantage of requiring the use of a large-capacity memory.

[Means for solving problems]

In order to solve these drawbacks, the present invention divides the integrated value into upper and lower digits, counts up the upper digits when the integrated value of the lower digits exceeds a predetermined value, and calculates the integrated value of the lower digits. The predetermined number is reduced from .

[Effect]

A fraction is left in the lower digits, and that fraction becomes the value at the start of the next count, and the addend is added to that value.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes a distance sensor which, as mentioned above, generates a pulse every time the vehicle travels a predetermined distance by rotating the speedometer cable. 2 is a lower digit adder, and 3ti is a higher digit adder.

The lower digit adder 2 receives the pulse 1 generated from the distance sensor 1.
Addend register 2m that stores the mileage per piece,
It is composed of an adder 2b, an arithmetic register 2c, and an OR circuit 2d, and the upper digit adder 3 includes a comparator 31 and a reference value register 3.
b, a subtracter 3e, and a counter 3d. The reference value register 3b stores a reference value for determining whether the addition result of the adder 2b has become a value to be carried, that is, a value for determining an overflow of the lower digits. The comparator 3a is configured to send out a carry signal during a period in which the addition result of the adder 2b is greater than the reference value stored in the reference value register 3b.

The subtracter 3c adds tI when a carry signal is supplied.
j, the data stored in the reference value register 3b is subtracted from the addition result of the unit 2b.

The operation of the device configured as described above is as follows. As the vehicle travels, the distance sensor 1 generates a pulse, which is supplied to the adder 2b.

The adder 2b is configured to add the value of the addend register 2a, that is, the addend, to the value of the calculation register 2c every time a pulse from the distance sensor 1 is supplied.

Then, the addition result is supplied to and taken in by the arithmetic register 2c via the OR circuit 2d, so that the addition result of the adder 2b increases by the value of the addend every time a pulse is supplied from the distance sensor 1. As mentioned above, the addend at this time is the travel distance per pulse.

When the addends are added several times in the adder 2b, the addition result eventually becomes larger than the value stored in the reference value register 3b, so the comparator 3a sends out a carry signal.
Counter 3d is counted up. Figure 2 shows this state. Figure 2 (a) is the value of the calculation register 2C, Figure 2 (b) is the value of the counter 3d, and the addend of 9 per pulse is α392m. There is. The first is the calculation register 2a.

Since the data in both counters 3d is zero, both data are marked as ``marks'' as shown in ←) and 佽). Then, when the first pulse is supplied, the addend is 0,392m
``392J'', which represents If you set it to "1000" or 1m, there will be no carry over at this point, so
The data of the counter 3d is "0" as shown in (b).

When the second pulse occurs, the data l'-392J of the calculation register 2c and the addend [392J are added, and the adder 2
The addition result of b is "784", this value is taken into the calculation register 2c, and the data of the calculation register 2c is (P).
It becomes Kr784J as shown in .

By the third pulse, the output of adder 2b becomes r1176.
J, the reference value 1000 is generated, so the comparator 3m generates a carry signal and counts up the counter 3d, so the counter 3d instructs "1" as shown in (b). The carry signal is also supplied to subtracter 3C, so
The reference value 1000 is obtained from the addition result “1176” of adder 2b.
is subtracted, and the result of the subtraction is taken into the arithmetic register 2c via the OR circuit 2d. As a result, calculation register 2
As shown in ←), the data of c is the fraction “17” after the carry.
6" and the counter 3d is "1" as shown in (b).
becomes.

When the fourth pulse is supplied, the adder 2b adds the addend 1'-392J to the data r176J in the arithmetic register 2c, so the data taken into the arithmetic register 2c becomes the added value 568.

When displaying this data, counter 3d, which is the upper digit,
It is sufficient to display the data up to that point, and if it is necessary to display the lower digits, the data in the arithmetic register 2c or only the most significant digit thereof may be displayed as the lower digit data.

FIG. 3 is a flowchart when programming this device, and steps 100 to 103 are executed by the lower digit adder 1.
The operation of step 104 corresponds to the operation of the high-order digit adder 3.

In addition, in the above embodiment, the addend is the distance traveled per distance pulse, but the distance pulse may not be used directly, and the input after branching may be used, and the addend is not limited to counting the distance, but the fuel It can also be used to count quantities such as

〔Effect of the invention〕

As explained above, this invention divides integration into upper and lower digits and corrects fractions in the lower digits, eliminating the need to use a large capacity memory as in the past. , it has the effect of being economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the states of registers, and FIG. 3 is a flow chart. 1...Distance sensor, 2...Φ・lower digit adder, 3...
... Counter (upper digit adder), 2 & OΦ, addend register, 2b @@ψ, adder, 2cm... calculation register, 31... comparator, 3b... reference value register , 3c...Subtractor.

Claims (1)

[Claims] In a totalizer that consists of a lower digit adder that adds lower digits each time an addition signal is supplied, and an upper digit adder that adds upper digits when the lower digit adder exceeds a predetermined value, The digit adder adds a unit value every time the addition result of the lower digit adder exceeds a predetermined value, and outputs calculation data obtained by subtracting a predetermined value from the lower digit addition result. An integrator characterized in that each time an addition signal is supplied, it outputs data obtained by adding a value obtained by integrating an addend, which is data corresponding to data for one signal.