JPH0342612B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting device that counts pulse signals generated in relation to changes in a measured quantity, such as the running speed or engine speed of an automobile or motorcycle.

In general, when displaying a measured quantity using pulses proportional to the measured quantity, pulses proportional to the measured quantity are counted at a gate time set by a reference clock signal, and this counted value is latched and displayed as it is updated sequentially. Devices that do this are known. The updateable time for this device is determined by setting the gate time using the reference clock signal, and measurement accuracy depends on the density of the number of pulses input within this gate time. Providing a high density of proportional pulses not only makes the pulse generator quite expensive, but even if it were available at low cost, the number of pulses generated within a clock period at high speeds would be extremely large. The disadvantage is that the capacity of the counter must be increased, resulting in an extremely large and expensive device overall. Furthermore, a method of increasing the gate time and relatively increasing the number of pulses input within this gate time can be easily achieved, but this method has the disadvantage that it is not possible to follow sudden changes in the measured quantity. Therefore, as shown in Fig. 1, when a pulse proportional to a change in the measured quantity is input to input terminal 1, it is counted by counter 2 connected to input terminal 1 and has a counting period. 2
When counting is completed, the counted value of the counter 2 is stored in a plurality of registers, for example, four registers 3a, 3b, 3c, and 3d, and these registers 3a to 3d are stored.
The count values stored in P are added by an adder 4, and a value corresponding to this added value P is displayed.

To explain the operation of the circuit shown in Fig. 1 with reference to Fig. 2, when a pulse A proportional to a change in a measured quantity, for example, the running speed, is input, when the counter 2 finishes counting,
At t ₁ , t ₂ , t ₃ , and t ₄ , the numbers of pulses P ₁ , P ₂ , P ₃ , and P ₄ counted in each display switching time, for example, 1 second, are stored in registers 3d, 3c, 3b, and 3a, The stored pulse numbers P ₁ , P ₂ , P ₃ , and P ₄ are added by the adder 4, and the display 5 shows (P ₁ +P ₂ +P ₃ +P ₄ ).
The traveling speed corresponding to the value of is displayed.

Here, if the traveling speed suddenly decreases and reaches 0 km/h at _t4 , at the end of counting by counter 2 at _t5 , the number of pulses counted during the new display switching time _t4 to _t5 is _P5 = 0 newly enters the register 3a, and the pulse numbers P ₄ , P ₃ , P ₂ previously stored in the registers 3a, 3b, 3c are sequentially shifted to the registers 3b, 3c, 3d, and the oldest display switching is performed. The number of pulses P ₁ counted from time t ₀ to t ₁ is shifted out of the register, and the running speed corresponding to the value (P ₂ +P ₃ +P ₄ +0) added by the adder 4 is displayed on the display. 5, and the display will show a certain speed value even though the traveling speed has reached 0 km/h.

Furthermore, at the end of the next counting, _t6 , the number of pulses P6 = 0 counted during the new display switching time _t5 to _t6 is newly entered into the register 3a, and until then the number of pulses _P6 = 0 is entered into the register 3a.
Number of pulses P ₅ , P ₄ , P ₃ stored in b and 3c
are sequentially shifted to registers 3b, 3c, and 3d, and the number of pulses _P2 counted during the oldest display switching time _t1 to _t2 is shifted out of the register.
The display 5 shows the traveling speed according to the value of (P ₃ +P ₄ +0+0) added by the adder 4, and the display continues to show a certain speed value even though the traveling speed is 0 km/h. .

Thereafter, at the end of counting _t7 , the pulse numbers _P3 to P6 stored in the registers 3a to 3d are shifted in the same manner as described above, and the pulse numbers counted at the oldest display switching time _t2 to _{t3 are} shifted. Instead of P ₃ being shifted out of the register, the number of pulses P ₇ = 0 counted during the new display switching time t ₆ to t ₇ enters the register 3a, and the value of (P ₄ +0+0+0) is added by the adder 4. The display 5 shows the traveling speed corresponding to the current speed, and the displayed value has not yet reached 0 km/h.

Then, at the end of counting _t8 , the number of pulses _P4 to _P7 stored in the registers 3a to 3d is shifted, and the number of pulses _P4 counted at the oldest display switching time _t3 to _t4 is stored in the register. The number of pulses counted in the new display switching time t ₇ to t ₈ instead of being shifted out
When P ₈ =0 enters register 3a, register 3a
The sum of ~3d is (0+0+0+0), and the traveling speed displayed on the display 5 for the first time is 0km/
h.

In this way, with a travel speedometer that uses a conventional pulse counting device, the display does not change to 0 after the car actually stops.
It took 4 seconds to display Km/h, and there was a drawback that the response was slow and there was a difference between the actual perceived speed value and the displayed value.

In order to eliminate the drawbacks of the conventional device, the present invention divides the gate time into multiple parts, counts the pulses generated according to the measured amount, detects the change in the number of pulses within the gate time, and uses this change to determine the gate time. The present invention is characterized by correcting the number of pulses counted within a period of time and displaying a numerical value according to the corrected result, and its purpose is to provide a pulse counting device that has quick response to sudden changes in the number of pulses.

To achieve the above object, the present invention divides the gate time for counting pulses generated in response to changes in the measured quantity into multiple parts, and calculates the number of pulses counted each time the divided gate time passes. A new number of pulses counted each time is stored in the first register among the registers, and a new number of pulses counted each time thereafter is stored in the first register, and the number of pulses stored in each register up to that point is sequentially stored in the subsequent register. In a pulse counting device that shifts the number of pulses stored in the last register and displays a value corresponding to the stored values of all registers, the latest number of pulses stored in the first register is Comparison and judgment means for comparing the number of pulses stored in other registers to determine whether the number of pulses has changed rapidly; means for correcting by rewriting with a predetermined value; and means for comparing and determining whether the latest pulse number has changed rapidly and the latest pulse number is the first.
If it is determined that a value other than the latest pulse number is continuously stored in other registers, including the register, the pulse number of all registers is compared and a constant means for rewriting and correcting the contents of a predetermined register so that it becomes an ordered numerical sequence, and according to the memorized values of all the registers after being corrected as a measured quantity with the latest pulse number of the first register as the main one. The device is configured to display the value that was obtained.

An embodiment of the present invention will be described in detail below based on the accompanying drawings.

FIG. 3 is a block diagram of a pulse counting device according to an embodiment of the present invention. In the same figure, 6 is an input terminal for inputting pulses generated in accordance with the measured amount of a speed detecting section (not shown), and 7 is an input terminal. This is a timer that sets the counting time of the pulses inputted at the terminal 6. The counting time is a value obtained by dividing the gate time by an arbitrary integer, and in this embodiment, it is set to 1/N of the gate time. 8 is a counter that counts the pulses inputted at the input terminal 6 during a set counting time; 9 is a storage section consisting of a plurality of registers that stores the number of pulses counted by the counter 8;
The number of registers in the storage section 9 is the value of the quotient when the gate time is divided by the counting time, and in this embodiment, N registers are used, and the number of pulses counted by the counter 8 is stored every time the counting time elapses. At the same time _, the pulse numbers previously stored in registers _{9 1 , 9 2 .}
... _9N , and the number of pulses stored in the register _9N is erased from the storage section 9. The values of each register are all input to an arithmetic circuit 10, which will be described later, every time the number of pulses is input. The arithmetic circuit 10 compares the latest pulse number within the gate time input to the register ₉₁ with the previous pulse numbers stored in the other registers ₉₂ to _9N , and detects a sudden change in the number of pulses, i.e. The increase/decrease status is compared and determined, and based on the determination result, the register 9 ₂
~9 This is to rewrite and correct the contents of the pulse number stored in _N. The content of this rewritten pulse number is transmitted to each register 9 via the distributor 11.
The numbers of pulses stored in registers ₉ 1 to 9 _N and then stored in registers 9 ₁ to 9 _N are added by an adder 12,
The latch circuit 13 performs the driving necessary for display, and the display section 14 displays a numerical value corresponding to the value of the adder 12.

Next, the configuration of the arithmetic circuit 10 will be explained in more detail based on FIG. 4.

The number of pulses stored in each of the registers 9 ₁ to 9 _N is determined by the number of pulses P ₁ of the register 9 ₁ and the number of pulses P _i of the registers 9 ₂ to 9 _N (i=2 to N ) are compared respectively, and |
When it is determined that (P ₁ −P _i )|≧X (X is a certain set value), the positive/ _negative determination circuit ₁₆
The sign of the register 9 ₂ is determined in the first or second rewriting circuit 17, 18 based on the result.
~9 The number of _N pulses is rewritten and corrected with a certain predetermined value. The rewritten pulse numbers in the registers 9 ₂ to 9 _N are transferred to the distributor 11. On the other hand _, when the comparison judgment circuit 15 judges that | ₍ P _{1 to P i} )| _< It is determined whether or not it has occurred twice or more consecutively, and the number of consecutive occurrences K is counted. The second consecutive number determining circuit 20 determines whether or not there is a consecutive value other than the pulse number P ₁ among the pulse numbers in the registers 9 ₂ to 9 _N. Third
The rewriting circuit 21 updates the registers 9 2 _{to 9} based on the results of the first and second consecutive number determination circuits 19 and 20.
₉ Register at least one of _{the N} pulse numbers.
The number of pulses is rewritten to P ₁ and corrected, and the result is transferred to the distributor 11.

The operation of the present invention constructed as described above will be explained in detail with reference to the flowchart of the arithmetic circuit shown in FIG.

First, pulses input from the input terminal 6 are counted by the counter 8 and input to the register ₉₁ every time 1/N of the gate time elapses. This register 9 ₁
The number of pulses input to is sequentially shifted from register 9 ₂ to register 9 _N every 1/N time. The number of pulses in these registers 9 ₁ to 9 _N is determined by the arithmetic circuit 1
It is transferred to the comparison/judgment circuit 15 that constitutes 0. The comparison/judgment circuit 15 compares the number of pulses P ₁ of the register 9 ₁ and the number of pulses P _i of the other registers 9 ₂ to 9 _N (i=2 to N).
are compared to determine whether the difference between P ₁ and P _i is greater than or equal to the set value X, that is, |(P ₁ −P _i )|≧X (STEP 1). In this embodiment, the set value X is assumed to be "2" for explanation purposes. If |(P ₁ −P _i )|≧2 in at least one register 9 ₂ to 9 _N , the positive/negative determination circuit 16 determines whether (P ₁ −P _i ) is positive or negative (STEP 2). In this case, if (P ₁ − _{P i} ) is positive, the latest number of pulses input to register ₉₁
The fact that P ₁ is larger than the number of pulses P _i of the other registers 9 ₂ to 9 _N indicates that the latest number of pulses is on the rise. Conversely, if (P ₁ −P _i ) is negative, it indicates that the number of pulses is decreasing. (P ₁ −
If P _i ) is positive, the first rewriting circuit 17 brings the value of the pulse number P _i of the other registers 9 ₂ to _{9 N} closer to the pulse number P ₁ of the register 9 1 to which the latest pulse number is input. In order to correct for each pulse number P ₂ ~ _{P N}
Rewrite with the predetermined value Y ₁ (STEP 3). This predetermined value
Although Y ₁ is the latest pulse number P ₁ or the value of "P ₁ -1", in this embodiment, Y ₁ is set to "P ₁ -1". If (P ₁ −P _i ) is negative, the second rewriting circuit 1
8, each pulse number is corrected by bringing the pulse _{number P i of} the other registers 9 ₂ to 9 _N closer to the pulse number P 1 of the register 9 ₁ to which the latest pulse number is input.
Rewrite P ₂ to P _N with a predetermined value Y ₂ (STEP 4). This predetermined value Y ₂ is the latest pulse number P ₁ or “P ₁
However, in this example, Y ₂ is set to “P ₁ +
1". These first rewriting circuits 17 or second
Register 9 ₂ ~ rewritten by rewriting circuit 18
The number of pulses P _i of 9 _N is transferred to each register 9 ₂ to 9 _N via the distributor 11, and then to each register 9 ₁ to 9 N.
The number of 9 _N pulses is added by an adder 12, and after a predetermined drive is performed by a latch circuit 13, a numerical value corresponding to the added value is displayed on a display section 14.

The operations in STEP 1 to STEP 4 above are for displaying a value close to the latest pulse number on the display unit ₁₄ when the number of pulses changes particularly rapidly _. The latest pulse number P ₁ ±
_The reason for setting it to 1 is that although the latest pulse number is input to register _{9 1} , it is not possible to predict the latest pulse number that will be input next. Part 14
Undershoot (display part 1)
This is to prevent the displayed value of 4 from being displayed smaller than the actual value) and overshoot (the displayed value of the display unit 14 being displayed larger than the actual value).

Next, in STEP 1, if |(P ₁ − P _i )|<2, the first consecutive number determination circuit 19 selects the register 9
₁ pulse number P ₁ includes this P ₁ and other registers 9 ₂
It is determined whether the number of pulses P ₂ to P _N of ~9 _N continues two or more times (STEP 5). Also, at this time, if it occurs two or more times in a row, the number of consecutive times K is counted and determined (STEP 6). Next, when the pulse number P ₁ is consecutive two or more times, the second consecutive number determination circuit 20 selects a value P _j other than the pulse number P ₁ that is consecutive two or more times in the registers 9 ₂ to 9 _N. Determine if there is (STEP 7). If there is a value P _j that is continuous two or more times within the number of pulses P ₂ to P _N , the third rewriting circuit 21 writes the value P j to registers 9 (K+2) to 9 _N according to the number of pulses P ₁ .
Rewrite the number of pulses P(K+2) to P _N in (STEP 8). Furthermore, in the fourth rewriting circuit 22, the number of pulses P(MK+ ₁ ) to 9N in the registers 9(MK+2) to _9N is rewritten by a value P _j that is continuous two or more times other than the number of pulses _P 1. . However, M=2, 3,...N (STEP 9). In the operations of STEP 5 to STEP 9, the latest pulse number P ₁ does not change so rapidly as compared to the pulse numbers P ₂ to P _N , but the frequency of the input pulse is not constant (i.e., the number of consecutive input pulses In such a case, by rewriting the values of the number of pulses P ₁ to P _N into several examples in a certain order according to the latest number of pulses P ₁ , P ₁
In addition to focusing on this, the number of pulses P ₂ to P _N in which the previous state is stored is also considered, and a value closer to the actual value is displayed. The number of pulses P ₂ rewritten and corrected by steps 8 and 9
~P _N is transferred to each register 9 ₁ ~ 9 _N via the distributor 11, and then predetermined control is performed to display the display unit 1.
4 is displayed. If "NO" is returned in STEP 5 and 7, the latest pulse number P ₁ does not change so rapidly compared to other pulse numbers and it is not determined that the input pulse frequency is not constant, so do not rewrite it as is. Register 9 ₂ ~
_9N , and is displayed on the display section 14 after being subjected to predetermined control.

Next, this specific operation will be explained with reference to the following table.

In the table, the number of input pulses counted every 1/8 of the gate time is stored in eight registers 9 ₁ to 9 _{8 .}
The contents of each register stored while being shifted sequentially, the contents of each register after being rewritten by the arithmetic circuit 10, the display value B corresponding to the stored contents of the register after being rewritten, and the display value B corresponding to the stored contents of the register after being rewritten, and A conventional display value C without any rewriting is shown.

In the initial state _t0 , "0" is stored in each register ₉₁ to ₉₈ , and the display value is also "0".

At counting time t ₁ , register 9 ₁ is input as an input pulse.
``2'' is input to . In reality, it is desirable to display a value "16" which is 8 times the value "2" of the register ₉₁ into which the latest pulse number is input, or a value close to it, but in the conventional example, "2" is displayed.
Therefore, in this embodiment, first, the comparison/judgment circuit 15 compares the latest pulse number P ₁ and other stored pulse numbers P _i
(i=2 to 8), and if it is determined that at least one of the differences causes the set value Since the number of pulses is larger than the other numbers of pulses, it is determined that the number of input pulses is increasing, and the first rewriting circuit 17 changes the number of pulses P ₂ to
_P8 is rewritten with a predetermined value _Y1 (in this embodiment, _Y1 = _P1-1 )=1. Therefore, display section B after rewriting becomes "9", and by displaying this, a value close to the current desired display value "16" will be displayed.

At counting time t ₂ , the latest pulse number P ₁ is stored in register 9 ₁ .
When "4" is input as , the number of pulses P ₂ to _{P 8} becomes Y ₁ = P ₁ -1 = 4-1 by the same operation as t ₁ above.
=3, and the displayed value B becomes "25".
At this time, the desired display value is "32", which is eight times "4", but the conventional display value C would be "6" if the rewriting at _t1 had not been performed. This means that a value close to the desired value can be displayed.

Next, at counting time _t11 , "0" is input to the register ₉₁ as the latest pulse number _P1 . At this time, if at least one of the differences between the latest pulse number P ₁ and the other pulse numbers P ₂ to P ₈ exceeds the set value Since the determination is made by the positive/negative determination circuit 16, the second
The rewriting circuit 18 rewrites the number of pulses P ₂ to _{P 8} to a predetermined value Y ₂ (in this embodiment, Y ₂ =P ₁ +1)=1. As a result, the rewritten display value B becomes "7". Since the desired display value is "0" and the conventional display value C is "11", this embodiment allows a value close to the desired value to be displayed. This operation is the latest pulse number
P ₁ exceeds the set value X, and other pulse numbers P ₂ to P ₈
Since it is smaller than at least one of the following, it is determined that the number of subsequent input pulses is on a decreasing trend.

Next, at counting time t ₂₁ , the latest pulse number is stored in register 9 ₁ .
“1” is input as P ₁ , and the comparison judgment circuit 15
It is determined that all the differences between the pulse number P ₁ and the other pulse numbers P ₂ to _{P 8} are within the set value X. This means that the latest pulse number P ₁ is the previously stored pulse number.
Since there is not much difference compared to P ₂ to _{P 8} , this indicates that the number of pulses inputted thereafter does not tend to increase or decrease, but is generally in a steady state. but,
In this case, the first consecutive number determination circuit 19
Since the latest pulse number P ₁ is "1" twice, the consecutive number K is determined to be 2, and the second consecutive number determination circuit 20 determines that the pulse number P ₁ is "0" twice.
Since it is determined that the frequency of the input pulse is not constant, it is determined that the frequency of the input pulse is not constant, and even in such a case, the number of pulses P ₂ to P _N in registers 9 ₂ to 9 _N
It is desirable to rewrite it into a certain sequence of numbers according to P ₁ . Therefore, the third rewriting circuit 21 writes "1" into the registers 9(2+2) to ₉₈ . Furthermore, by the fourth rewriting circuit 22, consecutive values "0" other than the pulse number P ₁ are changed to registers 9 (2M+1) (where M=2, 3, 4...N), that is, registers 9 ₅ and 9. ₇ can be entered. In this case, the pulse numbers in the registers 9 ₂ to 9 ₈ are repeated in a sequence of 1, 0 in a certain order. In other words, when the number of input pulses has a roughly steady trend, the display will match that trend even if there is a slight change in the latest input pulse number, taking into consideration the stored number of previously input pulses. will be done. In this case, the display value B is displayed as "5", and the desirable display value is "1" when judged only by the number of pulses _P1 .
However, the number of pulses stored before that is "8" which is 8 times that of "8", but since there are many "0"s in the number of pulses stored before that, the desirable display value is more than "8". It will be small.
That is, the display value B of this embodiment, which is "5", is a value close to that value.

Next, at counting time t ₃₁ , the latest pulse number is stored in register 9 ₁ .
"1" is input as _P1 . In this case, the comparison/judgment circuit 15 compares the number of pulses P ₁ with the number of other pulses P ₂ ~
It is determined that all the differences from P ₈ are within the set value X, and furthermore, the first consecutive number determination circuit 19 determines that the pulse number P ₁ is not consecutive two or more times including this pulse P ₁ . In this case, it is not recognized that there is no sudden change in the latest input pulse number and the frequency of the input pulse is not constant, and in such a case there is no need to rewrite, so the value should be displayed as is. I made it.

■■■ Turtle Shell [0003] ■■■ As described above, according to the present invention, the most recent input pulse number is the main pulse number, and previously stored pulses are By correcting the number, the responsiveness of the displayed value to sudden changes within the gate time becomes faster, and the difference between the actual perceived speed value and the displayed value becomes very small.

Note that the set value X set by the comparison/judgment circuit 15, which serves as a reference for determining a sudden change in the number of input pulses, can be set arbitrarily, and can also be determined by the first and second rewriting circuits 17, 18 for correction. predetermined value Y(Y ₁ ,
Y ₂ ) may be P ₁ instead of "P ₁ ±1" or a combination of both. Furthermore, the number of registers to be rewritten may be set in advance or may be determined according to the judgment result of the comparison judgment circuit 15. register 9 ₁
A method of selecting all or part of 9 _N may also be used.

In addition, in order to correct the number of pulses in the registers 9 ₂ to 9 _N to a certain sequence of numbers, the register to be rewritten in the third rewriting circuit 21 is the (K+2)th register, and the register to be rewritten in the fourth rewriting circuit 22 is the (MK+2)th register. However, this is just one example, and other methods are also possible.

As detailed above, according to the present invention, in a pulse counting device that counts and displays the number of pulses input within a certain gate time, by dividing the gate time into a plurality of times and counting the input pulses, Corrects the number of pulses counted within the gate time according to changes in the input pulse within the gate time,
By displaying the corrected results, it is possible to provide a pulse counting device with quick display response to sudden changes in input pulses.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pulse counting device.
Fig. 2 is an explanatory diagram of the operation of the same device, Fig. 3 is a block diagram of a pulse counting device which is an embodiment of the present invention, Fig. 4 is a block diagram of a comparison/judgment circuit of the same device, and Fig. 5
The figure is a flowchart showing the operation of the comparison/judgment circuit. 6...Input terminal, 8...Counter, 9 ₁ to 9 _N ...
...Register, 10...Arithmetic circuit, 11...Distributor, 12...Adder, 14...Display section, 15...
Comparison judgment circuit, 16... Positive/negative judgment circuit, 17...
First rewriting circuit, 18...Second rewriting circuit, 19
...First consecutive number determining circuit, 20... Second consecutive number determining circuit, 21... Third rewriting circuit, 22...
Fourth rewriting circuit.

Claims (1)

[Claims] 1 Divide the gate time that counts pulses generated in response to changes in the measured quantity into multiple parts, and store the number of pulses counted each time the divided gate time elapses in the first register among the multiple registers. After that, a new number of pulses counted each time is stored in the first register, and the number of pulses that had been stored in each register up to that point is sequentially shifted to the registers in the subsequent stage and stored in the register in the last stage. In a pulse counting device that erases the number of pulses that were on and displays a value according to the stored values of all registers, the latest pulse number stored in the first register is the number of pulses stored in the other registers. a comparison determination means for determining whether or not a sudden change has occurred by comparing the comparison determination means; and a means for correcting by rewriting a predetermined register with a predetermined value when it is determined by the comparison judgment means that a sudden change has occurred. , according to the comparison and determination means, there is no sudden change, and the latest pulse number is stored continuously in other registers including the first register, and values other than the latest pulse number are stored continuously in the registers. If it is determined that the pulse numbers of all the registers are corrected, the first register comprises a means for comparing the pulse numbers of all the registers and rewriting and correcting the contents of the predetermined register so that the number sequence is in a certain order.
A pulse counting device characterized by displaying a value according to the stored values of all registers after being corrected as a measured quantity with the latest pulse number of the register as the main value.