JPH0342614B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse counting device that counts pulse signals generated in relation to changes in a measured quantity, such as the running speed or engine speed of an automobile or motorcycle.

In general, when displaying a measured quantity using pulses proportional to the measured quantity, the pulses proportional to the measured quantity are counted at a game time set by a reference clock signal, and this counted value is latched and displayed in an updated manner. Devices that do this are known. The updateable time for this device is determined by setting the gate time using the reference clock signal, and measurement accuracy depends on the density of the number of pulses input within this gate time. Providing a high density of proportional pulses not only makes the pulse generator quite expensive, but even if it were available at low cost, the number of pulses generated within a clock period at high speeds would be extremely large. The disadvantage is that the capacity of the counter must be increased, resulting in an extremely large and expensive device overall. Furthermore, a method of increasing the gate time and relatively increasing the number of pulses input within this gate time can be easily achieved, but this method has the disadvantage that it is not possible to follow sudden changes in the measured quantity. Therefore, as shown in Fig. 1, when a pulse proportional to a change in the measured quantity is input to input terminal 1, it is counted by counter 2 connected to input terminal 1 and has a counting period. 2
When counting is completed, the counted value of the counter 2 is stored in a plurality of registers, for example, four registers 3a, 3b, 3c, and 3d, and these registers 3a to 3d are stored.
The count values written in are added by an adder 4, and a value corresponding to this added value P is displayed.

To explain the operation of the circuit shown in Fig. 1 with reference to Fig. 2, when a pulse A proportional to a change in a measured quantity, for example, the running speed, is input, when the counter 2 finishes counting,
At t ₁ , t ₂ , t ₃ , and t ₄ , the numbers of pulses P ₁ , P ₂ , P ₃ , and P ₄ counted in each display switching time, for example, 1 second, are stored in registers 3d, 3c, 3b, and 3a, The stored pulse numbers P ₁ , P ₂ , P ₃ , and P ₄ are added by the adder 4, and the display 5 shows (P ₁ +P ₂ +P ₃ +P ₄ ).
The traveling speed corresponding to the value of is displayed.

Here, if the traveling speed suddenly decreases and reaches 0 km/h at _t4 , at the end of counting by the counter 2 at _t5 , the number of pulses counted during the new display switching time _t4 to _{t5 P5} = 0 newly enters the register 3a, and the pulse numbers P ₄ , P ₃ , P ₂ previously stored in the registers 3a, 3b, 3c are sequentially shifted to the registers 3b, 3c, 3d, and the oldest display switching is performed. The number of pulses P ₁ counted from time t ₀ to t ₁ is shifted out of the register, and the running speed corresponding to the value (P ₂ +P ₃ +P ₄ +0) added by the adder 4 is displayed on the display. 5, and the display will show a certain speed value even though the traveling speed has reached 0 km/h.

Furthermore, at the end of the next counting, _t6 , the number of pulses P6 = 0 counted during the new display switching time _t5 to _t6 is newly entered into the register 3a, and until then the number of pulses _P6 = 0 is entered into the register 3a.
Number of pulses P ₅ , P ₄ , P ₃ stored in b and 3c
are sequentially shifted to registers 3b, 3c, and 3d, and the number of pulses _P2 counted during the oldest display switching time _t1 to _t2 is shifted out of the register.
The display 5 shows the traveling speed according to the value of (P ₃ +P ₄ +0+0) added by the adder 4, and the display continues to show a certain speed value even though the traveling speed is 0 km/h. .

Thereafter, at the end of counting _t7 , the pulse numbers _P3 to P6 stored in the registers 3a to 3d are shifted in the same manner as described above, and the pulse numbers counted at the oldest display switching time _t2 to _{t3 are} shifted. Instead of P ₃ being shifted out of the register, the number of pulses P ₇ =0 counted during the new display switching time t ₆ to t ₇ enters the register 3a, and is added directly to (P ₄ +0+0+0) added by the adder 4. The display 5 shows the traveling speed according to the speed, and the displayed value never reaches 0 km/h.

Then, at the end of counting _t8 , the number of pulses _P4 to _P7 stored in the registers 3a to 3d is shifted, and the number of pulses _P4 counted at the oldest display switching time _t3 to _t4 is stored in the register. The number of pulses counted in the new display switching time t ₇ to t ₈ instead of being shifted out
When P ₈ =0 enters register 3a, register 3a
The sum of ~3d is (0+0+0+0), and the traveling speed displayed on the display 5 for the first time is 0km/
h.

In this way, with a travel speedometer that uses a conventional pulse counting device, the display does not change to 0 after the car actually stops.
It took 4 seconds to display Km/h, and there was a drawback that the response was slow and there was a difference between the actual perceived speed value and the displayed value.

In order to eliminate the drawbacks of the conventional device, the present invention divides the gate time into multiple parts, counts the pulses generated according to the measured amount, detects the change in the number of pulses within the gate time, and uses this change to determine the gate time. The present invention is characterized by correcting the number of pulses counted within a period of time and displaying a numerical value according to the corrected result, and its purpose is to provide a pulse counting device that has quick response to sudden changes in the number of pulses.

To achieve the above object, the present invention divides a gate time for counting pulses generated in response to changes in a measured quantity into multiple parts, and calculates the number of pulses counted each time the divided gate time passes. A new number of pulses counted each time is stored in the first register among the registers, and a new number of pulses counted each time thereafter is stored in the first register, and the number of pulses stored in each register up to that point is sequentially stored in the subsequent register. Shift and erase the number of pulses stored in the last register, correct the number of pulses in each register according to the latest number of pulses stored in the first register, and use the corrected values stored in all registers. In the pulse counting device, the pulse counting device is configured to display a value according to the pulse count, and the pulse counting device is configured to determine whether or not the latest pulse number matches the pulse number in the second register that stores the previous latest pulse number. a second determining means for determining the number of consecutive pulses in the second register, including the second register, and obtaining the first consecutive number; a third determining means for determining whether the number of pulses in the register is continuous in other registers not including the first and second registers, and obtaining a second number of consecutive pulses; Comparison means for determining the difference in numbers, and means for correcting the values of registers other than the first and second registers based on the comparison result, the latest pulse number, the latest previous pulse number, and their It is configured to perform correction according to the number of consecutive sequences.

An embodiment of the present invention will be described in detail below based on the accompanying drawings.

FIG. 3 is a block diagram of a pulse counting device according to an embodiment of the present invention. In the same figure, 6 is an input terminal for inputting pulses generated in accordance with the measured amount of a speed detecting section (not shown), and 7 is an input terminal. This is a timer that sets the counting time of the pulses inputted at the terminal 6. The counting time is a value obtained by dividing the gate time by an arbitrary integer, and in this embodiment, it is set to 1N time of the gate time. 8 is a counter that counts the pulses inputted at the input terminal 6 during a set counting time; 9 is a storage unit consisting of a plurality of registers that stores the number of pulses counted by the counter 8; The number is the quotient value when the gate time is divided by the counting time, and in this embodiment, N pieces are used, and the number of pulses counted by the counter 8 is stored as the latest pulse in the storage unit 9 every time the counting time elapses. The number of pulses stored as a number is input to the first register ₉₁ , and the number of pulses previously recorded in the registers ₉₁ , ₉₂ ...9N _-1 is sequentially shifted to the registers ₉₂ , ₉₃ ... _9N , and The number of pulses stored at _9N is erased from the storage section 9. The values of each register are all input to an arithmetic circuit 10, which will be described later, every time the number of pulses is input. The arithmetic circuit 10 compares the latest pulse number within the gate time input to the register ₉₁ with the previous pulse numbers stored in the other registers ₉₂ to _9N , and detects a sudden change in the number of pulses, i.e. The increase/decrease state is compared and determined, and based on the determination result, a command is issued to correct the contents of the pulse numbers stored in the registers 9 ₂ to 9 _N. Based on this correction command, the distributor 11 rewrites the number of pulses in each register 9 ₂ to 9 _N and stores it in each register 9 ₂ to 9 _N , and then adds the number of pulses stored in registers 9 ₁ to 9 _N. Vessel 1
2, the latch circuit 13 performs the necessary driving for display, and the display section 14 displays a numerical value corresponding to the value of the adder 12.

Next, the configuration of the arithmetic circuit 10 will be explained in more detail based on FIG. 4.

The number of pulses stored in each register ₉₁ to _9N is determined by the comparison and judgment circuit 15 as the number of pulses in register ₉₁ .
P ₁ and the number of pulses P _i of registers 9 ₂ to 9 _N (i=2 to N)
are compared, and if it is determined that |(P ₁ −P _i )|≧X (X is a certain set value), the positive/negative determination circuit 1
6, the positive or negative of (P ₁ −P _i ) is determined, and based on the result, the first or second correction command circuit 17,
At step 18, a command is issued to rewrite and correct the number of pulses in the registers 9 ₂ to 9 _N with a certain predetermined value. The rewriting correction command for the registers 9 ₂ - 9 _N is transferred to the distributor 11, and the distributor 11 rewrites the values of the registers 9 ₂ - 9 _N based on the correction command. on the other hand,
When the comparison _/ determination circuit 15 determines that |( _{P 1} −P _i )| _< It is determined whether or not there are two or more consecutive times including the register ₉₁ within, and the number of consecutive times _K1 is counted.
The second consecutive number determining circuit 20 determines whether or not there is a consecutive value other than the pulse number P ₁ among the pulse numbers in the registers 9 ₂ to 9 _N.

Based on the results of the first and second consecutive number determination circuits 19 and 20, the third correction command circuit 21 converts at least one of the pulse numbers in the registers 92 _{to 9N} to the pulse number P in the register _91. The fourth correction command circuit 22 issues a command to rewrite to ₁ and correct it, and the fourth correction command circuit ₂₂
A command is issued to rewrite and correct a predetermined number of pulses out of ~ _9N to a value other than the number of consecutive pulses _P1 , and the result is transferred to the distributor 11.

The first consecutive number determining circuit 19, which is the first determining means, determines that the latest pulse number P ₁ is not consecutive two or more times, that is, the register 9 stores the pulse number P ₁ and the previous latest pulse number. When it is determined that the number of pulses P ₂ of ₂ do not match, the third consecutive number determination circuit 23 which is the second determination means determines whether the number of pulses P ₂ including the register 9 ₂ is continuous or not. and determine the consecutive number K ₂ (the first consecutive number)
Find it by counting. The fourth consecutive number determining circuit 24, which is the third determining means, determines whether the pulse number _P2 is consecutive two or more times in registers ₉₄ to _9N and not consecutive to register ₉₂ . The determination is made by counting the number of consecutive times K ₃ (the second consecutive number). The consecutive number comparing circuit 25, which is _the comparing means _, calculates (K ₃
−K ₂ )≧2. ( _K3 − _K2 )
If ≧2, the fifth correction command circuit 26 issues a command to rewrite and correct the predetermined number of pulses in the registers 9 ₃ to 9 _N to the value of the number of pulses P ₂ , and the sixth correction command circuit 27 issues a command to rewrite and correct a predetermined number of pulses in registers 9 ₃ to 9 _N to the value of pulse number P ₁ , and transfers the result to distributor 11 . The means for correcting the values of registers other than the first and second registers are the fifth and sixth correction command circuits 2.
6, 27.

The operation of the present invention constructed as described above will be explained in detail with reference to the flowchart of the arithmetic circuit shown in FIG.

First, pulses input from the input terminal 6 are counted by the counter 8 and input to the register ₉₁ every time 1/N of the gate time elapses. The number inputted into register 9 ₁ is sequentially shifted from register 9 ₂ to register 9 _N every 1/N time. The number of pulses in these registers 9 ₁ to 9 _N is then transferred to a comparison/judgment circuit 15 configuring the arithmetic circuit 10 . Comparison/judgment circuit 15
is the number of pulses _{P1 in register 91 and} other registers ₉₂ ~
9 _N pulse numbers P _i (i = 2 to N) are compared, and the difference between P ₁ and P _i is equal to or greater than the set value X, that is, | (P ₁ − _{P i} )
| Determine whether ≧X (STEP 1). In this embodiment, the set value X is assumed to be "2" for explanation purposes.
In at least one register 9 ₂ to 9 _N |
(P ₁ −P _i )|≧2, the positive/negative determination circuit 16 determines (P ₁
−P _i ) is positive or negative (STEP 2). In this case, if (P ₁ − _{P i} ) is positive, it means that the latest pulse number P ₁ input to register 9 ₁ is larger than the pulse number P _i of other registers 9 ₂ to 9 _N , that is, the latest pulse This indicates that the number is on the rise. Conversely, if (P ₁ −P _i ) is negative, it indicates that the number of pulses is decreasing. If (P ₁ −P _i ) is positive, the pulse number P 1 of the register 9 ₁ to which the latest pulse number is input in the first correction command circuit 17 is set to the pulse number P ₁ of the other registers 9 ₂ to 9 _N. In order to correct the value of _i by bringing it closer, a command is issued to rewrite each number of pulses P ₂ to P _N with a predetermined value Y ₁ (STEP 3). This predetermined value Y ₁ is the latest pulse number P ₁ or “P ₁ −
However, in this example, Y ₁ is set to "P ₁ -1".
shall be. If (P ₁ −P _i ) is negative, in the second correction command circuit 18, the pulse number P 1 of the register 9 ₁ to which the latest pulse number is input is set to the pulse number P ₁ of the register 9 ₂
In order to correct the number of pulses P _i of ~9 _N closer to each other, a command is issued to rewrite each number of pulses P ₂ to P _N with a predetermined value Y ₂ (STFP4). This predetermined value Y ₂ is set to the latest pulse number P ₁ or "P ₁ +1", but in this embodiment, Y ₂ is set to "P ₁ +1". The number of pulses P _i of the registers 9 ₂ to 9 _N to which the correction command was issued by the first correction command circuit 17 or the second correction command circuit 18
is corrected by a distributor 11 and transferred to each register 9 ₂ to 9 _N , and the number of pulses in each register 9 ₁ to 9 _N is added by an adder 12, and after a predetermined drive is performed by a latch circuit 13, the pulse numbers are added. The display unit 14 displays a numerical value corresponding to the determined numerical value.

The operations in STEP 1 to STEP 4 above are for displaying a value close to the latest pulse number on the display unit ₁₄ when the number of pulses changes particularly rapidly _. The latest pulse number P ₁ ±
_The reason for setting it to 1 is that although the latest pulse number is input to register _{9 1} , it is not possible to predict the latest pulse number that will be input next. Part 14
Undershoot (display part 1)
This is to prevent the displayed value of 4 from being displayed smaller than the actual value) and overshoot (the displayed value of the display unit 14 being displayed larger than the actual value).

Next, in STEP 1, if |(P ₁ − P _i )|<2, the first consecutive number determination circuit 19 selects the register 9
₁ pulse number P ₁ includes this P ₁ and other registers 9 ₂
It is determined whether the number of pulses P ₂ to P _N of ~9 _N continues two or more times (STEP 5). In addition, if this occurs two or more times in a row, the number of consecutive times _K1 is counted and determined (STEP 6). Next, if the pulse number P ₁ is consecutive two or more times, the second consecutive number determination circuit 20
It is determined whether there is a value P _j other than the number of pulses P ₁ that is continuous two or more times in the registers 9 ₂ to 9 _N (STEP 7). If there is a value P _j that is continuous two or more times within the number of pulses P ₂ to P _N , the third correction command circuit 21 sets the number of pulses in the register 9 _(K1+2) to 9 _N at the number of pulses P ₁ . Issue a command to rewrite P _(K1+2) ~P _N (STEP 8). Furthermore, in the fourth correction command circuit 22, the pulse number P _{(MK1+1) of the register 9 ( MK1} +1) is set at a value P _j that is a value other than the pulse number P ₁ and is repeated two or more times.
Rewrite the command and issue the command. However, M=2, 3,...N (STEP 9). In the operations of STEP 5 to STEP 9, the latest pulse number P ₁ does not change so rapidly as compared to the pulse numbers P ₂ to P _N , but the frequency of the input pulse is not constant (i.e., the number of consecutive input pulses In such cases, P 1 can be changed by rewriting the values of the number of pulses P ₁ to P _N into a sequence of numbers in a certain order according to the latest number of pulses _{P 1 .} Number of pulses that are regarded as main and remember the previous state P ₂ ~
It also takes P _N into account and displays values closer to the actual values. The number of pulses P ₂ to P _N issued the rewriting command in STEP 8 and 9 is rewritten by the distributor 11 and transferred to each register 9 ₂ to 9 _N , after which a predetermined control is performed and the number is displayed on the display unit 14. Is displayed.

Next, in STEP 5, the number of pulses P ₁ is set in register 9 ₁
If the number of pulses P ₁ and P ₂ do not match _{two or} more consecutive times including Find the number of times K ₂ (STEP 10),
Note that this consecutive number K ₂ also includes 1. Then the number of pulses
Determine whether P ₂ is consecutive two or more times without including registers 9 ₁ and 9 ₂ (STEP 11), and in this case 2
If the sequence continues more than once, count and find the number of consecutive times _K3 (STEP 12). Next, the consecutive number comparator circuit 25 compares whether the consecutive number K ₃ is greater than the consecutive number K ₂ by two or more (STEP 13). ( _K3 − _K2 )≧2
If so, the fifth correction command circuit 26 changes the number of pulses.
Issue a command to rewrite the number of pulses in registers 9 _(K2+2) to 9 _N using P ₂ (STEP 14). Furthermore, the sixth correction command circuit 27 inputs the register 9A _(K2+1) with the number of pulses P ₁ .
Issue a command to rewrite the number of pulses (STEP 15).
However, A=1, 2,...N. In addition, since |(P ₁ − _{P i} )|≧2 is determined in STEP 1, the value of the number of pulses for which the operations leading to STEP 10 to 15 are performed is the latest pulse number P ₁ and one other pulse. There is only _P2 . In such STEP 10 to 15 operations, there is no such sudden change in the latest pulse number P ₁ compared to the pulse numbers P ₂ to P _N , but the frequency of the input pulse is not constant (i.e., the number of consecutive input pulses is In this case, the latest input pulse _P1 is not stored continuously, but it is determined that it is in a steady state to some extent.In such a case, the number of pulses _P3 to _PN is By rewriting the value into a sequence of numbers in a certain order according to the latest pulse number P ₁ , the previous latest pulse number P ₂ , and the number of consecutive pulses, the sequence with the newer pulse number among the multiple registers can be set as the main sequence. This allows the display to display values closer to the actual values more quickly. Number of pulses issued by rewriting command in STEP14 and 15
P ₂ to P _N are rewritten by the distributor 11 and transferred to the respective registers 9 ₂ to 9 _N , after which predetermined control is performed and displayed on the display unit 14.

If "NO" is obtained in STEP 7, 11, or 13, the latest pulse number P ₁ does not change so rapidly compared to other pulse numbers and the input pulse frequency is not determined to be constant, so it is left as is. Transferred to registers 9 ₂ to 9 _N without being rewritten,
After predetermined control is performed, the information is displayed on the display section 14.

Next, this specific operation will be explained with reference to a table.

First, the operations of STEP 1 to STEP 9 will be explained based on Table 1.

Table 1 shows the contents of each register, in which the number of input pulses counted every 1/8 of the gate time is sequentially shifted and stored in eight registers 9 ₁ to 9 ₈ , and the contents of the arithmetic circuit 10 and distributor 11. Thus, the contents of each register after being rewritten, a display value B corresponding to the stored contents of the register after being rewritten, and a conventional display value C without such rewriting are shown.

In the initial state _t0 , "0" is stored in each register ₉₁ to ₉₈ , and the display value is also "0".

At counting time t ₁ , register 9 ₁ is input as input pulse.
"2" is input in the field. In reality, it is desirable to display a value "16" which is 8 times the value "2" of the register ₉₁ into which the latest pulse number is input, or a value close to it, but in the conventional example, "2" is displayed.
Therefore, in this embodiment, first, the comparison/judgment circuit 15 compares the latest pulse number P ₁ and other stored pulse numbers P _i
(i=2 to 8), and if it is determined that at least one of the differences exceeds the set value Since the number of input pulses is larger than other pulse numbers, it is determined that the number of input pulses is increasing, and the first correction command circuit 17 adjusts the number of pulses.
P ₂ to _{P 8} are set to a predetermined value Y ₁ (in this example, Y ₁ = P ₁ −1) =
Issue a command to rewrite with 1. Therefore, display section B after rewriting becomes "9", and by displaying this, a value close to the current desired display value "16" will be displayed.

At counting time t ₂ , the latest pulse number P ₁ is stored in register 9 ₁ .
When "4" is input as , the number of pulses P ₂ to _{P 8} becomes Y ₁ = P ₁ -1 = 4-1 by the same operation as t ₁ above.
=3, and the displayed value B becomes "25".
At this time, the desired display value is "32", which is eight times "4", but the conventional display value C would be "6" if it was not rewritten at _t1 , so in this embodiment, This means that a value close to the desired value can be displayed.

Next, at counting time _t11 , "0" is input to the register ₉₁ as the latest pulse number _P1 . At this time, if at least one of the differences between the latest pulse number P ₁ and the other pulse numbers P ₂ to P ₈ exceeds the set value Since the determination is made by the positive/negative determination circuit 16, the second
The correction command circuit 18 sets the number of pulses P ₂ to _{P 8} to a predetermined value.
A command is issued to rewrite Y ₂ (in this embodiment, Y ₂ =P ₁ +1)=1. As a result, the rewritten display value B becomes "7". Since the desired display value is "0" and the conventional display value C is "11", this embodiment allows a value close to the desired value to be displayed. This operation determines that the number of input pulses thereafter is on a decreasing trend because the latest pulse number P ₁ exceeds the set value X and is smaller than at least one of the other pulse numbers P ₂ to _{P 8} . .

Next, at counting time t ₂₁ , the latest pulse number is stored in register 9 ₁ .
“1” is input as P ₁ , and the comparison judgment circuit 15
It is determined that all the differences between the pulse number P ₁ and the other pulse numbers P ₂ to _{P 8} are within the set value X. This means that the latest pulse number P ₁ is the previously stored pulse number.
Since there is not much difference compared to P ₂ to _{P 8} , this indicates that the number of pulses inputted thereafter does not tend to increase or decrease, but is generally in a steady state. but,
In this case, the first consecutive number determination circuit 19
The latest pulse number P ₁ is "1" twice in a row, the consecutive number K ₁ is determined to be 2, and the second consecutive number determination circuit 20 determines that the pulse number P ₁ is "0" twice. Since it is determined that the input pulses are continuous, it is determined that the frequency of the input pulses is not constant, and even in such a case, the number of pulses P ₂ ~ in registers 9 ₂ ~ 9 _N
It is desirable to rewrite P _N to a certain number sequence according to P ₁ . Therefore, the third correction command circuit 21 issues a command to rewrite registers 9 ₍₂₊₂₎ to 9 ₈ with "1". Further, the fourth correction command circuit 22 inputs consecutive values "0" other than the pulse number P ₁ to registers 9 _(2M+1) (however, M=2, 3, 4...N), that is, registers 9 ₅ and 9. Issue a command to rewrite ₇ . In this case, the pulse numbers in the registers 9 ₂ to 9 ₈ are repeated in a sequence of numbers having a certain order [1.0]. In other words, when the number of input pulses tends to be approximately steady, even if there is a slight change in the latest number of input pulses, taking into account the number of previously input pulses that are stored,
The goal is to display information that matches that trend. In this case, the display value B is displayed as "5", and the desirable display value is "8", which is 8 times "1" if only the pulse number P ₁ is judged. Since there are many "0" pulses in the number of pulses, judging from this, the desirable display value is smaller than "8". That is, the display value B of this embodiment, which is "5", is a value close to that value.

Next, at counting time t ₃₁ , the latest pulse number is stored in register 9 ₁ .
"1" is input as _P1 . In this case, the comparison/judgment circuit 15 compares the number of pulses P ₁ and other numbers of pulses P ₂ to P ₈
It _is determined that all the differences between the two pulses are within the set value
It is determined that there are no consecutive occurrences including _P1 . In this case, it is not recognized that there is no sudden change in the latest input pulse number and the frequency of the input pulse is not constant, and in such a case there is no need to rewrite, so the value should be displayed as is. I made it.

■■■ Turtle Shell [0006] ■■■ Next, the operations in STEP 10 to 15 will be explained based on Table 2.

Usually, the number of registers for counting and storing pulses corresponding to changes in a measured quantity such as the running speed of a car is 10 to 20. The reason for the large number of registers is that the switching time per multi-divided gate time is shortened, and
This is because the accuracy can be improved because the display can be changed more quickly each time. The operations in STEP 10 to 15 become effective when the number of registers increases in this way, and Table 2 shows the number of input pulses counted every 1/12 of the gate time, for example, in 12 registers. The contents of each register stored while being shifted sequentially from 9 ₁ to 9 ₁₂ , the arithmetic circuit 10 and the distributor 11
The contents of each register after being rewritten by are shown.

At counting time _t41 , "1" is input to the register ₉₁ as the latest pulse number _P1 , and the comparison/judgment circuit 15 calculates all the differences between the pulse number _P1 and the other pulse numbers _P2 to _P12 as the set value X( X=2) or less. Then, the first consecutive number determining circuit 19 determines that the pulse number P ₁ "1" is not consecutive two or more times including the register 9 ₁ , that is, the pulse numbers P ₁ and P ₂ are different. Then, the third consecutive number determining circuit 23 determines that the consecutive number K ₂ of the pulse number P ₂ "2" in the register 9 ₂ is 1. Furthermore, a fourth consecutive number determination circuit 2
4, it is determined whether the values of the number of pulses _P2 are continuous in the registers ₉₄ to ₉₁₂ . In this case, since "2" does not occur two or more times in a row in the registers 9 ₄ to 9 ₁₂ , the correction command is not transferred to the distributor 11 because there is no need to rewrite it into a certain sequence of numbers.

At counting time _t42 , "2" is newly input into the register ₉₁ as the latest pulse number _P1 . Below mentioned above t ₄₁
The explanation of the same operation will be omitted. The first consecutive number determining circuit 19 determines that the pulse number P ₁ "2" is not consecutive two or more times including the register 9 ₁ , that is, the pulse numbers P ₁ and P ₂ are different. and,
The third consecutive number determining circuit 23 determines that the consecutive number _K2 of pulse number _P2 of "1" in the register ₉₂ is 1. Further, the fourth consecutive number determining circuit 24 determines whether the value of the pulse number P ₂ is consecutive two or more times in the registers 9 ₄ to 9 ₁₂ and determines that the consecutive number K ₃ is three.
The consecutive number comparison circuit 25 compares the consecutive numbers K ₂ and K ₃ and determines that (K ₃ −K ₂ )≧2. Therefore, the fifth correction command circuit 26 inputs the pulse number P ₂ "2" to the register 9.
₍₁₊₂₎ ~9 Issue a command to rewrite ₁₂ . Furthermore, the sixth
The correction command circuit 27 issues a command to rewrite the registers 9A ( ₁ +2) (where A=1, 2...N), that is, the registers 9 ₃ , 9 ₆ , 9 ₉ , 9 ₁₂ with the pulse number P 1 "1". The number of pulses P ₂ to _{P 12} after this rewriting is a series of [1, 2, 1], and the number of pulses P 2 to P 12 after this rewriting is a series of [1, 2, ₁ ], _and
By rewriting the earlier pulse numbers with a certain sequence of newer pulse numbers,
The display will take into account the newer number of pulses and their continuous trend. Here, the number of pulses P ₁ of register 9 ₁ is not included in the above fixed number sequence, but
The latest number of pulses is always input to register ₉₁ , and determining whether this is on an increasing, decreasing, or steady trend depends on the number of input pulses thereafter, including the latest pulse number _P1 . Setting a sequence of numbers in a certain order ignores subsequent trends and lacks accuracy when considered from a long time perspective.
We decided not to include P ₁ in a certain sequence of numbers.

Furthermore, as shown in FIG. 6, since the input pulse signal a and the gate signal having multi-divided gate times are not synchronized, the input pulse signal a
Even if there is no fluctuation in the frequency of both signals a and b during counting
Since a count difference of at most one occurs depending on the phase relationship between the pulse numbers P 1 and 1, the pulse number P ₁ may be "1", and in this case, the pulse number P ₁ can also be regarded as a sequence of numbers with a certain order.

At counting time _t51 , "2" is input to the register ₉₁ as the latest pulse number _P1 . The third consecutive number determining circuit 23 sets the number of consecutive pulses _P2 of "1" to ₂ , and the fourth consecutive number determining circuit 24 determines the number of pulses _P2 by using registers other than the above, that is, registers ₉₄ to ₉₁₂ . Determine whether the value is consecutive two or more times, and calculate the number of consecutive times.
Determine K ₃ as 4. Note that although "1" is displayed three times in a row in the registers ₉₅ to ₉₇ , the larger number of consecutive times _K3 is adopted. Then, the consecutive number comparison circuit 25 determines that (K ₃ −K ₂ )≧2. This means that the latest pulse number P ₁ and the different pulse number P ₂ are continuous in newer registers 9 ₂ and 9 ₃ in the register,
By taking this into consideration and also taking into account the frequency of the latest pulse number _P1 , the pulse number is rewritten to a numerical sequence with a newer number of pulses in a certain order as much as possible. Therefore, the fifth correction command circuit 26 registers 9 ₍₂₊₂₎ to
9 ₁₂ is rewritten with the pulse number P ₂ "1", and the sixth correction command circuit 27 writes the register 9A (2+2).
That is, 9 ₄ , 9 ₈ , and 9 ₁₂ are rewritten with the pulse number P ₁ "2". The number of pulses P ₂ to 9 ₁₂ after this rewriting is a series of [1, 1, 2, 1], and is a numerical sequence in a certain order.

■■■ Tortoise Shell [0007] ■■■ As described above, according to the present invention, the latest input pulse number, the latest pulse number before one time, and their consecutive numbers are taken into account, and the more recently stored pulses are By correcting the previously stored number of pulses according to the number sequence, the responsiveness of the displayed value to sudden changes within the gate time becomes faster, and the difference between the actual speed sense value and the displayed value becomes very large. It becomes less.

Note that the set value Determined value Y
(Y ₁ , Y ₂ ) may be P ₁ instead of "P ₁ ±1" or a combination of both. Furthermore, the number of registers to be rewritten may be set in advance or may be determined by the comparison/judgment circuit 15. A method may also be used in which all or part of the registers 9 ₁ to 9 _N are selected depending on the result.

Further, in the third correction command circuit 21, the registers to be rewritten in order to correct the number of pulses in the registers 9 ₂ to 9 _N to a certain sequence of numbers are (K ₁ +2)th,
In the fourth correction command circuit 22 (MK ₁ +1)
In the fifth correction command circuit 26, (K ₂ +
2) In the sixth correction command circuit 27
A _(K2+2) th, respectively, but this is just one example, and other methods are also possible.

As detailed above, according to the present invention, in a pulse counting device that counts and displays the number of pulses input within a certain gate time, by dividing the gate time into a plurality of times and counting the input pulses, Corrects the number of pulses counted within the gate time according to changes in the input pulse within the gate time,
By displaying the corrected results, it is possible to provide a pulse counting device with quick display response to sudden changes in input pulses.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional pulse counting device.
Fig. 2 is an explanatory diagram of the operation of the same device, Fig. 3 is a block diagram of a pulse counting device which is an embodiment of the present invention, Fig. 4 is a block diagram of a comparison/judgment circuit of the same device, and Fig. 5
The figure is a flowchart showing the operation of the comparison/judgment circuit, and FIG. 6 is a waveform diagram for explaining the pulse counting operation. 6...Input terminal, 8...Counter, _91-9N ...Register, 10...Arithmetic circuit _, 11...Distributor, 12...Adder, 14...Display section, 15...Comparison/judgment circuit, 16
...Positive/negative judgment circuit, 17...First correction command circuit, 1
8... Second correction command circuit, 19... First consecutive number determining circuit, 20... Second consecutive number determining circuit, 23... Third consecutive number determining circuit, 24... Fourth consecutive number determining circuit, 25 ...Continuation number comparison circuit, 26...Fifth correction command circuit, 27...Sixth correction command circuit.

Claims (1)

[Claims] 1 Divide the gate time that counts pulses generated in response to changes in the measured quantity into multiple parts, and store the number of pulses counted each time the divided gate time elapses in the first register among the multiple registers. After that, a new number of pulses counted each time is stored in the first register, and the number of pulses stored in each register up to that point is sequentially shifted to the subsequent registers and then entered in the final register. The number of pulses that were on is erased, the number of pulses in each register is corrected according to the latest number of pulses stored in the first register, and a value corresponding to the corrected value of all registers is displayed. In the pulse counting device, a first determining means for determining whether or not the latest pulse number and the pulse number in a second register storing the previous latest pulse number match; a second determining means for determining the number of consecutive pulses of the register including the second register and calculating the first consecutive number;
third determining means for determining whether the number of pulses in the register is continuous in other registers not including the first and second registers and obtaining the second consecutive number;
Comparing means for determining the difference between the first and second consecutive numbers; and means for correcting the values of registers other than the first and second registers based on the comparison result; A pulse counting device characterized by performing correction according to the latest number of previous pulses and the number of consecutive pulses.