JPH027406B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a pulse counting device for counting pulse signals generated in relation to changes in a measured quantity, such as the running speed or engine speed of an automobile, and displaying the pulse signals digitally or as a bar graph. It is related to.

Generally, when measuring and displaying using a repetitive pulse signal proportional to a change in a measured quantity, a configuration is commonly used in which the pulse signal is counted during a game time based on a reference clock signal, and this is latched and displayed in a sequentially updated manner.

In the above configuration, the updateable time is determined by the setting of the reference clock signal period, and the measurement accuracy depends on the density of the number of repetitive pulses input within the above period, but generally it is proportional to the change in the measured quantity. Increasing the density of repetitive pulses not only makes the path generator itself quite expensive, but even if it were provided at a low price, the number of pulses generated within a clock cycle at high speeds would be extremely large. The capacity of the counter must be increased, resulting in an extremely large and expensive device overall.

Furthermore, in order to improve measurement accuracy, it is easily possible to lengthen the clock cycle and relatively increase the number of input pulses within this cycle. It tends to lack the responsiveness required to smoothly update the display in response to changes in the measured quantity, especially when displaying changes in the measured quantity as a bar graph. This has become a problem in practical application.

Therefore, as a method for improving the responsiveness of the above-mentioned gate time type counting device, a frequency measuring circuit disclosed in Japanese Patent Publication No. 52-6189 has been proposed which shortens the update period.

In other words, it has a configuration in which a plurality of counters to which repetitive pulses are applied and which have the same counting period are provided in parallel, the counting start time of each counter is sequentially shifted, and the output count value of the counter is stored in an output register at the end of each counting. The counting operation is shown in FIG.

Figure a shows the cyclic operation of each counter during the counting period T ₁ to _{T 4} when four of the above-mentioned plurality of counters are installed, and the change in each counter count value after the input signal frequency changes. FIG. 2B shows changes in the actual input signal frequency and changes in display values due to each counter count value, and the display update period in this case is shortened to 1/4 of the gate time T.

However, when the input signal frequency changes rapidly over a relatively large range as shown in Figure 1b, the displayed value will change as shown by the dashed line b with respect to the actual change shown by the solid line a. It takes a considerable amount of time to reach the change value, and during that time the change appears to the observer as a slow change. The time to reach the actual measured value requires at least the gate time T, as shown in Figure a, and no matter how many counters you increase, the update cycle will simply become shorter and the displayed value will not follow the actual measured value. There is no improvement whatsoever. In this case, it still takes time to match the actual measured value.
Therefore, the displayed value only changes linearly as shown by the broken line b, and the observer cannot be informed of a sudden change in the input signal frequency.

The purpose of the present invention is to count input pulse signals in a shortened gate time T/n period, which is obtained by dividing the basic gate time T necessary for measurement and display of the minimum display unit on a display by n, and to count input pulse signals at each T/n period. A counting circuit consisting of, for example, an n-stage shift register or n parallel counters is provided to update and hold the count value as a total sum over a period of gate time T, and the count sum of this counting circuit is successively added and determined by an adder. Multiply the latest count value corresponding to the latest shortened gate time T/n by n, and multiply this multiplication value by the ratio setting value for the above added value, and calculate the average value of this calculated value and the added value at gate time T. By configuring the system to display the values, the system can effectively track steep changes in the actual measured values over a relatively large range.Furthermore, when the range of change in the latest consecutive counted values is minute, the added value is displayed as is. It is an object of the present invention to provide a counting device that obtains a smooth display that adapts to a wide range of changes in measured quantities by transferring the measured values to a measuring device.

Hereinafter, an embodiment including a cyclic counting type counting circuit consisting of four parallel counters will be described in detail.

In FIG. 2, 1 is a pulse generator that generates repetitive pulses proportional to changes in a measured quantity such as the engine speed of an automobile, 2 is a reference clock generator that generates a reference clock signal, and 3 is a clock from clock generator 2. 4 is a ring counter 3 which inputs the clock signal and outputs 4 circulating signals.
This gate circuit controls passage of the repetitive pulse from the pulse generator 1 using the output signal of the AND gate 4(1) to 4(4). 5 is a counting circuit that counts the repetitive pulses from the pulse generator 1 that have passed through the gate circuit 4; ) to 5(4). 6 indicates counters 5(1) to 5 which counted during the counting period based on the circulating signal of the ring counter 3.
This is a gate circuit that clears the contents of (4) and supplies a reset signal to start counting in a counting period using a new circulating signal, and inputs the circulating signal from the ring counter 3 and the clock signal from the reference clock generator 2. AND gates 6(1) to 6(4)
Consists of. Reference numeral 7 denotes an adder which adds the counts of each of the counters 5(1) to 5(4) of the counting circuit 5 to calculate the number of repetitive pulses for four cycles of the clock signal. 8 is counter 5(1)~5
Gates 8(1) to 8 are arranged corresponding to the respective outputs of counters 5(1) to 5(4), and are gates 8(1) to 8 which are gates 8(1) to 8 which are arranged to correspond to the respective outputs of counters 5(1) to 5(4).
(4), and the opening/closing control of each gate 8(1) to 8(4) is performed by a reset signal to the counting circuit 5 which is cyclically outputted from the gate circuit 6, for example, a reset signal to the counter 5(1). is applied and starts counting subsequent repetitive pulses,
The connection is configured so that only the output of the counter 5(4) containing the latest count value obtained by applying the above-mentioned reset signal to the gate 8(4) passes through. 9 inputs the latest counted value output from the selection circuit 8, multiplies this counted value by an integer n corresponding to the number of counters in the counting circuit 5, and calculates the weight of the latest counted value with respect to the added value of the adder 7. This is a multiplier that calculates the latest measured value by multiplying by a ratio setting value K (constant) for setting. In this case, the set value K is set to 1 .
10 is an average value circuit that adds the added value of the adder 7 and the multiplied value of the multiplier 9, and divides the sum by K+1;
The average value at gate time T with the added values of (1) to 5(4) is calculated. Reference numeral 11 indicates a memory in which the previously added value in the adder 7 is shifted and is held as data for determining the range of change in successive measured values; 12 indicates the added value in the adder 7 and the previous value held in the memory 11 a comparator that compares the added value and determines whether the range of change exceeds a predetermined value set in advance and outputs a determination signal;
Reference numeral 13 denotes a gate circuit that selects a gate based on the judgment signal from the comparator 12 and controls the passage of either the added value of the adder 7 or the average value of the average value circuit 10. Display data is selected according to the range of change. Reference numeral 14 denotes a display device consisting of a latch circuit, a decoder driver, and a digital display element, which displays a digital signal with followability according to the range of change in the measured quantity, using the average value output calculated by the average value circuit 10 or the added value output from the adder 7. It is to be displayed.

Here, the gate time t by the reference clock generator 2 is conventionally set to 1/4 of the gate time T when counting with one counter, and the addition operation in the adder 7 and the multiplication in the multiplier 9 It is assumed that the operation and the calculation operation in the average value circuit 10 are repeated at the cycle of the clock signal.

Next, the operation of the above configuration will be explained with reference to the time chart in FIG.

The reference clock generator 2 operates upon power-up of the circuit and generates a clock signal b. The ring counter 3 receives the clock signal b and outputs four circulating signals c, d, e, f, and outputs the AND gates 4(1) to 4(4) in the gate circuit 4.
and AND gate 6 (1) in gate circuit 6
~Apply to the A input of 6(4). This results in the above
The repetitive pulses from the pulse generator 1 applied to the AND gates 4(1) to 4(4) are allowed to pass to the corresponding counters 5(1) to 5(4), and the AND gates 6(1) to The clock signal applied to the B input of 6(4) is sent to counters 5(1) to 5.
Clear signal to (4) and control signals g, h, i, and j to gates 8(4), 8(1), 8(2), and 8(3) of selection circuit 8 are respectively distributed and passed through. urge Adder 7 includes counters 5(1) to 5
The addition operation is started a little earlier than the reset signal to (4), and the addition output is supplied to the average value circuit 10 at the above-mentioned clock signal period.

Now, assuming that a repetitive pulse a proportional to the change in the measured quantity is generated from the pulse generator 1, this repetitive pulse a is applied to the B inputs of AND gates 4(1) to 4(4) in the gate circuit 4. counters 5(1) to 5 depending on the signal state to the A input.
(4). Control of the counting period is controlled by the circulating signal c from the ring counter 3.
~f, but first, during the counting period _t1 by the circulating signal c, only the AND gate 4(1) is in the passing state, and the repetitive pulse a is passed through the counter 5(1).
It is counted at . In this case, at the beginning of the output of the circulating signal c, the clock signal b is in the passing state.
In order to reset the counter 5(1) as a reset signal g through the AND gate 6(1),
The counter 5(1) outputs a count value only for the number of repetitive pulses input within the counting period _t1 . At the beginning of the output of the circulating signal d, the counter 5(2) is similarly reset by the reset signal h, and the above circulating signal d
The repetitive pulse a within the counting period _t2 is counted by the counter 5.
It is counted in (2). The counters 5(3) and 5(4) are set in the same manner when the circulation signals e and f are output.
is reset and counts the repetitive pulses a occurring within each counting period t ₃ , t ₄ . In this way, counter 5
When counting is performed in the corresponding counting period in steps (1) to 5(4), the repeated pulse a within the counting period _t5 due to the circulation signal c from the ring counter 3 is counted again by the counter 5(1). It is counted at . At this time as well, the count contents of the counter 5(1) during the counting period _t1 have been cleared by the reset signal g at the beginning of the generation of the circulation signal c, and are counted and output as the number of repetitive pulses within the counting period _t5 . Thereafter, in the same manner, the repetitive pulses a generated in the counting period _t6 to _t8 by the circulating signals d to f are sequentially counted by the counters 5(2) to 5(4), respectively, and by repeating the above, 4 cycles of the clock signal are obtained. The number of repeated pulses in minutes is counted by counter 5 (1) ~
The count is sequentially output in step 5 (4).

The adder 7 sequentially adds the contents of the counters 5(1) to 5(4) at the clock signal period. In other words, each counter 5(1) to 5(4) has a counting period
The total number of repetitive pulses counted from t ₁ to _{t 4} is calculated, and then the counting period t ₂ is one cycle of the clock signal.
The number of repetitive pulses at ~ _t5 is calculated, and thereafter, the number of repetitive pulses for four periods shifted by one clock signal period is calculated one after another, and the average value circuit 10, comparator 12,
It operates to output to the gate circuit 13, and also transfers the number of repetition pulses for the previous four cycles to the memory 11.

Further, the counted values of counters 5(1) to 5(4) are outputted to gates 8(1) to 8(4) of selection circuit 8, respectively, and only the latest counted value is transferred to multiplier 9. That is, the latest count value in the first calculation period T ₁ that is added in the adder 7 is the content of the counter 5 (4) that counted the number of repetitive pulses in the counting period t ₄ , and Control signal g (reset signal to counter 5(1)) is applied only to (4) to transfer the latest count value of counter 5(4) to multiplier 9. The latest count value in the second calculation period _T2 is the content of the counter 5(1) that counts the number of repetitive pulses within the counting period _t5 , and at this time, the control signal h (counter 5) is sent to the gate 8(1). (2)
A reset signal) is applied to the counter 5.
It operates to transfer the latest count value of (1) to the multiplier 9.

In the following calculation periods T ₃ , T ₄ . . . , the latest count values of the corresponding counters 5(1) to 5(4) are cyclically controlled by the selection circuit 8, and sudden changes in the measured quantity are detected. is transferred to the multiplier 9 as data to be calculated in a short time. The multiplier 9 calculates the latest counted value transferred as a multiplied value of an integral multiple corresponding to the number of counters, and further multiplies it by a constant that sets the weight for the added value of the adder 7 to calculate the latest measured value corresponding to the calculation period. do. That is, the multiplier 9 is programmed to give the latest measured value S as follows: S=KnN (1) where N is the latest counted value, n is the number of counters, and K is a constant.

As mentioned above, the average value circuit 10 calculates the average value of the added value in the adder 7 and the calculated value in the multiplier 9 per calculation period T, and when the above added value is taken as X, the average value Y is configured to be given by Y=KnN+X/K+1...(2).

That is, the average value Y found here is the number of repetitive pulses in the calculation period T counted by the counting circuit 5, in other words, the virtual input in the calculation period T based on the average frequency of the input signal in the calculation period T and the latest count value N. The average of the signal average frequency, at least the counting period t in counters 5(1) to 5(4)
The aim is to detect and display the latest fluctuations in the measured quantity over a measurement time of . Further, the constant K is used to set the ratio of the virtual input signal average frequency to the actual average frequency in the counting circuit 5,
In order to change the display value by appropriately following the change in the latest measured quantity in the latest counting period t, this can be achieved by setting the constant K to a large value. In the embodiment shown in FIG. 2, the ratio of each average frequency in the calculation period T is set at 1:1, so the constant K=
It is configured to be calculated as 1. Therefore, the actual calculation process in the average value circuit 10 is programmed to be executed as follows: Y=4N+X/2 (3).

The average value Y calculated in the average value circuit 10 over the counting period t period is sequentially transferred to the gate circuit 13, and is selected from the added value X in the adder 7 according to the variation width of the measured quantity.

When the measured quantity is stable at a substantially constant value, the frequency of the repetitive pulse output from the pulse generator 1 is also stable at a value corresponding to the measured quantity. Therefore, the number of repeated pulses in each counting period t, which are cyclically counted by the counters 5(1) to 5(4) of the counting circuit 5, is always constant in each counter 5(1) to 5(4). , the added value X in the adder 7 is also stable as the sum of the counts of each counter 5(1) to 5(4). Furthermore, since the latest count value N passed by the selection circuit 8 is also the same as the count value in other counters, that is, X/4, the average value Y calculated by the multiplier 9 and the average value circuit 10 is Y=X can be obtained from equation (3). After all, if the measured quantity is stable at a constant value, the added value X of the adder 7 is transferred to the display 11, and the measured quantity is digitally displayed.

Let us now assume that the measured quantity changes rapidly from point P as shown in FIG.

If the repetitive pulse frequency corresponding to the measured quantity detected up to the change point P _{is f1} , and the changed repetitive pulse frequency after point P is _f2 , then the number of repetitive pulses in the counting period t in the counting circuit 5 is It is counted as f ₁ t, f ₂ t. Each counter 5(1) to 5 up to point P
Since the count value in (4) is always given by f ₁ t, the addition value X of the adder 7 calculated in the counting period t period
is stable at 4f ₁ t, and the latest count value Y during the same period is determined by the execution process at the time of stability described above.
It is stable at 4f ₁ t, and therefore, the measured quantity corresponding to the average value Y=4f ₁ t is digitally displayed on the display 11 until the calculation period T ₀ . Change point P of measured quantity
The average value Y in the calculation period T ₁ including the immediately following counting period t ₄ is the latest count value N at the counter 5 (4).
changes to f ₂ t, the virtual average frequency in the calculation period T ₁ calculated by the multiplier 9 and the average value circuit 10 greatly participates. In other words, the added value X of the adder 7 in the calculation period T ₁ is the counted value
The sum of counters 5( ₁ ) to 5(3) including f 1 t and counter 5(4) including count value f ₂ t is given by X = 3f ₁ t + f ₂ t, and the latest count value N is calculated as the counter Since the latest measured value S is given by 4f ₂ t in the multiplier 9, which calculates the value multiplied by n times the number, the average value Y calculated in the average value circuit 10 is calculated by the above equation (3), Y =3f ₁ t+5f ₂ t/2 (4) and transferred to the gate circuit 13.

Further, the contents of the memory 11 at this point are held as the addition value X ₀ =4f ₁ t in the calculation period T ₀ , and the predetermined value M set in advance in the comparator 12 and the addition value of the memory 11 X ₀ =4f Added value of adder 7 for ₁ t X ₁ = 3f ₁ t + f ₂ Change width of t △X =
f ₂ t−f ₁ t is compared, and when ΔX>M, a judgment signal is outputted and the gate of the gate circuit 13 is operated to switch to the average value side. In this case, comparator 12
The predetermined value M is preferably set to a value that is compared and determined as a change in the measurement frequency in which the change width of the display value at the gate time t corresponds to about the display unit. That is, the addition value X in the adder 7
The selective display operation of the average value Y in the average value circuit 10 has the effect of preventing a large flickering phenomenon of the displayed value due to, for example, the display of the average value Y changing significantly more than the actual measured value when the measured quantity slightly fluctuates. Yasu. Therefore, when the change from f ₁ to f ₂ at point P is large, the average value circuit 10 is displayed on the display 14.
The average value Y in is displayed as the measured quantity, and if the fluctuation width ΔX is smaller than the predetermined value Y,
The added value in will be displayed as the measured quantity.

Now, if the rate of change in the repetitive pulse frequency before and after the change point P of the measured quantity is f ₂ = 2f ₁ , the gate circuit 13 switches to the average value circuit 10 side, and therefore the average value given by the average value circuit 10 Y is above
According to equation (4), Y = 13f ₁ t/2, which is naturally displayed after the change for X = 5f ₁ t, which is a simple addition value in adder 7 (effective number of repeated pulses in calculation period T ₁ ). It will be displayed as a value approximated by the power actual measured value 8f ₁ t. Therefore, the observer can more accurately grasp rapid changes in the measured quantity as the counting period t passes, and the display 1
This prevents the slow update display in 4 and enables display with extremely good responsiveness that is approximated by the amount of change.

The above average value calculation and display process is performed during the calculation period T ₂
Subsequent operations are performed in the same manner, and a display with extremely good followability as shown in line b can be provided compared to the conventional slow follow-up operation shown in line a in FIG. 4.

Furthermore, if the change width ΔX of the addition value X ₁ of the adder 7 with respect to the addition value X ₀ of the memory 11 is smaller than the predetermined value M of the comparator 12, the data transfer operation to the display 14 is switched to the adder 7 side. Instead, the correction operation by the multiplier 9 and the average value circuit 10 is not performed.
Now, the change in frequency at point P is from f ₁ to 1.01f ₁
If the value is as small as 1/100, the added value X in the adder ₇ will be
4f ₁ t, given as 4.01f ₁ t in calculation period T ₁ . At this time, the latest measured value S calculated by the multiplier 9 is transferred to the average value circuit 10 as 4.04f ₁ t, and as a result, the average value Y in the calculation period T ₁ is 4.02f ₁ t, which is the actual measured value 4.01 The output will have a larger variation than f ₁ t. The device of the present application uses a comparator 12 and a gate circuit 13 to selectively operate the added value It is configured as a device that performs display. in this case,
Since the change width of the added value ΔX=0.01f ₁ t is smaller than the predetermined value M of the comparator 12, the judgment signal is not output, the gate of the gate circuit 13 is switched to the adder 7 side, and the display 14 shows The added value X is transferred, making it possible to stably display a small amount of change.

In addition, in the above-described embodiment, a cyclic counting method having a plurality of parallel counters was adopted as the counting circuit that performs counting at the shortened gate time, but the counted value at the shortened gate time is sequentially shifted by the basic gate time. It is also possible to configure it using a shift register that updates and retains it.In any case, when the constant K in the multiplier is set to 1, the update display shown in line b in Figure 4 is obtained in the same way, but the constant K
If we set 2 or 3 to give a larger weight to the latest count value N, we get line c in Figure 4,
It is possible to obtain a display with better responsiveness as shown on the d-line, and the ability to follow rapid changes in the measured quantity can be arbitrarily selected by setting the constant K according to the degree of need. Accordingly, it is possible to provide a counting device having display performance.

[Brief explanation of drawings]

Fig. 1 is a time chart explaining the execution process in a conventional pulse counting device, Fig. 2 is a circuit diagram showing an embodiment of the pulse counting device according to the present invention, and Fig. 3 is a counting execution in the device shown in Fig. 2. FIG. 4 is a time chart illustrating the process and is an explanatory diagram showing the display responsiveness of the device of the present invention to changes in the measured quantity. 1...Pulse generator, 2...Reference clock generator,
3...Ring counter, 4,6...Gate circuit, 5...
Counting circuit, 7... Adder, 8... Selection circuit, 9... Modifier, 10... Average value circuit, 11... Memory, 12... Comparator, 13... Gate circuit, 14... Display.

Claims (1)

[Claims] 1. Input a pulse signal with a frequency proportional to the change in the measured quantity, and sequentially count and hold the pulse signal at a shortened gate time T/n period, which is obtained by dividing the basic gate time T required for measurement of at least the minimum display unit by n. an adder which inputs the outputs of the n counting circuits and calculates the sum by adding the sum of the counted values every shortened gate time T/n period; and an adder connected to the output of the counting circuit; Shortened gate time T/n
A selection circuit that passes a corresponding latest count value, and a selection circuit that is connected to the selection circuit, calculates a multiplication value by multiplying the latest count value that has passed through the selection circuit by n, and calculates a multiplication value by multiplying this multiplication value by the above-mentioned addition value. A multiplier that calculates the latest measured value by multiplying by a constant that sets
an average value circuit that calculates an average value in the adder; and a memory that retains the previously added value in the adder;
A comparator that compares the content held in the memory and the added value of the adder and determines whether the difference exceeds a predetermined value, and a judgment signal from the comparator that determines whether the added value or A pulse counting device comprising a gate circuit that selectively passes one of the average values in an average value circuit, and a display that displays the measured value using an output signal from the gate circuit.