SU1069169A1 - Pulse repetition frequency divider with variable division ratio - Google Patents

Description

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The invention relates to a pulse and compute; 7noy technique and can be used in adaptive measurement systems.

A pulse frequency divider is known, comprising a frequency divider with a controlled division factor, a code comparison unit, two adders, a delay element, a gate, and a memory unit tl;

A disadvantage of the known device is limited functionality.

The closest to the technical essence of the invention is a divider of the pulse frequency containing the first pulse counter discharge outputs of which are connected to the inputs of the corresponding elements AND, the second pulse counter, the delay element, the OR element, pulse drivers, shift register, adder, gated pulse generator element BANE C2

A disadvantage of the known device is limited functionality due to the lack of the possibility of adjusting the step of changing the division factor in the complexity of the equipment.

The purpose of the invention is to expand the functionality.

The goal is achieved in that a variable-division pulse frequency divider containing a first pulse counter whose discharge outputs are connected to the first inputs of the corresponding AND elements, the second pulse counter, the delay element and the OR element, the third and fourth pulse counters, and the element input The base of which is connected with the output of the OR element and the zero input of the second pulse counter, and the output with the second inputs of the AND elements, the outputs of which are connected to the discharge inputs of the second Pulse detector, the output of which is connected to the first input of the OR element, the second input of which is connected to the input of the first pulse counter and to the output of the third pulse counter, the input of which is connected to the input bus and the input of the fourth pulse counter, the output of which is connected to the input of the second pulse counter.

The drawing shows a block diagram of the proposed device.

The device contains the first counter of 1 pulses, the bit outputs of which are connected to the first inputs of the corresponding elements AND 2, second 3, third 4 and fourth 5 counters. Pulses, the element OR 6 and the delay element 7, the input of which is connected to the output of the element OR 6 and folded The input of the second counter is 3 pulses, and the output is with the second inputs of the I 2 elements, the outputs of which are connected to the bit inputs of the second counter of 3 pulses, the output of which is connected to the first input of the element OR 6, the second input of which is connected to the input of the first counter 1 pulses and to the output of the third counter 4 pulses, the input of which is connected to the input bus 8 and the input

the fourth counter 5 pulses, the output of which is connected to the input of the second counter 3 pulses, the output bus 9.

A pulse frequency divider with a variable division factor operates as follows. In the initial state, the coefficient of recalculation of the counter 3 is set equal to one () due to the switching off of the bits in the single state. Counter 1 cleared. In counter 5, the recalculation coefficient K m is determined, determined by the required rate of change of the division factor of the device.

The conversion factor of the counter, K4 is set equal to the required cycle length

where T is the cycle length,

FO is the pulse frequency at the device input.

When applying the FO frequency pulses to the bus 8 on the bus 9, pulses will appear with the frequency PO / (since the counting factor). If, for example, K 1, then the frequency

output pulses, j is equal to

fo () The pulses at the output of counter 4 will appear at time intervals T K / -Ro, with the first impulse generated

recorded in the counter 1, transferring its first discharge to the inverse state, so that the first input of the And 2 element of this discharge will have a low potential. Simultaneously with this, through element 6, the counter 3 will be reset to its initial state and overwriting the contents of counter 1 through elements 2 by applying a pulse from the output of element 6 through element 7 to the second inputs of elements 2. As a result, pulses on bus 9 will appear frequency f. / 2x2. until time T at the input of counter 1 does not produce a pulse. There will be a second recording

pulse (switching on the first bit and turning off the second) and rewriting it into a controllable counter, the division factor of which will be equal to 3 (K 3). Follow frequency

impulses on bus 9 will become equal

fft / ir-lC. The cycle will continue until counter 1 is full.

The device can be resumed by resetting the counter 1 manually or by applying a pulse from the output of the counter 1 to its zero input.

If, in the initial state, the counter 1 is partially filled, the start of the cycle may begin with the frequency of the output pulses.

 s ° yyu.tlch

where - the initial installation of the counter 3.

t

fewy.niir - VCjV; .

Thus, the range of frequency variation at the output of the splitter lies within

 four

the maximum number of cycles is 1 Kg.

Maximum total length of all cycles

+ Lh. .TS.Obsh, - -f.

and does not depend on the magnitude of the recalculation coefficient of the task tag.

In the proposed device, it is possible to control the speed

0 changes in the pulse frequency (division ratio). The device does not require complicated adjustment in the process of adjusting the value of the range of variation of the division factor, which is achieved by presetting the division factor of all the counters.

In addition, the proposed divider has a simpler circuit compared with the known device.

0

An important advantage of the device is that the cycle time T remains invariant during the regulation process, which allows the device to be used in adaptive systems of 5 measurements, which work in conditions of maintaining the time of information transmission when its spectral composition changes.

Claims (1)

FREQUENCY SEPARATOR -. . NII OF PULSES WITH VARIABLE DIVISION COEFFICIENT, containing the first pulse counter, the bit outputs of which are connected to the 'first inputs of the corresponding AND elements, the second pulse counter, delay element and the OR element, characterized in that, in order to expand the functionality, they are introduced into it the third and fourth pulse counters, while the input of the delay element is connected to the output of the OR element and the zeroing input of the second pulse counter, and the output is connected to the second inputs of the AND elements, the outputs of which are connected to the input inputs of the second pulse counter, the output of which is connected to the first input of the OR element, the second input of which is connected to the input of the first pulse counter and to the output of the third pulse counter, the input of which is connected to the input bus and the input of the fourth pulse counter, the output of which is connected to the input of the second pulse counter