JPS6318502A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To eliminate the need for troublesome adjustment and to facilitate compatibility by controlling each operation of a signal processing means based on a point of time of a head part of a reproducing signal by a detection means. CONSTITUTION:A signal outputted by an HSWP generator 9 goes to H at the time of A head 1A and goes to L at the time of B head 1B based on a pulse generated by pulse generators PGA, PGB, they are inputted to a phase inversion detection circuit 10 and when the changeover of the head is detected, an output of the circuit 10 goes to H during the period of one basic clock. An initial flag latch 11 is set in response to the leading of the output of the phase inversion detection circuit 10 from L to H, and its Q output goes to H. When the initial counter 12 counts number of basic clocks fM corresponding to a prescribed period, a CY output rises and the leading of the CY output is impressed to an encode data processing section 18 as a recording start signal and the encode data processing section 18 outputs the recording data.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, and reproduces the digital signal recorded by a rotating head as one diagonal track on a recording medium for each unit of time. This invention relates to a digital signal reproducing device suitable for.

[Technical background of the invention and its problems]

When an audio signal is recorded on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotating head, and when this track is to be played back, the audio signal is converted into PCM and recorded and played back. There is a digital signal recording and reproducing device called a DAT (rotating head digital audio tape recorder) that has been considered as a device.

The format of the track actually recorded in R-DAT is the pattern shown in Figure 12 (al), and the frequency of each of MARGIN, PLL, and PO3 TAMBLE is t/2 fH (rs = 9.4 MHz).
, IBG frequency is 1/6 f,4. SUB and P
The direction C is composed of blocks as shown in FIG. 12(b). 5YNC is fixed at 9 bits, and the remaining bits have various patterns depending on the location, audio signal, etc. SU
In the case of B, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 12 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas (A
TF: Automatic Track Fin
ding) is for making it possible to perform tracking control so that the rotary head correctly scans the recording track during reproduction using the output of the rotary head without providing a special head.

That is, the ATF area is located at the beginning and end of each track when the PCM signal is compressed in the time axis and recorded by two rotating heads diagonally forming tracks on a magnetic tape without a guard band. A PCM signal is a tracking biloft signal recorded in an independent recording area, and during playback, the recording track is scanned by a rotating head whose scanning width is wider than the track width, and the rotating head scans both adjacent tracks of the track being scanned. The reproduction output of the pilot signal from the rotary head is used to control the tracking of the rotating head.

Then, the track pattern for this ATF is the first one.
As shown in Figure 3, the pattern shown is a drum diameter of 30 m, a drum winding angle of 90°, and a rotation speed of 20 m.
The case of 00 rpm will be explained.

ATFl and A in the front and rear parts of each track
TF2 is a low frequency signal f with little azimuth effect as a pilot signal for tracking.

This is used to detect the level of crosstalk from both adjacent tracks during playback, and to obtain the level difference between the crosstalk components of both adjacent tracks as a tracking error signal. A low frequency signal of f,/72 (130 KHz) is used as the pilot signal f1.

Further, in ATFI and ATF2, a sync signal for determining the position where the viroft signal f is recorded is recorded. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. The sync signals are different from each other in order to distinguish between the A head and the B head, with the head corresponding to +azimuth being A1 and the head corresponding to -azimuth being B, and the frequency f for the A head. Sink 1 signal f2 of s/18, (=522KHz) has a frequency fw/12 for the B head.
(=784KH2) sink 2 signal f.

are recorded at respective predetermined positions.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. Therefore, the frequency r, 4/6 (=1.56MHz) is placed at a predetermined position to erase the pilot signal fl, sync 1 signal f2, and sync 2 signal f3 of the previous recording.
An erasure signal f4 is recorded.

The positions of the ATF biloft signals are all different between the on-track and both adjacent tracks, and the level of the on-track biloft signal and the pilot signal level of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Five blocks are allocated to each of the ATF areas ATF 1 and ATF2, and the biloft signal f1 is recorded in two of the blocks. The sync signal f,,f, is 1 from the center of the position where one adjacent track is recorded.
It is recorded using blocks or 0.5 blocks.

The pilot signal f1 of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. 1 block of sync signals are assigned to odd frames, and 0.5 blocks of sync signals are assigned to even frames.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, when a magnetic tape recorded in a formant as shown in FIG. 12 (ta+) is reproduced by a rotary head, an RF multiplied signal as shown in FIG. 14(a) is obtained from the rotary head. If this RF multiplied signal is obtained by reproducing the odd frame track (A) in FIG. 13, for example,
By passing it through a 130 KHz band pass filter (BPF), a pilot signal r1 as shown in fbl is obtained.

Section (2) is due to the on-track biloft signal, and sections (2) and (2) are due to crosstalk between the pilot signals of (B) the odd frame track and (B) the even frame track. When the rotary head is correctly scanning on-track, the envelope levels of sections ■ and ■, i.e., fc) ■■ and V■ should be equal, but if there is a track deviation, ■■≠■■ Then,
The amount and direction of deviation of the rotary head from on-track can be determined by its magnitude and polarity. Therefore, by operating the capstan servo and finely adjusting the tape speed based on the difference between V■ and ■■, the rotary head can be run on-track.

In order to perform the above-described operation, it is necessary to detect the sync signal at a predetermined position and accurately sample the levels of Vff and ■■. However, the PCM signals in the SUB and PCM areas before and after the A T F area have the same frequency components as the biloft signal f11 and the sync signals f2 and f3. For this reason, it is necessary to accurately install a window so that the signal processing section that should operate in connection with the A TF area does not operate when it is in the SUB or PCM area. The same can be said for the SUB and PCM Si regions.

Therefore, a pulse generator (PG) installed in the drum is used to generate signals for switching between the two rotating heads and for servo control of the drum motor that rotates the drum on which the rotating heads are installed. It has been considered to set the above-mentioned window based on the signal of .

However, with this method, there is no compatibility between devices having different positional relationships between the rotary head and the PC.

Even if the machine is of the same model or the same type of equipment, the position of the window relative to each rotary head will not be constant due to manufacturing variations or changes over time, so the window must be set wide depending on the tolerance. If this is done, malfunctions are likely to occur. Of course, it is possible to set a somewhat narrow window by adjusting the window creation for each drum and head, but the adjustment work is troublesome and costly, and there are still problems in terms of compatibility with other equipment. remain.

〔the purpose〕

The present invention has been made to solve the above-mentioned problems, and by controlling the operation of each signal processing section based on a reproduced signal that is always in a constant format,
It is an object of the present invention to provide a digital signal reproducing device that eliminates troublesome adjustments and eliminates compatibility problems.

[Summary of the invention]

A digital signal reproducing device according to the present invention, which has been made to achieve the above object, transmits a plurality of signals including a digital signal obtained by converting an audio signal into a PCM signal and compressing the time axis to each of a plurality of diagonal tracks along the longitudinal direction of each track. at least two rotary heads for reproducing the plurality of signals on a recording medium recorded in a predetermined format with recording areas independent in the direction, and a plurality of signals from each track reproduced by each rotary head. The digital signal is reproduced by processing each of the signals by separate signal processing means, and includes means for detecting the leading portion of the reproduced signal from each rotary head, and detecting the leading portion of the reproduced signal by the detecting means. The operation of each of the signal processing means is controlled based on the detection time point. As a result, the operation of each signal processing means is always performed at an accurate point in time based on a reproduced signal of a fixed format, eliminating the need for troublesome adjustments and eliminating compatibility problems.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, l is a rotating drum with a diameter of 30φ, and the rotating drum 1 has two rotating heads of 180", A head IA for recording and reproducing +azimuth and B head IB for recording and reproducing -azimuth. The A head IA is spaced apart from each other.
Two pulse generators (PCs) PGA and PCB are arranged at an intermediate position W between the head B and the head IB.

2 is a crystal oscillator that generates a basic clock fH of 9.4 MHz, and the basic clock f is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system, and outputs a PB/REC switching signal to control switching of the toggle switch 4 consisting of switches SWI and SW2.

5 is a reference signal generator, which generates reference signals of XHz (66Hz: in the case of 2PG), YHz (depending on the number of FCs of the capstan motor) and ZHz based on the basic clock fM applied to the CK large input.

Reference numeral 6 denotes a drum servo, which servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on the reference signal ZH2 under the control of the system controller 3. 8 is a capstan servo, which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when switch 4 is switched to the B contact side by the system controller 3, and switch 4 is switched to the A contact side. During playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is a HSWP (A/100) signal generator,
HSWP that switches between A head IA and B head IB based on pulses from the two PGs above (A/100)
A signal is generated, and the HSWP (A/100) signal is H for A head and H for B head, and is also supplied to each part of the system.

10 is a phase reversal detection circuit, into which the basic clock "9" applied to the GK large input and the HSWP (A/B) signal are input, and the output is supplied to the S input of the initial flag latch 11. 11, the CY output of the initial counter 12 is input to the R input, and the Q
The output is supplied to the R input of the initial counter 12.

The initial counter 12 is under the control of the system controller 3, and the Q output of the initial frang latch 11 is input to the R input, and the CK large input basic clock f. are respectively input, and the CY output is supplied to the R input of the initial flag latch 11, and is also supplied to the S input of the head touch window flag latch 14 via the AND gate 13, which is opened and closed under the control of the system controller 3. There is. Further, the CY output is input to an encode data processing section 18, which will be described later.

The head touch window flag latch 14 is for generating a window that prohibits the head touch detection operation during the noise period when switching the head.The Q output is input as an on signal to the decode data processing section 17, and the R input is used for the processing. A clear signal is input from section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, HSWP (A/
100) Encode data processing unit 18 (described later) based on the signal
The recording data is received and supplied to the rotary heads IA and 1B via the switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
After extracting data from the F-fold signal, performing 10/8 conversion (demodulation), deinterleaving, error correction, etc., it is sent to the D/A converter, and also performs head touch detection, ATF sync detection, tracking error detection, etc. , an error signal is supplied from the track deviation signal generating section 17a to the capstan servo 8.

The encoded data processing unit 1B performs interleaving, parity addition, 8/10 conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above configuration, P from the system controller 3
A recording operation is performed when the B/REC signal is L.

Since the PB/REC signal is L, switch 4 is set to b.
The capstan servo 8 is switched to the contact side, a reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied based on the reference signal YHz, and tracking is controlled.

The H3WP (A/B) signal output by the H3WP (A/B) generator 9 based on pulses generated by the PGA and PCB due to the rotation of the drum 1 becomes H when the A head is IA and becomes L when the B head is IB. This H3WP (A/100) signal is input to the phase reversal detection circuit 10,
100) When the signal level changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H for one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial flag latch 11 is set and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic clocks fM corresponding to a fixed period of 3.75 ms, its CY output rises, and this resets the initial flag latch 1, and The rising edge of the CY output is applied to the encode data processing section 18 as a recording start signal. Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined format.

Next, when the P B/RE signal from the system controller 3 is H, the switch 4 is set to the a side, and the rotating head I
A and IB are connected to the reproduction amplifier 15 and supplied to the RF multiplied signal decode data processing section 17 .

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The amount of track deviation is an ATF error signal that corresponds to the level difference in the amplitude of crosstalk between pilot signals of both adjacent tracks, and the details will be described later.

H3WP (A/B) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 is a reproduction mode counter, and when the count value reaches a value corresponding to, for example, 100 μs/1 ms, the CY output becomes H. This prohibits the head touch operation, which will be described later, while noise occurs when the head is switched, and after the above-mentioned certain period of time, the head touch window flange luff 14 is sent via the AND gate 13 to output its Q output. This is to set H to output an on signal for head touch detection. The on signal from the head touch window flangel rafter 14 is sent to the decode data processing section 17.
head touch, i.e. tape T and head IA
Alternatively, when it is detected that the IB contacts and outputs the RF multiplied signal, the navel window flag graffiti 14 is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproduction amplifier 15, a bandpass filter (BPF) 101, and an envelope detector 102.
, the first sample hold (S/H) circuit 103, the 23rd
/H circuit 104, third S/H circuits 105a and 105b
, toggle switch 106, comparator 107, differential amplifier 108, level correction circuit 109, and resistor RI~
It consists of R4.

On the other hand, the digital system includes the crystal oscillator 2, touch detection circuit 201, sync detection circuit 202, ATF timing generator 203, regeneration flag latch 204, system counter 205, timing generator 206.172 frequency divider 207, ATF initial flag launch 208,
It consists of a power-on reset circuit 209, a latch circuit 210, a protection counter 211, a noise error latch 212, a latch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, to explain from the analog system, the RF signal is input from the head IA and IB (FIG. 1) to the input of the reproduction amplifier 15, and its output is input to each input of the BPFIOl, the head touch detection circuit 215, and the sync detection circuit 216. is supplied to.

The BPFIOI passes only the 130 KHz component in the RF signal and inputs it to the envelope detector 102. The envelope detector 102 envelope-detects the 130KHz component, and sends it to the S/H circuits 103, 105a, 105.
b and 10 inputs of the differential amplifier 108.

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SPI applied from the sync detection circuit 202 to the C input, and outputs this to one input of the comparator 107 and the output of the differential amplifier 108. *PF S/H circuit 10 to be applied respectively
What is sampled and held by 3 is the DC level of the crosstalk of the pilot signal of one adjacent track.

The S/H circuit 104 receives a signal whose level has been adjusted by the level adjustment circuit 109 at its input, samples and holds this signal using the sampling signal SP2 from the ATF timing generator 203, and outputs the signal to the capstan servo 8 (Fig. 1).
is supplied as an ATF error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The S/H circuit 105a samples and holds the output from the envelope detector 1.degree. 2 using the sampling signal 5P3A from the ATF timing generator 203, and toggles this with one end of the resistor R.

output to the a contact of switch SWI of circuit 106.

What the S/H circuit 105a samples and holds is the D of the on-track pilot signal when A track is played back.
It is C level.

The S/H circuit 105b samples and holds the output from the envelope detector 102 using the sampling signal 5P3B from the ATF timing generator 203, and outputs this to one end of the resistor R1 and the b contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105b samples and holds is the D on-track pilot signal when B track is played back.
It is C level.

Resistors R1 to R4 have the same value, and S/H circuits 105a and 105 are added to one end of resistors R8 and R3, respectively.
This is for dividing the output of 5b. The interconnection points of the resistors R and R2 and the interconnection points of the resistors R8 and R4 are respectively connected to the a contact and b contact of the switch SW2 of the toggle switch 106, and each interconnection point has a sample of each 878 circuits. A level of 1/2 of the hold value is obtained.

The toggle switch 106 is controlled by the H3WP (A/100) signal, and when the H3WP (A/100) signal is H, the a
side, and when it is L, it is switched to the b side.

The comparator 107 has one input connected to the S/H circuit 105a.
and 1/2 level of the output of 105b is connected to resistors R3 to R4.
and is applied via the switch SW2, and the output of the S/H circuit 103 is applied to the other input. Comparator 1
07, when 1/2 of the sample and hold values of the S/H circuits 105a and 105b is larger than the output level of the S/H circuit 103, the output becomes H, and this is sent as an OK double signal to the input of the ATF timing generator 203. supply

The differential amplifier 108 has the output of the envelope detector 102 applied to the 10 input and the S/
The difference between the output of the H circuit 103 and the output of the H circuit 103 is taken and inputted to the level adjustment circuit 109. That is, envelope detector 1
The output of 02 is the DC of the crosstalk of the other adjacent track.
When outputting the level, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

The level adjustment circuit 109 is the S/H circuit 105a and 105
For example, the amplification degree is changed in inverse proportion to the output level of b,
By adjusting the signal level from the differential amplifier 108, variations in the outputs of the rotary heads IA and IB are corrected.

Next, to explain the digital system, the head touch detection circuit 201 is connected to the head touch window flag latch 1.
4 (FIG. 1) and the basic clock r8, and supplies the signal to the S input of the reproduction flag launch 204, the details of which will be described later.

The sink detection circuit 202 receives the RF multiplied signal H3WP (A/B
) signal, the ATF window cent signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise error flag 212, the basic clock f from the crystal oscillator 2,
4 and the enable clear signal from the OR gate 216 are input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to the output thereof. The sampling signal SPI is connected to the C input of the S/H circuit 103 and the latch 21.
The enable signal and the detection pulse signal are respectively input to the ATF timing generation circuit 203 at the R input of 0. After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects the beginning of the ATF sync patterns SYl and SY2 of the rotating healds IA and IB, outputs the sampling signal SPI, and then outputs the sampling signal SPI. It operates so as to output a detection pulse signal to the target, and the details will be described later.

The ATF timing circuit 203 is an OK multiplied signal 1/2 frequency divider 20 which is the output of the comparator 107.

7, the initial signal that is the Q output of the ATF initial flag launch 208, the enable signal and detection pulse signal from the sync detection circuit 202, and the output signal from the timing generator 206. The N signal, the enable clear signal from the OR gate 216, and the basic clock fM from the crystal oscillator 2 are input, and the sampling signal SP is output.
2.5P3A, SF3B s false detection signal, and ATF
Sends an END signal. Sampling signal SP2 is S/
The sampling signal 5P3A is connected to the S input of the H circuit 104 and the ATF initial franchise 208.
The C input of the H circuit 105a, the sampling signal 5P3B is connected to the C input of the S/H circuit 105b, and the false detection signal is connected to the latch 2.
The S input of 10, one input of the OR gate 216, the GK large input of the false detection counter 214, and the ATFEND signal are input to one input of the OR gates 216 and 217, respectively.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer counter (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and performs a specified If the detected pulse exceeds the specified value by the time, the sampling signal SP2
．． It outputs 5P3A and 5P3B, and operates to output an erroneous detection signal when the signal is below a specified value or the output of the comparator 107 is at L level, and the details will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of channel bit data of R, -DAT, and outputs a basic clock f. The basic clock fM is applied to the CK large input of the head touch detection circuit 201, the sync detection circuit 202, the ATF timing generator 203, the system counter 205, and the protection counter 211, respectively.

The launches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes H in response to a rising edge of the S input, and whose Q output becomes L in response to a rising edge of the R input.゛The regeneration flag latch 204 is S.
The output of the head touch detection circuit 201 is input to the input, the END signal which is the output of the timing generator 206 is input to the R input, and the Q output is input to the system counter 2.
It is input to the R input of 05. This regeneration Frangelafchi 2
When the Q output of 04 is H, the reproducing operation is in progress.

The system counter 205 receives the Q output of the reproduction flag latch 204 and the CK large input basic clock 7 fl and I at its R input, and outputs Q0 to Q.

is input to the timing generator 206.

This system counter 205 is for roughly indicating the position on the track where each signal is recorded.

Timing generator 206 provides ST to its output based on the Q + "" Q x output from the system counter.
Generates the F window set signal, rear/“front” signal, window clear signal, and E N D signal, sends the ATF window set signal to the sync detection circuit 202, sends the rear/N signal to the ATF timing generator 203, and sends the window clear signal. is supplied to the OR gate 217, and the END signal is supplied to the R input of the reproducing Flange raft 204, respectively. This timing generator 206 is the system counter 20
It decodes the output of 5 and generates the timing required for each part.

1/2 frequency divider 207 is H3WP to which CK large input is applied.
(A/100) Divide the signal by 1/2 and output OD D/E to Q output.
It generates a V E N signal and supplies it to the ATF timing generator 203 . The R input of the 1/2 frequency divider has A.
The Q output of the TF initial flag latch 208 is input.

ATF initial flag latch 208 connects AT to S input.
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. IATF initial flag latch 208 is ATF
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The latch 210 connects the ATF timing generator 203 to the S input.
The sampling signal SPI from the sync detection circuit 202 is input to the R input, and the Q output is input to the R input of the protection counter 211. When the latch 210 detects an error, the Q output becomes H and is reset in response to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain period of time from an erroneous detection, and only when the R input is H, counts the basic clock R to which the CK high input is applied, and is cleared by the R input.

The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise-if flag latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The latch 212 receives the Q output of the latch 213 and the CY output of the large CK input sampling counter 215 at its D input, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

In the latch 213, the CY output of the false detection counter 214 is input to the S input, the CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise error flag latch 212.

The false detection counter 214 receives the false detection signal from the large CK input ATF timing generator 203 and the CY output of the sampling counter 215 at its R input, and the CY output is supplied to the S input of the latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SPI is erroneously detected during a - period, and when the value exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives CK large input H3WP (
A/100) signal is input, and CY output is false detection counter 2.
14, the R input of the launch 213, and the CK large input of the noise error graph 212 are respectively supplied.

The OR gate 216 receives the false detection signal and ATF E N D signal from the ATF timing generator 203 and the CY output of the protection counter 211, and outputs an enable clear signal to the sync detection circuit 202 and the ATF timing generator 203. Send out.

OR gate 217 is a window clear signal from timing generator 206, ATF timing generator 20
The ATF E N D signal from 3 and the CY output from the protection counter 211 are respectively input, and the ATF window off signal to the sync detection circuit 202 is sent to the output thereof.

In the above configuration, the head touch detection circuit 201 and the sync detection circuit 202 pass through the RF double signal regeneration amplifier 15.
and the BPF 101. B.P.
Only the 130 KHz component of the RF multiplied signal supplied to F 101 is passed. The amplitude level of the 130KHz component is converted to a DC level by the envelope detector 102, and then the S/H
It is applied to the inputs of each of circuits 103, 104, 105a and 105b, and to the differential amplifier 108.

The envelope detector 102 sequentially outputs the DC levels of the amplitudes of the crosstalk of the biloft signal of one adjacent track, the crosstalk of the pilot signal of the other adjacent track, and the amplitudes of the crosstalk of the pilot signal of the other adjacent track in chronological order. The DC level of the amplitude of the on-track biloft signal is output before or after the signal.

The S/H circuit 103 samples and holds the DC level of the pilot signal of one adjacent track at the timing of the sampling signal SPI from the sync detection circuit 202.

The crosstalk level of one adjacent track sampled and held is determined by the comparator 107 and the differential amplifier 10.
8 is applied to one person's power.

The S/H circuit 105a converts the DC level of the on-track pilot signal during playback of +azimuth A track to the S/H circuit 105a.
The circuit 105b samples and holds the DC level of the on-track pilot signal during reproduction of one azimuth B track. The output of the S/H circuit 105a, that is, the DC level of the on-track pilot signal is:
The voltage is supplied to the control input of the level adjustment circuit 109 through the a contact of the switch SWI of the toggle switch 106, and the voltage is divided to 1/2 by the resistors R1 and R2, and then the voltage is supplied to the comparator 107 through the a contact of the switch SW2. supplied to one input. Similarly, the output of the S/H circuit 105b is sent to the level adjustment circuit 10 through the b contact of the switch SWI.
9, and after being divided into 1/2 by the resistors R1 and R4, the voltage is applied to the comparator 107 via the b contact of the switch SW2.
is fed to one input of

The comparator 107 becomes an OK multiplied signal H when the level input via the switch SW2 is higher than the human power from the S/H circuit 103. In other words, it is determined that the crosstalk level of one adjacent track has been correctly sampled. In the opposite case, it is determined that the on-track level has been sampled. Therefore, when the OK double signal is L, it is determined that the sync has been erroneously detected. This OK double signal is supplied to the ATF timing generator 203.

The differential amplifier 108 inputs the DC level of the crosstalk amplitude of one adjacent track when the envelope detector 102 outputs the DC level of the crosstalk amplitude of the other adjacent track. Therefore, the output includes the difference in DC level of crosstalk between both adjacent tracks,
That is, the amount of track deviation is obtained, and this is input to the level adjustment circuit 109.

The level adjustment circuit 109 is the S/H circuit 105a and 105
The output of b is applied as a control input, and when the control input is large, the level of the input signal is lowered, and when it is small, it is raised and output.

In short, the level adjustment circuit 109 automatically corrects variations in the outputs of the two rotary heads and inputs the result to the next S/H circuit 104. The S/H circuit 104 samples and holds the corrected deviation amount of both adjacent tracks using the sampling signal SP2. The output of this S/H circuit 104 is supplied to the capstan servo 8.

FIGS. 3(a) to 3(il) are timing charts showing signal waveforms generated in each part by the above operations, corresponding to the symbols attached to each part.

The H3WP (A/100) signal shown in Part 3) is H when played by A head IA with +azimuth, and B head IB.
becomes L during playback. H3W when the head is switched
P The phase of the (A/B) signal is inverted. When the phase is reversed, the Q output of the initial flag latch 11 (FIG. 1) becomes H, and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is determined that the tape has passed a noisy part, and the head touch window flag latch 1
4 (Figure 1) and set its Q output to H. When the Q output of the head touch window flag latch 14 becomes H, the head touch detection circuit 201 operates.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF scratch signal is reproduced, its output becomes H.
, set the regeneration frang latch 204 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 outputs the ATF window set signal to the sync detection circuit 2 based on the Q0 to QX outputs of the system counter 205 and sends the ATF window set signal to the sync detection circuit 2 shortly before the recordings of ATF-1 and ATF-2.
Supply to 02.

After converting the RF flaw signal into a digital signal, the sync detection circuit 202 detects sync 1 (= f
2) and the pattern of sync 2 ("'fs) in the case of B head IB, each sync is detected based on the relationship shown in the table below depending on the frame.

Here, when the sync detection circuit 202 detects 4 syncs in a normal case or 5 syncs in a noisy case, it outputs a sampling signal SPI, and sends a cross of the pilot signal r of one adjacent track to the S/H circuit 103. The talk level is sampled and held, and an enable signal is supplied to the ATF timing generator 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SPI is output from the sync detection circuit 202.
0th order 1.2 to check whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI
After 5 blocks, it is determined whether the sync is detected at a specified value or more, and if it is above the specified value, it is assumed that the sync has been detected correctly and the sampling signal SP2 is sent to S/H after 2 blocks.
The signal is supplied to a circuit 104 to sample and hold the crosstalk level difference between both adjacent tracks, and its output is supplied to the capscun servo 8 as the amount of track deviation.

In addition, if the on-track pilot signal f exists after the sync, when playing back by A to Rad IA, A
Since TF-2 and B heads are being played back at ATF-1, in this case, the sampling signals 5P3A and 5P3B are output after 4 blocks, and these are supplied to the S/H circuits 105a and S/H 105b, respectively. Sample and hold the level of the on-track pilot signal being played by each head.

If the above series of operations are performed correctly, ATF E
An ND signal is output, and is supplied to the sync detection circuit 202 and the ATF timing generator 203 as an enable clear signal via the OR gate 216. ATF
The END signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. Ru.

Missampling, that is, the output of the comparator 107 causes the level of the on-track biloft signal to be S/H.
If it is determined that the circuit 103 has sampled and held,
If the sink is not equal to or greater than the specified value, the erroneous detection signal is set to H, the Q output of the touch 2IO is set to H, and the protection counter 211 performs a counting operation, and the erroneous detection counter 214 performs a +1 operation. When the false detection signal becomes H, the enable clear signal to the sink detection circuit 202 and ATF timing generator 203 via the OR gate 216 also becomes H.

When the enable clear signal becomes H, the sink detection circuit 2
02 performs the operation of detecting the sync again from the beginning, and once the sync is detected, outputs the sampling signal SP1 again. On the other hand, the ATF timing generator 203 sets the sync detection counter and timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal S.
When PI is output, the launch 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the CY output of the protection counter 211 becomes H while an erroneous detection signal is output once, that is, after a specified time (2.5 blocks), the sync detection circuit 202 and the ATF timing generator 203 are connected via the OR gate 216. The enable clear signal to becomes H, and the operation stops.

In addition, the sampling counter 215 is H5WP (A/B
) The rising edge of the signal increases +1, but this is managed by the length of the tape, and if the number of false detections exceeds a certain level during that period, the CY output of the false detection counter 214 becomes H, and this causes the noise flag to rise. The Q output of the latch 213 is set to H to notify the sync detection circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent large dropouts.

In addition, FIG. 4 (al to (C1) and (A) to (H) are timing charts showing the outline of the signal waveforms of each part of the digital system after the initial flag latch varnish is set during playback, and the corresponding The reference numerals are given in FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific example of the configuration of the head touch detection circuit 201 described above.

In the figure, the comparator 1-1 has an RF signal input to one input, and a reference voltage +■ to the other input. Comparator 1-2 has an RF signal at one input,
A reference voltage -V is input to the other input.

The outputs of comparators 1-1 and 1-2 are OR gates l-
3. D-type frisopfloop (FF) via resistor 1-4
1-5 and is further connected to the D input of capacitor 1-5.
6 to ground.

The D-type FF1-5 receives the CK large input basic clock f,4, and its Q output is connected to the input of the AND gate 1-7, and its 0 output is connected to the input of the AND gate 1-8.

The basic clock fH is input to the inputs of the AND gates 1-7 and 1-8, and the outputs of each are connected to the UP large input and the DOWN input of the up/down counter 1-9, respectively. Qa”Qa of up/down counter 1-9
The output is passed through OR gates 1-10 to AND gates 1-8.
The CY outputs are respectively connected to the CK large inputs of the D-type FF1-11. D input of D type FFL-11 is V
It is connected to CC, and the Q output is the output of the touch detection circuit 201.

Up/down counter 1-9 and D type FFI-11 8
For human power, head touch window flag latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, the comparator 1-1 becomes L if the level is higher than the R'F multiplied signal +V and the output is H1 lower. For example, if the level of the comparator 1-2 is higher than the RF multiplied signal -V, the output becomes L if H2 is lower. In other words, when the RF multiplied signal is not within the range of ±V, OR gates 1-3
The output becomes H.

The resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise leaking from the output of the OR gate 1-3. The output of the OR gate 1-3 from which spike-like noise has been removed by the integration circuit is the D-type FF1.
-5 is applied to the D input.

The D-type FF1-5 samples the state of the D input using the basic clock f,4 applied to the CK large input, and outputs the state to the Q output. The 0 output is the inverted output of the Q output. The Q output of D-type FF 1-5 is the basic tarokku “9”.
is applied to one input of the AND gate 1-7, and when the Q output of the D-type FF1-5 is H, the up/down counter 1-7 is applied to one input of the up/down counter 1-7. UP large input basic clock fM of 9 is input. Therefore, the up/down counter 1-9 counts up the basic clock fs when the Q output of the head touch window flag latch 14 is H, the window is standing, and the Q output of the D-type FF 1-5 is H.

When the Q output of the D-type FF1-5 is L, that is, when the RF multiplied signal level is within the range of +v and it is determined that there is no signal, the 0 output becomes H. In this state, Q, -Q of up/down counter 1-9.

When any one of is H, that is, when the counter is not 0, the basic clock f8 is input to
It is applied to the OWN input, and the up/down counters 1-9 perform a down-count operation. Furthermore, due to this down count or reset, the contents of the counter become O and Q.
When all the outputs of the A-QDs are L, the output of the OR gate 1-1O is L and the AND gates 1-8 are closed, so the basic clock f is not supplied to the DOWN input.

When the up/down counter 1-9 counts up, a carry occurs and the CY output becomes H, and this rise causes the D-type FF1-11 to memorize the state of the D input. Since 0 human power is H, the Q output becomes H.

6(a) to 6(0) are timing charts showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in FIG. 6(a) is input.

In a state where the RF multiplied signal is present, the amplitude is continuously greater than ±■, and in a state where there is no signal, that is, where the head is not in contact with the tape, there is almost no amplitude greater than ±V.

Note that ±V is set to a value that allows a signal and noise to be clearly distinguished.

(In response to the RF multiplied signal input as shown in 81, a waveform as shown in (b) appears in the output of the comparator 1-1, and a waveform as shown in (C1) appears in the output of the comparator 1-2. And the output of OR gate 1-3 has Tb
) and (0) are logically summed, resulting in a waveform as shown in (d). As is clear from the waveform in (d), there is gate leakage etc. in the output of gates 1-3. This gate leakage is removed by the integrating circuit, and the D-type FF 1-
A signal having a waveform as shown in (e) is manually inputted to the input of 5.

As a result, a waveform as shown in (f) appears in the Q output of D-type FF1-5, and the period when the Q output is H is AND gate 1-5.
When the basic clock f, 4 passes through 7, a signal as shown in (h) appears at the output of AND gates 1-7.On the other hand, a signal as shown in (h) appears at the output of AND gates 1-8. A signal appears.

Incidentally, noise components slightly exceeding ±V and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears singly, the integrating circuit cannot completely remove it.

The signal (min and (hl) is the U of the 7-up down counter 1-9.
It is applied to the P large input and the DOWN input, respectively.

When the amplifier down counter 1-9 counts a predetermined number, it sends out a carry as shown in il to the CY output, and in response, the D-type FF1-11 stores the D input, and the Q output shows as 01. stand up like that.

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down count 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 7 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H3WP (A
/100) signal, basic clock '., ATF window cent signal, ATF window clear signal, noise signal and enable clear signal are manually input.

A, which is supplied with the RF multiplied signal from the reproduction amplifier 15 (Fig. 1)
The TF equalizer 2-1 has a band of 400 for the ATF sync signal.
Limiter 2 with emphasis on KHz ~900 KHz
-2. Limiter 2-2 is set to H5 if the signal amplitude is larger than the specified level, and L if it is smaller to RF.
Convert to double signal digital signal.

The output of the limiter 2-2 is the CK large input basic clock f.

is supplied to the D input of the D-type FF 2-3, and also to one input of the exclusive (E) OR gate 2-4.

The other input of the EOR gate 2-4 is supplied with the Q output of the D-type FF 2-3, and the EOR gate 2-4 and the D
The type FF2-3 constitutes a phase reversal detection circuit.

The ATF window set signal is input to R and the ATF window clear signal is input to ATF window latch 2-
5 and the ATF window latch 2-
The ATF window signal is output from the Q output of 5.

The output of the EOR gate 2-4 is supplied to the D input of an 11-stage shift register 2-6, in which the basic clock fH is input to the CK input, and the ATF window signal from the ATF window latch 2-5 is input to the R input. Ru. The Q1 output of the 11-stage shift register 2-6 is passed through the inverter 2-7 to the AND gate 2-8 and the AND gate 2-9.
2~Q.

The output is to AND gates 2-8 and 2-9, Q, ~Qll
The output is to NOR gate 2-10 and AND gate 2-9,
Q, ~Qll outputs are respectively sent to the Noah gate.

The outputs of NOR gates 2-10 and 2-11 are supplied to AND gates 2-8 and 2-9, respectively. The inputs of AND gates 2-8 and 2-9 are supplied with H3WP (A/100) after and before inversion by inverter 2-12.
signals are provided respectively. The outputs of AND gates 2-8 and 2-9 are supplied to the input of OR game 2-13.

The output of OR gate 2-13 is CK large input basic clock f
. D of the 29-stage shift register 2-14 to which is input
supplied to the input. Q of 299-stage shift register 2-1
1 output goes to the input of AND gates 2-15 to 2-20, and becomes H when sink 2. Q h = Q a output goes to the input of OR gate 2-21, and goes H when sink 1.
Q, output is input to OR gate 2-22, and becomes H when sink 2, □~Q14 output is input to OR gate 2-23, and Qlf becomes H at both sink 1 and sink 2.
The l~Q2° outputs are input to the OR gate 2-24, and the Q27~Q2. The outputs are supplied to the inputs of OR gates 2-25, respectively.

The output of OR gate 2-21 is connected to the input of AND gates 2-16 and 2-18 and the input of OR gate 2-26, and the output of OR gate 2-22 is connected to AND gates 2-16 and 2-18 and the input of OR gate 2-26.
-17 and the input of OR gate 2-27, the output of OR gate 2-23 is connected to AND gate 2-16 and 2-
18 and the input of OR gate 2-26, the output of OR gate 2-24 is connected to AND gates 2-15 to 2-18.
The input of AND gate 2-27 and the output of OR gate 2-25 are respectively supplied to the input of AND gate 2-15. Also, or gate 2-26 and 2
The output of -27 is supplied to AND gates 2-20 and 2-19, respectively.

The H3WP (A/100) signal is on the above Antogame) 2-15. 2-17 and 2-19, and Antogame) 2-16.
The H5WP (A/100) signal inverted by the inverter 2-12 is supplied to 2-18 and 2-20, respectively. Further, the AND gates 2-15 and 2-16 are supplied with a noise-like signal, and the AND gates 2-17 and 2-18 are supplied with a noise-like signal inverted by an inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28, and the output of the OR gate 28 is output as a detection pulse signal via the AND gate 2-29. On the other hand, the outputs of the AND gates 2-15 to 2-18 are supplied to the OR gate 2-30.
The output of 30 is outputted as a sampling signal SPi via AND gate 2-31, and the ATF enable latch 2-30 is supplied with an enable clear signal to the R input.
32 S input. ATF enable latch 2
The Q output of -32 is output as an enable signal and is also supplied to the input of AND gate 2-29. The 0 output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

A digital signal corresponding to ATF sync 1 and sync 2 in the RF signal is output to the limiter 2-2, and the output of the EOR gate 2-4 corresponds to one clock in accordance with the phase inversion of the digital signal.

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK high input when the window signal from the ATF window latch 2-5 applied to the R input is H. In response to the rise of the basic clock fM, the D input is taken in and sent to the Q1 output, and thereafter the basic clock fM is input.

It is sequentially shifted at each rising edge of Qt and sent to the Q11 output. That is, the shift register 2-6 delays the output of the EOR gate 2-4 by 1-11 clocks and outputs Q, ~Q1.
Send to 1 output.

When Q1 output is L, that is, when there is a change, it is output to AND gates 2-8 and 2 via inverter 2-7.
-9, and when any one of the Q6 to Q6 outputs becomes negative, it is applied to the AND gate 2 through the Nant gate 2-10.
Set one input of -8 to H. Q2 to Q, the output is H when there is no change. At this time, H3WP (A
/100) signal is applied to the input of the AND gate 2-8 via the inverter 2-12.

In this state, all inputs of the AND gate 2-8 become H, and the output becomes H. Therefore, when this condition is not satisfied, the output remains L, does not change for at least 4 clocks, changes for 5 to 7 clocks, and H5WP
(A/100) signal is detected and the 1/2 cycle of the sync 2 signal is detected when the B head IB is reproducing the signal.

In addition, in reality, the sink 2 signal fz (=784KH
z, f, 4/12), so the length that does not change is 6
However, due to clock timing, jitter, etc., there is a margin of ±11 clocks.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

Furthermore, from the output of the AND gate 2-9, the sink 1 signal f2 (=520KHzSfs/
18), but the H3WP (A/100) signal is Hl, that is, A
It is detected when the head IA is performing reproduction, and is output from the AND gate 2-9. Note that the period with no change is 7 clocks, and a change occurs between 8 and 10 clocks.

The sink 2 signal is sent from the AND gate 2-8 when the H3WP (A/100) signal is low, and the sink l signal is sent from the AND gate 2-9 via the OR gate 2-13 when the H3WP (A/100) signal is high. output and shift register 2-
14 D input.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock and sends it to the Q output, and thereafter is shifted every time the clock is applied and sent to the Q t = Q z q output. That is, Q, ~Q2. 1 to 29 for output
The state of the D input is output with a delay of the clock.

When there is a change in the Q and output of the shift register 2-14, the Q1 output becomes H. Sink 2 signal (f3=780K
Hz - 1/12 f) In the case of l), if there is a change 1/2 period before the Q1 output, it will be an error) 2-21
The output becomes H. Further, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. The output of the OR gate 2-26 is the Q of the shift register 2-14, the output and HSWP (A
/B) signal is applied to the input of AND gate 2-20. That is, for sink 2, AND gate 2
Q after one clock delay after detecting sync 2 by -8
1 output appears, and at this time, the change from 1/2 period ago is passed through OR gates 2-21 and 2-26, and the change from one cycle before is sent to AND gates 2-23 and 2-26, respectively. When applied to the inputs of the gate 2-20 at the same time, the output of the AND gate 2-20 becomes H, and accordingly the output of the OR gate 2-28 becomes H.

The output of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink is 2, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SPi through the OR gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable raft 2-32, and the ATF The Q output of enable latch 2-32 becomes H and the Q output becomes L. The Q output is output as an enable signal and is applied to the AND gate 2-29.
After that, the detection pulse signal can be outputted.

In the case of sink 2, when the noise signal is H,
The output of the AND gate 2-16 becomes H, and a similar operation is performed.

On the other hand, when sink 1, or game) 2-22゜2-2
4 and 2-25 become H, and when the noise signal is L, the output of AND gate 2-17 becomes H, and when the noise signal is H, the output of AND gate 2-15 becomes H, and as described above. The same thing is done.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

FIG. 8 (al to fg) is a timing chart showing waveforms of various parts when detecting the sync 2, and corresponding symbols are given in FIG. 7.

Further, FIGS. 9A to 9E are timing charts showing waveforms of various parts when detecting the sync 1, and corresponding symbols are given in the figures.

FIG. 10 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
A signal, basic clock f, 4, HSWP (A/100) signal, enable signal, enable clear signal, rear /'@ signal, OK signal, initial signal, and detection pulse signal are input.

Enable signal to E input, CK large input basic clock fM
, and the 0 and 25 block counters 3-1 each having an enable clear signal input to their R inputs have a value of 9.5.
When a count corresponding to μs is performed, the CY output becomes H, which is input to the E input of the high counter 3-2 and the decoder 3.
-3 are respectively input to the C input.

High counter 3-2 has CK large input basic clock f+q,
An enable clear signal is input to each R input, and counts up every 0.25 block. The Q0 to Q:l (2° to 23) outputs of the counter 3-2 are input to the decoder 3-3.

Decoder 3-3 is for decoding each time,
Only when the C input is H, the 0 to 8.16 and 17 outputs become active, and the 0 to 8 outputs send 0.25 to 2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is input to the gates 3-4 to 3-11, and the 0.5 block signal is input to the gate 3-12.
R human power is supplied to the CK input of D type FF3-13, and 1
The pro-block signal is supplied to the CK large input of the D-type FF3-14.

The decoder 3-15 to which the HSWP (A/100) signal and rear/front signals are respectively input is the ATF currently being reproduced.
This is for decoding the position of the signal, and outputs the B-ATF-1, A-ATF-1, B-ATF-2, and A-ATF-2 signals to the 0 to 3 outputs, and sends this to the gate 3-3. 4
and 3-7 as well as gates 3-16 and 3-17.

Table 3-18, into which the HSWP (A/B) signal and the initial signal are input, has 7 threshold values for the sink detection threshold, and the held threshold value is determined by the HSWP (A/100) signal and the initial signal. is switched and the cent is added to the sync detection counter 3-19. The HSWP (A/100) signal sets each section for sync 1 during head head playback and for sync 2 during B head playback, and each section has 50 consecutive sync patterns.
%. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-27 and inverters 3-28 to 3-30.

Then, the sample signal SP2 is output from the gate 3-10.
An erroneous detection signal is output to the output of gate 3-26, a sample signal S P 3 A is output to the output of gate 3-4, an ATFEND signal is output to the output of gate 3-27, and a sample signal 5P3B is output to the output of gate 3-7. .

In the above configuration, when the sync detection circuit 202 generates the sampling signal SPI, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK multiplication signal, which become H at the falling edge of the sampling signal SPI. The CY output becomes H every time. The decoder 3-3 decodes the state of the high counter 3-2, and its output becomes H only when the CY output of the 0.25 block counter 3-1 is H.

When the O output of the decoder 3-3 appears, that is, 0.25 blocks after the generation of the sampling signal SPI,
If the crosstalk sample value of one adjacent track is less than 1/2 of the on-track level, OK double signal L
Therefore, the D output of the decoder 3-3 does not appear at the output of the AND gate 3-8 which is input via the OK multiplication signal inverter 3-9. However, if there is no OK double signal, the output of AND gate 3-8 becomes H,
This is output from the OR gate 3-26 as an erroneous detection signal.

When 1 output of decoder 3-3 becomes H, 0, 5
As processing after blocking, this is applied to the input of the sink detection counter 3-19 via the OR gate 3-11, and is also applied to the R input of the latch 3-12 and the D-type FF 3-1.
3 CK large input is also applied.

Since the CY output of the sync detection counter 3-19 is input to the D input of the D-type FF 3-13 via the latch 3-12, it is determined whether there is a detected pulse signal greater than the specified value after 0.5 blocks. This will be sampled by the D-type FF3-13. At the same time, the latch 3-12 is reset and the sync detection counter 3-12 is reset.
19, again enter the threshold value from Table 3-18.

When the 3 outputs of the decoder 3-3 are H, processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF 3-14 applied to the D input via the latch 3-12. After one block, sampling is performed to determine whether there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and 3-30 determines whether or not a prescribed detection pulse signal is present based on the ODD/EVEN signal. In case of ODD, D type FF3-13.

Q outputs of 3-14 are both H, D type F in case of EVEN
When the Q output of F3-13 is H, the output of OR gate 3-25 becomes H if there is a specified detection pulse signal.

In similar processing, when the initial signal is H, the output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore,
When the 4 outputs of decoder 3-3 are H, that is, 1.25
After blocking, when a specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-9
An erroneous detection signal of H is outputted from the output of the OR gate 3-26 via.

When the 7 output of the decoder 3-3 is H, that is, after 2 blocks, the presence of the specified detection pulse signal and the OK double signal cause the output of the AND gate 3-10 to be used for sampling other adjacent tracks. sampling signal SP
Outputs 2.

Also, after 4 blocks when the 3 outputs of the decoder 3-15 are H during playback by the A head and the 16 outputs of the decoder 3-3 are H, the sampling signal 5P3A is transferred to the B
When the 1st output of decoder 3-15 is H during playback by the head and the 16th output of decoder is H, 5P
Output 3B and sample the on-track level.

Furthermore, when the 17 output of the decoder 3-3 is H and the A head is ATF-2 and the B head is ATF-1, the ATFEND signal is output via the gates 3-17, 3-5 and 3-27.
A signal is output. Then, when the 8 outputs of the decoder 3-3 become H when the A-head is ATF-1 or the B-head is ATF-2, the ATFEND signal is output via the gates 3-16, 3-6 and 3-27. .

FIG. 11 (al-(1)) is a timing chart showing waveforms of each part accompanying the above operation, and corresponding symbols are assigned to each part.

Note that in the above embodiment, only the operation of the ATF signal processing section is controlled based on the beginning part of the reproduced signal, but the 5U
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as BI, PCM, and 5UB-2.

〔effect〕

As explained above, according to the present invention, the operation of the plurality of signal processing means that detects the leading portion of the reproduced signal by each rotary head and processes each of the plurality of signals on the track based on the detected time point is controlled. This eliminates the need for adjustments that would be required when controlling based on rotating head switching, and allows accurate control even when recording with another device, eliminating compatibility issues. There is.

[Brief Description of the Drawings] Fig. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, Fig. 2 is a block diagram showing main parts of the present invention,
Figures 3 and 4 are timing charts showing signal waveforms of each part in Figure 2, Figure 5 is a circuit diagram showing the specific configuration of a part of Figure 2, and Figure 6 is in Figure 5. FIG. 7 is a block diagram showing the specific configuration of other parts in FIG. 2. FIGS. 8 and 9 are timing chart diagrams showing signal waveforms of each part in FIG. FIG. 10 is a circuit diagram showing a specific configuration of another part in FIG. 2, FIG. 11 is a timing chart showing signal waveforms of each part in FIG. 10, and FIG. R-DA
FIG. 13 is a diagram showing the ATF l-rank pattern of R-DAT, and FIG. 14 is a diagram for explaining the principle of tracking control using the track pattern of FIG. 13. be. IA, IB... Rotating head, 201... Head touch detection circuit, 2-6... Timing generator. Yasuo Nakaniku

Claims (1)

[Claims] Audio signals are transmitted to each of a plurality of diagonal tracks by a PC.
At least a method for reproducing the plurality of signals on a recording medium in which a plurality of signals including digital signals converted into M signals and time axis compressed are recorded in a predetermined format with independent recording areas in the longitudinal direction of each track. In an apparatus that has two rotating heads and reproduces a digital signal by processing each of a plurality of signals from each track reproduced by each rotating head with separate signal processing means, the reproduced signal from each rotating head What is claimed is: 1. A digital signal reproducing device comprising: means for detecting a leading portion of a reproduced signal; and controlling the operation of each of the signal processing means based on a point in time when the detecting means detects the leading portion of a reproduced signal.