JPS6334762A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To execute stable tracking control by executing operation for detecting a normal sink signal again when a detected sink signal is not a normal sink signal. CONSTITUTION:When it is decided that missampling, i.e. an output of a comparator 107 is 'L' and the level of a pilot signal on an ON track is sampled and held by a sample holding circuit 103 and when the number of sinks is <= a specified value, a misdetection signal is turned to 'H' and a Q output of a latch 210 is turned to 'H' to allow a protection counter 211 to execute counting operation and to allow a misdetection counter 315 to execute '+1' operation. When the misdetection signal is turned to 'H' and an ENABLE clear signal to be supplied to an automatic track finding(ATF) timing generator is turned to 'H', the circuit 202 executes the operation for detecting sinks again from the initial sink, and at the time of detection of a sink, outputs a sampling signal SP1 again.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, and reproduces the digital signal recorded by a rotating head as one diagonal track on a recording medium for each unit of time. This invention relates to a digital signal reproducing device suitable for.

[Technical background of the invention and its problems]

A device that records audio signals on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotary head, and when reproducing the audio signals, converts the audio signals into PCM and records and reproduces them. There is a digital signal recording and reproducing device called DAT (rotating head digital audio tape recorder), which is considered as a digital audio tape recorder.

The format of the track actually recorded in R-DAT is the pattern shown in FIG. 15(a), and the frequency of each of MARGIN, PLL, and posTAMBLE is 1/2fH (fM=9.4MHz) I
The frequency of BG is 1/6 rM. The SUB and PCM are composed of blocks as shown in FIG. 15(b). 5YNC is 10 bits (fixed at 9 bits), and the remaining bits have various patterns depending on the location, audio signal, etc. In the case of SUB, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 15 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas located between 5UB-1 and PCM0 and between PCM and 5UB-2 (A T
F: Autotxatic Track Find
inB) is for making it possible to perform tracking control so that the rotary head correctly scans the recording track during reproduction by the output of the rotary head without providing a special head.

In other words, the ATF area is used to record the beginning and end of each track when compressing the time axis of the PCM signal and forming tracks diagonally on a magnetic tape using two rotary heads without guard bands. A tracking pilot signal is recorded in a separate recording area from the PCM signal, and during playback, the recording track is scanned by a rotating head whose scanning width is wider than the track width, and the rotating head scans both sides of the track being scanned. The reproduction output of the biloft signal from the adjacent track is used to control the tracking of the rotating head.

Then, the track pattern for this ATF is the first one.
As shown in Figure 6, the pattern shown is a drum diameter of 30mm, drum winding angle of 90'', and rotational speed of 20mm.
The case of 00 rpm will be explained.

ATFl and A in the front and rear parts of each track
TF2 is a low frequency signal f with little azimuth effect as a pilot signal for tracking.

This is used to detect the level of crosstalk from both adjacent tracks during playback, and to obtain the level difference between the crosstalk components of both adjacent tracks as a tracking error signal. A low frequency signal of f, 4/72 (130 KHz) is used as the pilot signal r1.

Furthermore, a sync signal for determining the position where the pilot signal f1 is recorded is recorded in ATFI and ATF2. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. Assuming that the head corresponding to +azimuth is A and the head corresponding to -azimuth is B, the sync signal distinguishes between A head and B head.
Therefore, the sync 1 signal ft with the frequency fM/18 (=522KHz) is used for the A head, and the frequency f M /1 is used for the B head.
l 2 (=784 kHz) sink 2 signal r.

are recorded at respective predetermined positions.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. For this reason, the frequency f, 4/6 (= 1.56 MH
z) erasure signal f4 is recorded.

The positions of the ATF pilot signals are all different between the on-track and both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Five blocks are allocated to each ATF area of ATF 1 and ATF2, and the pilot signal f1 is recorded in two of the blocks. The sync signal f,,f, is 1 from the center of the position where one adjacent track is recorded.
It is recorded using blocks or 0.5 blocks.

The pilot signal f1 of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. A sync signal of 1 block is assigned to an odd frame, and a sync signal of 0.5 block is assigned to an even frame.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, when a track of a magnetic tape recorded in the format shown in FIG. 15(a) is played back by each rotary head, the rotary head outputs an R as shown in FIG. 17(a).
An F-fold signal is obtained. For example, if this RF multiplied signal is obtained by reproducing the odd frame track (A) in FIG.
PF), a pilot signal f as shown in (b) is obtained.

Section I is due to on-track pilot signals, and sections ■ and ■ are due to crosstalk between pilot signals of (B) odd frame tracks and (B) even frame tracks. When the rotating head is correctly scanning on-track, the envelope levels of sections ■ and ■, that is, V■ and ■■ in (C), should be equal, but if there is a track deviation, ■■≠■ ■ becomes,
The amount and direction of deviation of the rotary head from on-track can be determined by its size and radiality. Therefore, by operating the capstan servo and finely adjusting the tape speed based on the difference between v■ and ■■, it becomes possible to run the rotary head on-track.

Also, as mentioned above, R-DAT does not have an erasing head,
Since the recording is performed for the second and third time due to overriding, it may not be possible to accurately detect the sync signal and sample ■ and ■ to generate a correct error signal.

That is, in R-DAT, recording can be performed within ±22 blocks from the center of the PCMfiJf area. Further, the recording level of the pilot signal f+ (-130 KHz) is to be slightly lower than the level of other signals. This is because low frequency signals are recorded at a deep level on the tape, and the previously recorded pilot signal f1 can be erased by the erase signal at the time of overriding. However, if the level of the pilot signal f is lowered in this way, when the biloft signal f1 is newly recorded at the previously recorded sync signal [2 or f3, the previous sync signal will not be completely erased. Sometimes it remains.

Specifically, when a later recording is performed ahead of the previous recording, the sync signal of the later recording always precedes the unerased sync signal of the previous recording by two tracks. Although this is not a problem, if the later recording is shifted backward, the unerased sync signal will precede the sync signal of the later recording. An example of this is when there is a deviation of 1 to 2 blocks later, and A
For TF-1, in (A) even frames and (A) odd frames, for ATF-2, in (B) even frames, (B) in odd frames, pilot signal f,
Part or all of the sync signal f2f3 of the previous recording will remain in the portion.

When this happens, the level of the frequency component of the pilot signal in the reproduced RF signal at that time is sampled according to the sync signal of the previous recording. Although this pilot signal should originally be at the crosstalk level of the sampling signal of one adjacent track, the sampled frequency component is the on-track pilot signal itself, and the level obtained by this sampling is an extremely large value. becomes. After that, the frequency component of the pilot signal in the reproduced RF signal two blocks later is sampled, the difference between this sampling value and the sample value two blocks before is taken, and this level difference is used as the amount of track deviation to control the capstan servo. However, since what is sampled first is the on-track level, not the crosstalk level of the adjacent track, a very large level difference that is far from the actual track shift amount is obtained. If this happens, the capstan servo will be disturbed and the tape running will be adversely affected.

The above was a case where the previous sync signal remained in the pilot signal portion recorded later, but the sync signal was replaced by the erased signal f.
There is a good possibility that the noise may not be completely erased by 4 and may remain as noise.

To solve the above problem, it is determined whether the detected sync signal is a regular sync signal or not, and if it is not a regular sync signal, the crosstalk between the pilot signals of both adjacent tracks based on the sync signal is determined. The capstan servo may not be controlled based on the level difference.

However, since the information for tracking the R-DAT itself is recorded in a distributed manner on each track, there are few opportunities to obtain this information. In such a situation, if you stop obtaining the level difference of the Kuko talk due to one false detection of the sync signal as described above, the capstan servo will become very difficult to operate, and you may need to increase the gain of the servo system, etc. However, when the gain is increased, it becomes weaker against external disturbances, and another problem arises.

〔the purpose〕

The present invention has been made in order to solve the above-mentioned problems, and is a digital camera that detects as many regular sync signals as possible and performs stable tracking control even if the recording quality of the recording medium is not good. The purpose is to provide a signal reproducing device.

[Summary of the invention]

In order to achieve the above-mentioned object, the present invention makes it possible to detect the sync signal again when the detected sync signal is not a regular sync signal. The crosstalk level difference between the pilot signals of both adjacent tracks can be sampled to enable higher performance tracking control.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, 1 is a rotating drum with a diameter of 30φ, and the rotating drum 1 has two rotating heads, A head IA for recording and reproducing +azimuth and B head IB for recording and reproducing one azimuth. The A head IA is spaced apart from each other.
Two pulse generators (PG), PGA and PGB, are arranged at an intermediate position between the B head IB and the B head IB.

2 is a crystal oscillator that generates a basic clock f,4 of 9.4 MHz, and the basic clock f14 is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system 6, and outputs a P B/REC switching signal to control switching of a toggle switch 4 consisting of switches SWI and SW2.

5 is a reference signal generator, which generates XHz (66Hz: 2P
G), YHz (depending on the number of FG of the capstan motor) and ZHz reference signals are generated.

Reference numeral 6 denotes a drum servo, which servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on a reference signal ZHz under the control of the system controller 3. Reference numeral 8 denotes a capstan servo, and during recording when the switch 4 is switched to the B contact side by the system controller 3, the rotation of the capstan motor is servo controlled based on the reference (f number YHz), and the switch 4 is switched to the A contact side. During playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is an ISWP (A/100) signal generator, and drum 1
The ISWP (A/100) signal is generated (switching between A head IA and B head IB based on the pulses from the two PGs above), and the ISWP (A/100) signal is H, B when A head is selected. This is also supplied to each part of the system.

10 is a phase reversal detection circuit, and tL to which CK large input is applied.
LE i book clock f M to HS W P (A/B
) signal is input, and the output is supplied to the S input of the initial flag latch 11. The initial flag latch 11 receives the CY small output of the initial counter 12 at its R input, and its Q output is supplied to the R input of the initial counter 12.

The initial counter 12 is the PB/Tf? from the system controller 3? A threshold value from the table 13 under the control of the T signal is set, and the CY small output becomes H by counting the set value.

PB printed via the CY small output inverter 13a
It is input to the encode data processing section 18 via the AND gate 13b which is opened and closed by the /REC signal, and
AND gate 13C opened and closed by PB/REC signal
to the S input of the head touch window flag launch 14.

The head touch window flag latch 14 is used to generate a window that prohibits the head touch detection operation during the noise period when switching the head.The Q output is input as an on signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, ISWP (A/
100) Encode data processing unit 18 (described later) based on the signal
The recording data is received and supplied to the rotary heads IA and IB via the switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
Data from the F-fold signal is extracted, and after being subjected to 10/8 conversion (demodulation), deinterleaving, error correction, etc., it is sent to the D/A converter, and also performs head touch detection, ATF sync detection, tracking error detection, etc. , an error signal is supplied from the track deviation signal generating section 17a to the capstan servo 8.

The encoded data processing unit 18 performs interleaving, parity addition, 8/10 conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above configuration, P from the system controller 3
A recording operation is performed when the B/REC signal is L.

Since the PB/REC signal is L, Suinochi 4 is b
The capstan servo 8 is switched to the contact side, a reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied based on the reference signal YHz, and tracking is controlled.

The H3WP (A/100) generator 9 outputs based on the pulses generated by PGA and PGB due to the rotation of the drum 1.
The 3WP (A/B) signal becomes H when the A head is IA, and becomes L when the B head is IB. This Hswp(A,/100) signal is input to the phase reversal detection circuit 10, and H3WP(A,/100)
B) When the signal level changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H for one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial flag latch 11 is set and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic clocks f corresponding to a fixed period corresponding to 3.75 m5 according to the set value from the table 13, the CY ratio output rises, and the initial flag latch 11 is thereby activated. At the same time as being reset, the rising edge of the CY ratio output is applied to the encode data processing section 18 as a recording start signal.

Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined format.

Next, when the P B/RE signal from the system controller 3 is H, the switch 4 is set to the a side, and the rotating head I
A and IB are connected to the reproduction amplifier 15 and supplied to the RF multiplied signal decode data processing section 17 .

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The amount of track deviation is an ATF error signal that corresponds to the level difference in the amplitude of crosstalk between pilot signals of both adjacent tracks, and the details will be described later.

H5WP (A/B) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 becomes a playback mode counter based on the set value from table 13, and the count value is, for example, 100 μs/1.
When the value corresponds to m s, the CY ratio output becomes H. This prohibits the head touch operation, which will be described later, while noise occurs when the head is switched, and sets the head touch window flag latch 14 via the AND gate 13 after the above-mentioned certain period of time, and outputs its Q output. This is to set it to H and output an on signal for head touch detection. When the decode data processing unit 17 detects a head touch, that is, a contact between the tape T and the head IA or IB to output an RF multiplied signal, the ON signal from the head touch window flag latch 14 is output from the head touch window flag latch 14. is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproducing amplifier 15, a band pass filter (BPF) 101, and an envelope detector 102.
, the first sample hold (S/H) circuit 103, the 23rd
/H circuit 104, third S/H circuits 105a and 105
b,) Glue switch 106, comparator 107, differential amplifier 108, level correction circuit 109, and resistor R1
It consists of ~R4.

On the other hand, the digital system includes a crystal oscillator 2, a head touch detection circuit 201, a sync detection circuit 202, an ATF timing generator 203, a regeneration flag latch 204, a system counter 205, a timing generator 206, a 1/2 frequency divider 207, and an ATF initial flag. latch 208,
It consists of a power-on reset circuit 209, a latch circuit 210, a protection counter 2111, a noise error latch 212, a latch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, to explain from the analog system, the RF multiplied signal is input from the rotary heads IA and IB (Fig. 1) to the input of the reproduction amplifier 15, and its output is input to each input of the BPF IOL, the head touch detection circuit 215, and the sync detection circuit 216. Supplied.

The BPFIOI passes only the 130 KHz component in the RF signal and inputs it to the envelope detector 102. The envelope detector 102 envelope-detects the 130KHz component, and sends it to the S/H circuits 103, 105a, 105.
b to each input of the differential amplifier 108.

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SPI applied from the sync detection circuit 202 to the C input, and outputs this to one input of the comparator 107 and the output of the differential amplifier 108. Apply each. What is sampled and held by the S/H circuit 103 is the DC level of the crosstalk of the biloft signal of one adjacent track.

The S/H circuit 104 receives a signal whose level has been adjusted by the level adjustment circuit 109 at its input, samples and holds this signal using the sampling signal SP2 from the ATF timing generator 203, and outputs the signal to the capstan servo 8 (Fig. 1).
is supplied as an ATF error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The S/H circuit 105a samples and holds the output from the envelope detector 102 using the sampling signal 5P3A from the ATF timing generator 203, and outputs it to one end of the resistor R1 and the a contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105a samples and holds is the D of the on-track pilot signal when A track is played back.
It is C level.

The S/H circuit 105b samples and holds the output from the envelope detector 102 using the sampling signal 5P3B from the ATF timing generator 203, and outputs this to one end of the resistor R3 and the b contact of the switch SW1 of the toggle switch 106.

What the S/H circuit 105b samples and holds is the D on-track pilot signal when B track is played back.
It is C level.

Resistors R1 to R4 have the same value, and S/H circuits 105a and 10 are added to one end of resistors R1 and R3, respectively.
This is for dividing the output of 5b. The mutual connection point of the resistors R3 and R2 and the mutual connection point of the resistors R3 and R4 are respectively connected to the a contact and the b contact of the switch SW2 of the toggle switch 106. A level 1/2 of the sample hold value is obtained.

The toggle switch 106 is controlled by the H3WP (A/100) signal, and when the H3WP (A/100) signal is H, the a
side, and when it is L, it is switched to the b side.

The comparator 107 has one input connected to the S/H circuit 105a.
and 1/2 level of the output of 105b is connected to resistors R1 to R4.
and is applied via the switch SW2, and the output of the S/H circuit 103 is applied to the other input. Comparator 1
07, when 1/2 of the sample and hold values of the S/H circuits 105a and 105b is greater than the output level of the S/H circuit 103, its output becomes H, and this is supplied to the input of the ATF timing generator 203 as an OK signal. .

The differential amplifier 108 separates the output of the envelope detector 102, which is applied to the input power, and the S/D output, which is applied to the input power.
The difference between the output of the H circuit 103 and the output of the H circuit 103 is taken and inputted to the level adjustment circuit 109. That is, envelope detector 1
The output of 02 is the DC of the crosstalk of the other adjacent track.
When outputting the level, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

The level adjustment circuit 109 includes S/H circuits 105a and 10
5b, that is, the output level of the on-track pilot signal, the signal level from the differential amplifier 108, that is, the crosstalk level difference between the biloft signals of both adjacent tracks, is adjusted. This is to correct variations in the output level between the two. The level adjustment circuit 109 may be, for example, an analog division circuit that divides the crosstalk level difference between the pilot signals of both adjacent tracks as the numerator and the output level of the on-track pilot signal as the denominator, or a gain circuit as shown in FIG. A variable amplification circuit can be applied.

In FIG. 3, the comparator 109a has one input inputted with the level of the on-track biloft signal sampled and held in the S/H circuit 105a or 105b, and the other input inputted with the reference voltage ■, as a threshold level. The output becomes H when the level of the pilot signal is greater than 1. In the window comparator 109b, the level of the pilot signal is input to the first input, and the reference voltages v1 and 2 are input to the second and third inputs, respectively, so that the level of the pilot signal is as follows.

The output becomes H when the reference voltages (1) and (2) are between the two threshold values. Comparator 109
In c, the level of the pilot signal is inputted to one input, and the reference voltage v2 is inputted to the other input as a threshold value, and when the level of the pilot signal is smaller than the reference voltage 2, the output becomes H.

The amplifier 109d has resistors 109h to 109j connected between its input and output via switches 1096 to 109g that are turned on when the outputs of the comparators 109a to 109C are H, and the input is connected to the differential amplifier 1 via a resistor 109k.
08, and its output is connected to the input of the S/H circuit 104.

The resistors 109h to 109j determine the gain of the amplifier 109d, and the gain is the smallest when the resistor 109h is connected, and the gain increases sequentially as the resistors 109i and 109j are connected. That is, S/H
As the signal level from the circuit 105a or 105b, that is, the pilot signal level increases, the amplifier 10
The gain of 9a becomes smaller, and accordingly, the difference in level of crosstalk between the pilot signals of both adjacent tracks is output at a smaller level than in other cases. and,
When the level of the on-track pilot signal is low, the crosstalk level difference is output at a higher level than in other cases. As a result, the A rotating head IA
Variations in crosstalk level differences due to variations in characteristics between the rotating heads IB and B are automatically absorbed and corrected.

Although not shown, if the level adjustment circuit is constituted by a division circuit, for example, if the level of the on-track pilot signal of the A rotary head IA is IOV and the crosstalk level difference is 4V, the result of division is is 4/10=0
．． It becomes 4V. On the other hand, if the on-track pilot signal level of B rotating head IB is 8V and the crosstalk level difference is 3.2V, the division result is 3.2/
8 = 0.4V. That is, even if there is a difference in output level between the A and B rotary heads, the same value is output as the ATF error signal, and variations in the crosstalk level difference are corrected.

Next, to explain the digital system, the head touch detection circuit 201 detects the touch window frame 1
4 (Fig. 1) and the basic clock f, 4
This detects that the RF multiplied signal has been input and supplies the signal to the S input of the reproduction flag latch 204, the details of which will be described later.

The sink detection circuit 202 receives the RF multiplied signal H5WP (A/B
) signal, the ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise flag latch 212, the basic clock "8" from the crystal oscillator 2.
, and the enable clear signal from the OR gate 216 are input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to its output. The sampling signal SPI is connected to the C input of the S/H circuit 103 and the latch 210.
The enable signal and detection pulse signal are connected to the R input of the A
Each is input to the TF timing generation circuit 203.

The sync detection circuit 202 converts the RF multiplied signal into a digital signal, detects the beginning of the ATF sync patterns SYl and SY2 of the rotary heads IA and IB, outputs a sampling signal SPI, and then outputs a sampling signal SPI to the continuously detected sync patterns. It operates to output a detection pulse signal to the target, and the details will be described later.

The ATF timing circuit 203 includes an OK multiplied signal which is the output of the comparator 107, an ODD/EVEN signal which is the Q output of the 1/2 frequency divider 207 (7), an initial signal which is the Q output of the ATF initial frang latch 208, and a sink detection circuit. The enable signal and the detection pulse signal from 202, the "after/punishment" signal from the timing generator 206, the enable clear signal from the OR gate 216, and the basic clock f,4 from the crystal oscillator 2 are inputted, and the sampling signal SP2 is outputted from the crystal oscillator 202. .5P3A, 5P3B
, an erroneous detection signal, and an ATFEND signal. The sampling signal SP2 is generated by the C input of the S/H circuit 104 and the AT
The sampling signal 5P3A is connected to the S input of the F initial frang latch 208, the sampling signal 5P3B is connected to the C input of the S/H circuit 105b, and the false detection signal is connected to the S input of the latch 210 and the OR gate 2.
16 and the CK large input of the false detection counter 214, the ATFEND signal is the 1 of the OR gates 216 and 217.
input into two inputs, respectively.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer link (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and specifies the If the detected pulse exceeds the specified value by the time of , the sampling signal SP
It outputs 2.5P3A and 5P3B, and operates to output an erroneous detection signal when it is below a specified value or at the L level of the OK multiplied signal which is the output of the comparator 107, and the details will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of channel bit data of the R-DAT, and outputs a basic clock fM. The basic clock f, 4 is used by the head touch detection circuit 201, the sync detection circuit 202, and the ATF.
The CK large inputs of the timing generator 203, system counter 205, and protection counter 211 are applied, respectively.

The latches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes 1 in response to a rising edge of the S input (and whose Q output becomes L in response to a rising edge of the R input).

The output of the head touch detection circuit 201 is input to the S input of the playback flag latch 204, the END signal which is the output of the timing generator 206 is input to the R input, and the Q output thereof is input to the R input of the system counter 205. When the Q output of the regeneration flag latch 204 is H, the regeneration operation is in progress.

The system counter 205 receives the Q output of the reproduction flag latch 204 and the CK large input basic taro, 7ri f, and 4 into the R input, respectively, and the output Q o '' Q x is input to the timing generator 206 .

This system counter 205 is for roughly indicating the position on the track where each signal is recorded.

The timing generator 206 generates an ATF window set signal, a rear/■ double signal window clear signal, and an END signal at its output based on the Q, ~Qx outputs from the system counter, and sends the ATF window set signal to the sync detection circuit 202. The window clear signal is sent to the rear/■ double signal ATF timing generator 203 by the OR gate 2.
17, and play the END signal flag latch 204
8 manpower each. This timing generator 206 decodes the output of the system counter 205 and generates the timing required for each part.

1/2 frequency divider 207 receives 1■SWP to which CK large input is applied.
(A/100) Divide the signal by 1/2 and output Q output with ODD/E
Generates the VEN signal and supplies it to the A T F timing generator 203 . The R input of the 1/2 frequency divider has A.
The Q output of the TF initial flag latch 208 is manually input.

ATF initial flag latch 208 is AT manually
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. The ATF initial flag launch 208 is ATF
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The latch 210 connects the ATF timing generator 203 to the S input.
The sampling signal SPI from the sync detection circuit 202 is input to the R input, and the Q output is input to the R input of the protection counter 211. When the latch 210 detects an error, the Q output becomes H and is reset in response to the output of the sampling signal SP1.

The protection counter 211 is only for counting a certain period of time from erroneous detection, and the basic clock f? is applied with a large CK input only when the R input is H? I count operation, R
Cleared by input.

The Q output of the latch 210 is input to the R input, which is input to the CY ratio output OR gate 217.

The noise-if-flat latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The Q output of the latch 213 and the CY ratio output of the large CK input sampling counter 215 are respectively input to the D input of the latch 212, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

In the latch 213, the CY ratio output of the error detection counter 214 is input to the S input, the CY ratio output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise error counter 212.

The false detection counter 214 receives the false detection signal from the CK large input ATF timing generator 203 and the CY ratio output of the sampling counter 215 at its R input, and is supplied to the S input of the CY ratio output latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SP1 is erroneously detected in a certain period of time, and when it exceeds a certain value, the CY ratio output becomes H.

The sampling counter 215 receives CK large input H3WP (
A/B) signal is input, CY ratio output error detection counter 2
14, the R input of the latch 213, and the CK large input of the noise-if-flat latch 212.

The OR gate 216 connects the false detection signal from the ATF timing generator 203 and the ATFEND signal to the protection counter 21.
The CY ratio output of 1 is input, and the sync detection circuit 2 is connected to the output.
02 and an enable clear signal to the ATF timing generator 203.

OR gate 217 is a window clear signal from timing generator 206, ATF timing generator 20
3 and the CY ratio output from the protection counter 211 are respectively input, and an ATF window off signal is sent to the sync detection circuit 202 at its output.

In the above configuration, the head touch detection circuit 201 and the sync detection circuit 202 pass through the RF double signal regeneration amplifier 15.
and the BPF 101. B.P.
Only the 130 KHz component of the RF multiplied signal supplied to F 101 is passed. The amplitude level of the 130KHz component is converted to a DC level by the envelope detector 102, and then the S/H
It is applied to the inputs of each of circuits 103, 104, 105a and 105b, and to the differential amplifier 108.

The envelope detector 102 sequentially outputs the DC level of the amplitude of the crosstalk of the pilot signal of one adjacent track, the amplitude of the crosstalk of the pilot signal of the other adjacent track, and the amplitude of the pilot signal of both adjacent tracks. ri of the signal or the DC level of the amplitude of the on-track pilot signal is output.

The S/H circuit 103 samples and holds the DC level of the pilot signal of one adjacent track at the timing of the sampling gain signal SPI from the sync detection circuit 202. It is applied to the power of amplifier 108 .

The S/H circuit 105a changes the DC level of the on-track pilot signal during playback of +azimuth A track to the S/H circuit 105a.
The ZH time 1105b samples and holds the DC level of the on-track pilot signal while the -azimuth B track is being reproduced. The output of the S/H circuit 105a, that is, the DC level of the on-track pilot signal, is supplied to the control input of the level adjustment circuit 109 via the a contact of the switch SW1 of the toggle switch 106, and is adjusted to 1 by the resistors R0 and R2. /2 and then supplied to one input of the comparator 107 via the a contact of the switch SW2. Similarly, S/H circuit 10
The output of 5b is supplied to the level adjustment circuit 109 via the b contact of the switch SWI, and after being divided into 1/2 by resistors R3 and R4, is supplied to one input of the comparator 107 via the b contact of the switch SW2. Ru.

The comparator 107 becomes the OK multiplication signal 11 when the level input via the switch SW2 is higher than the input from the S/H circuit 103. In other words, it is determined that the crosstalk level of one adjacent track has been correctly sampled. In the opposite case, it is determined that the on-track level has been sampled. Therefore, when the OK double signal is L, it is determined that the sync has been erroneously detected. This OK
The double signal is supplied to the ATF timing generator 203.

When the envelope detector 102 is outputting the DC level of the crosstalk amplitude of the other adjacent track, the differential amplifier 108 inputs the I)C level of the crosstalk amplitude of one adjacent track. Because
The difference in the DC level of the crosstalk between both adjacent 1-L2-2, that is, the amount of track deviation, is obtained as an output, and this is input to the level adjustment circuit 109.

The level adjustment circuit 109 is the S/H circuit 105a and 105
The output of b is applied as a control input, and when the control input is large, the level of the human input signal is lowered, and when it is small, it is raised and output.

In short, the level adjustment circuit 109 automatically corrects variations in the outputs of the two rotary heads and inputs the resulting signal to the next S/H circuit 104. The S/H circuit 104 samples and holds the corrected deviation amount of both adjacent tracks using the sampling signal SP2. The output of this S/H circuit 104 is supplied to the capstan servo 8.

FIGS. 4(a) to 4(il) are timing charts showing signal waveforms generated in each part by the above operations, corresponding to the symbols attached to each part.

The H3WP (A/100) signal shown in Fig. 4 fbl is
When reproduced by B, it becomes L. H3 when the head is switched
The phase of the WP (A/B) signal is reversed. When the phase is reversed, the Q output of the initial flag latch 11 (FIG. 1) becomes H, and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is judged that the tape has passed a noisy part, and the head touch window flag latch 14 (FIG. 1) is set to make its Q output H. Q output of head touch window flange latch 14 is H
Then, the head touch detection circuit 201 operates.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF multiplied signal is reproduced, its output becomes H.
, set the regeneration flag latch 204 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 is the Q of the system counter 205.

Based on the ~QX output, an ATF window set signal is supplied to the sync detection circuit 202 just before the recording of ATF-1 and ATF-2.

After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects sync 1 (= f
2) and the pattern of sync 2 (=f3) in the case of B head IB, each sync is detected based on the relationship shown in the table below depending on the frame.

Here, when the sync detection circuit 202 detects 4 syncs in a normal case or 5 syncs in a row in a noisy case, it outputs a sampling signal SPI, and the crosstalk of the pilot signal r1 of one adjacent track is sent to S/8 times 9103. The level of the ATF timing generator 203 is sampled and held, and an enable signal is supplied to the ATF timing generator 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SPI is output from the sync detection circuit 202.
Check whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI. Next 1.2
After 5 blocks, it is determined whether the sync is detected at a specified value or more, and if it is above the specified value, it is assumed that the sync has been detected correctly and the sampling signal SP2 is sent to S/H after 2 blocks.
The signal is supplied to a circuit 104 to sample and hold the crosstalk level difference between both adjacent tracks, and its output is supplied to the capstan servo 8 as the amount of track deviation.

In addition, if the on-track pilot signal r exists after the sync, when playing back by the A head IA,
Since TF-2 and B heads are being played back at ATF-1, in this case, the sampling signals 5P3A and 5P3B are output after 4 blocks, and these are supplied to the S/H circuits 105a and S/H 105b, respectively. Sample and hold the level of the on-track pilot signal being played by each head.

If the above series of operations are performed correctly, ATFEN'
A D signal is output, and this is sent to the sink detection circuit 202 and A as an enable clear signal via an OR gate 216.
The signal is supplied to the TF timing generator 203. ATFEN
The D signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. Ru.

Missampling, that is, the output of the comparator 107 is L, and the level of the on-track pilot signal is S/H.
If it is determined that the circuit 103 has sampled and held,
If the sink is not equal to or greater than the specified value, the erroneous detection signal is set to H, the Q output of the latch 210 is set to H, and the protection counter 211 is caused to perform a counting operation, and the erroneous detection counter 214 is caused to perform a +1 operation. When the false detection signal becomes H, the enable clear signal to the sink detection circuit 202 and ATF timing generator 203 via the OR gate 216 also becomes H.

When the enable clear signal becomes H, the sink detection circuit 2
02 performs the operation of detecting the sync again from the beginning, and once the sync is detected, outputs the sampling signal SPi again. On the other hand, the ATF timing generator 203 sets the sync detection counter and timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal s.
When P1 is output, the latch 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the CY ratio output of the protection counter 211 becomes H after the erroneous detection signal is output once, that is, after a specified period of time (2.5 blocks), the sync detection circuit 202 and ATF timing generation are performed via the OR gate 216. The enable clear signal to the device 203 becomes H, and the operation stops.

Moreover, the sampling counter 215 is II S W P
(A/100) The rising edge of the signal is +1, but this is managed by the length of the tape, and if the number of false detections exceeds a certain level during that period, the CY ratio output of the false detection counter 214 becomes H. As a result, the Q output of the noise corrector 213 is set to H to notify the sync detection circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent large dropouts.

Note that FIGS. 5(a) to 5(C1) and (A) to (G) are timing charts showing the outline of the signal waveforms of each part of the digital system after the initial flag latch 11 is set during playback, and the corresponding The reference numerals are given in FIGS. 1 and 2.

FIG. 6 is a block diagram showing a specific example of the configuration of the head touch detection circuit 201 described above.

In the figure, the comparator 1-1 has an RF multiplied signal inputted to one input, and a reference voltage element 2 inputted to the other input. Comparator 1-2 has an RF multiplied signal on one input,
The reference voltage -■ is input to the other input.

The output of comparators 1-1 and 1-2 is or game 1-1
-3, a D-type flip-flop (FF
) is connected to the D input of 1-5 and is further connected to the capacitor 1.
-6 to ground.

The D-type FF1-5 receives the CK large input basic clock fH, and its Q output is connected to the input of the AND gate 1-7, and the Q output is connected to the input of the AND gate 1-8.

The basic clock fH is input to the inputs of the AND gates 1-7 and 1-8, and the outputs of each are connected to the UP input and I) OWN input of the up/down counter 1-9, respectively. QA of amplifier down run 1-9
- The QD ratio output is connected to the input of the AND gate 1-8 via the OR gate 1-10, and to the CK input of the CY ratio output D type FF1-11. The 0 output of the D type FFL-11 is connected to VCC, and the Q output is connected to the touch detection circuit 201.
This is the output.

Up/down counter 1-9 and D type FF1-11 2
For human power, head touch window flang latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, if the level of the comparator 1-1 is higher than the RF multiplied signal +■, the output becomes H1, and if it is lower, the output becomes L. For example, if the level of the comparator 1-2 is higher than that of the RF multiplied signal 1, the output becomes H1, and if it is lower, the output becomes L. That is,
When the RF multiplied signal is not within the range of ±V, the output of the OR gates 1-3 becomes H.

The fffi resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise etc. leaked to the output of the OR gate 1-3. The output of the OR gate 13 from which spike noise has been removed by the integration circuit is a D-type F.
Applied to the D input of Fl-5.

The D-type FF1-5 samples the state of the D input using the basic clock r applied to the CK input, and outputs the state to the Q output. The 0 output is the inverted output of the Q output. The Q output of the D-type FF1-5 is applied to the other input of the AND gate 1-7, which has the basic clock f, 4 applied to one input, and the Q output of the D-type FF1-5 becomes H.
At this time, the UP large input basic clock f4 of the up/down counter 1-9 is inputted via the AND gate 1-7. Therefore, the up/down counter 1-9 up-counts the basic clock "8" when the Q output of the head touch window flange latch 14 is H, the window is standing, and the Q output of the D-type FF 1-5 is H.

When the Q output of the D-type FF l-5 is L, that is, when the RF multiplied signal level is within -V and it is determined that there is no signal, the 0 output becomes 11. In this state, QA-Q of up/down counter 1-9.

When any one of is H, that is, when the counter is not 0, the basic clock fM is
OWN is applied to the human power, and the up/down counters 1-9 perform a down-counting operation. Furthermore, due to this down count or reset, the contents of the counter become O and Q.
When all the outputs of A-QIll are L, the output of OR gate 1-10 is L, and the output of AND gate 1-10 is L.
8 is closed, so the basic clock f14 is not supplied to the DOWN input.

When the up/down counter 1-9 up-counts, a carry occurs and the CY ratio output becomes H, this rise causes the D-type FF1-11 to memorize the state of the D input. Since the D input is H, the Q output becomes H.

7+a) to U) are timing charts showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in FIG. 7(a) is input.

In a state where the RF multiplied signal is present, the amplitude is continuously greater than ±■, and in a state where there is no signal, that is, where the head is not in contact with the tape, there is almost no amplitude greater than ±■.

Note that ±■ is set to a value that makes it possible to clearly distinguish between a signal and noise.

In response to the RF multiplied signal input as shown in (al), a waveform as shown in (bl) appears in the output of the comparator 1-1, and a waveform as shown in (C1) appears in the output of the comparator 1-2. The output of OR gates 1-3 includes (b
A waveform as shown in l and (fd obtained by logical sum of the waveforms of C1) appears. As is clear from the waveform in (d), there is gate leakage etc. in the output of gates 1-3. This gate leakage is removed by the integrating circuit, and the D-type FF1-5
A signal having a waveform as shown in fe) is input to the input of .

As a result, a waveform as shown in parentheses appears in the Q output of D-type FFL-5, and the period when the Q output is H is AND gate 1-
When the basic clock fH passes through 7, a signal as shown in (gl) appears at the output of AND gates 1-7. On the other hand, a signal as shown in (hl) appears at the output of AND gates 1-8. .

Incidentally, noise components slightly exceeding ±■ and gate leakage are removed by the integrating circuit1, but when noise with a large amplitude appears singly, it cannot be completely removed by the integrating circuit.

Signals (g) and fhl are applied to the UP large input and DOWN input of the up/down counter 1-9, respectively.

When the up/down counter 1-9 counts a predetermined number, it sends out a carry as shown in O) as a CY ratio output, and in response, the D-type FF1-11 stores the D input, and the Q output becomes (J). Stand up as shown.

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down counters 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 8 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H3WP (A
/100) signal, basic clock f, , ATF window cent signal, ATF window clear signal, noise signal, and enable clear signal are input.

A, which is supplied with the RF multiplied signal from the reproduction amplifier 15 (Fig. 1)
The TF equalizer 2-1 is the band 4 of the ATF sync signal.
00KHz to 900KHz is emphasized and output to the limiter 2-2. The limiter 2-2 converts the signal into an RF multiplied digital signal by setting H5 if the amplitude of the signal is larger than a specified level and L if it is smaller.

The output of limiter 2-2 is CK large input basic clock f,
4 is supplied to the D input of the D-type FF 2-3, and also to one input of the exclusive (E) OR gate 2-4.

The other input of the EOR gate 2-4 is supplied with the Q output of the D-type FF 2-3, and the FOR gate 2-4 and the D
The type FF2-3 constitutes a phase reversal detection circuit.

The ATF window cent signal is supplied to the S input of the A'l''F window latch 2-5, which receives the ATF window clear signal at its R input, and the ATF window signal is supplied from the Q output of the ATF window latch 2-5. Output.

The output of the EOR gate 2-4 is supplied with the CK large input basic clock rH to the D input of an 11-stage shift register 2-6 whose R input receives the ATF window signal from the ATF window latch 2-5. Ru. The Q output of the 11-stage shift register 2-6 is passed through the inverter 2-7 to the AND gate 2-8 and the AND gate 2-9.
2~Q.

The output is output to AND gates 2-8 and 2-9, Qb"""Q
8 outputs are connected to NOR gate 2-10 and AND gate 2-9, Q, to Q7. The outputs are respectively supplied to the Noah gates,
The outputs of NOR gates 2-10 and 2-11 are supplied to AND gates 2-8 and 2-9, respectively. Inverter 2-12 is used for AND gates 2-8 and 2-9.
The inverted and previous H5WP (A/B) signals are supplied respectively. The outputs of AND gates 2-8 and 2-9 are supplied to the input of OR gate 2-13.

The output of the OR gate 2-13 is the 29-stage shift register 2-14 to which CK large input basic clock 2, f, 4 is input.
0 manpower is supplied. 29-stage shift l-register 2-1
4's Ql output goes to the input of AND gates 2-15 to 2-20, and becomes H when sink 2, ~ QIl output goes to the input of ORG/-1-2-21, and becomes H when sink 1 Q
, ~Ql+ output is the input of OR gate 2-22, Q, which becomes H when sink 2, □~Q14 output is the input of OR gate 2-22.
23, Q18-Q2° which becomes H at both sink 1 and sink 2 output is connected to the input of OR gate 2-24, and Q2? which becomes H at sink 1. ~C1zz outputs are respectively supplied to inputs of OR gates 2-25.

The output of OR gate 2-21 is connected to the input of AND gates 2-16 and 2-18 and the input of OR gate 2-26, and the output of OR gate 2-22 is connected to AND gates 2-15 and 2-18.
-17 and the input of OR gate 2-27, the output of OR game 1-2-23 is
-18 and the input of the OR gate 2-26, the output of the OR gate 2-24 is connected to the AND gates 2-15 to 2-1.
8 and the input of OR gate 2-27, and the output of OR gate 2-25 is supplied to the input of AND gate 2-15, respectively. Further, the outputs of OR games 1-2-26 and 2-27 are supplied to the inputs of AND gates 2-20 and 2-19, respectively.

H3WP (A/100) signal is applied to Hokuki AND gate 2-15, 2-17 and 2-19, and AND gate 2-16,
The H3WP (A/100) signal inverted by the inverter 2-12 is supplied to 2-18 and 2-20, respectively. Further, the AND gates 2-15 and 2-16 are supplied with a noise-like signal, and the AND gates 2-17 and 2-18 are supplied with a noise-like signal inverted by an inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28', and the output of the OR gate 28 is output as a detection pulse signal via the AND gate 2-29. On the other hand, the above AND gates 2-15 to 2-18
The output of OR gate 2-30 is supplied to OR gate 2-30.
The output of -30 is outputted as a sampling signal SPI via AND gate 2-31, and an enable clear signal is supplied to the R input of ATF enable latch 2.
-32 S input. The Q output of the ATF enable latch 2-32 is output as an enable signal and is also supplied to the input of the AND gate 2-29. This output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

A digital signal corresponding to sink 1 and sink 2 for ATF in the RF multiplied signal is output to the limiter 2-2, and the output of the EOR gate 2-4 becomes one clock in accordance with the phase inversion of the digital signal.

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK large input when the window signal from the ATF window latch 2-5 applied to the R input is H. The D input is taken in according to the rising edge of the basic clock "A" and sent to the Q output, and thereafter it is shifted sequentially at every rising edge of the basic clock 1.4.
Send to Q11 output. That is, shift register 2-
6 delays the output of the EOR gate 2-4 by 1 to 11 clocks and sends it to the Ql-Qll outputs.

When the Ql ratio output is L, that is, when there is a change, this is passed through the inverter 2-7 to the AND gates 2-8 and 2.
-9, and one of the Q6 to Qll outputs goes low.
Then, one input of the AND gate 2-8 is set to H via the Nandt gate 2-10. Q2 to Q, when there is no change in the output, it is I]. At this time, H3WP
If the (A/100) signal is present, H is applied to the input of the AND gate 2-8 via the inverter 2-12.

In this state, all inputs of AND gate 2-8 become H, and the output becomes I (.Therefore, when this condition is not met, the output remains L and does not change for at least 4 clocks. , there is a change in the 5-7 clock period, H3WP
When the (A/B) signal is being reproduced by the B head IB, 1/2 cycle of the sync 2 signal is detected. Note that in reality, the sink 2 signal f 3 (= 78
4 KHz, f, 4/12), the length that does not change is 6 clocks, but a margin of ±11 clocks is allowed due to clock timing, jitter, etc.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

Further, from the output of the AND gate 2-9, the sink 1 signal f is obtained through the same processing as the sink 2.

(-520KHz, fH/1 B) is H3WP (A
/B) When the signal is being reproduced in Hl, that is, in the head IA, it is detected and output from the AND gate 2-9. Note that the period with no change is 7 clocks, which is 8 to 10 clocks.
Changes occur between clocks.

The sink 2 signal is sent from the AND gate 2-8 when the H3WP (A/100) signal is L, and the sink l signal is sent from the AND gate 2-13 from the AND gate 1-2-9 when the H3WP (A/100) signal is H. output via shift register 2
-14 is applied to the D input.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock, sends it to the Q1 output, and thereafter shifts it every time the clock is applied and sends it to the Q2 to Q29 outputs.

That is, the state of the D input is output to the Q,'-"Q2. output with a delay of 1 to 29 clocks.

When there is a change in the Q and output of the shift register 2-14, the Q1 output becomes H. Sink 2 signal (f 3 = 7
In the case of 80 KHz, 1/12 f, 4), if there is a change 1/2 cycle before the Q1 output, the output of the OR gate 2-21 becomes H. Further, if there is a change one cycle before, the output of the OR game) 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. OR game) 2-26 output is output from AND gate 2 along with Q, output and H3WP (A/B) signal of shift register 2-14.
-20 input. In other words, in the case of sink 2, an output appears at the QI output after a one-crotter delay after detecting sink 2 by the AND gate 2-8, and at this time, the change 1/2 period before is an or game) 2-21 and 2-26
, and the change from one cycle before is applied to the AND gate 2-20 simultaneously through 2-23 and 2-26, the output of AND gate 2-20 becomes H, and this Accordingly, the output of the or game 1-2-28 becomes H.

The output of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink is 2, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SP1 via the OR gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable latch 2-32. The Q output of 2-32 becomes H and the Q output becomes L. The Q output is output as an enable signal and is applied to the AND gate 2-29.
After that, the detection pulse signal can be outputted.

In the case of sink 2, when the noise signal is I(), the output of AND gate 2-16 becomes 11, and a similar operation is performed.

On the other hand, when sink 1, or gate 2-22°2-2
When the outputs of 4 and 2-25 become H, and the noise signal is L, the output of AND gate 2-17 becomes H, and when the noise signal is H, the output of AND gate 2-15 becomes H, and as described above. A similar thing is done.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

FIGS. 9A to 9G are timing charts showing waveforms of various parts during detection of the sync 2, and corresponding symbols are given in FIG.

Moreover, FIGS. 10(A) to 10(E) are timing charts showing waveforms of various parts when detecting the sink 1, and corresponding symbols are given in the figures.

FIG. 11 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
signal, basic clock f, H5WP (A/100) signal,
enable signal, enable clear signal, rear/front signal,
The OK double signal initial signal and detection pulse signal are input.

Enable signal to E input, CK large input basic clock f,
4, and the 0 and 25 block counters 3-1 to which the enable clear signal is input to the R inputs are 9.
After counting for 5 μs, the CY output becomes H, which is input to the E input of the high counter 3-2 and the C input of the decoder 3-3, respectively.

The high counter 3-2 has a CK large input basic clock r14,
Enable clear signals are input to the R inputs, and the clocks 1 to 1 are raised every 0.25 blocks. Q of the counter 3-2. -Q3 (2° to 23) output is input to the decoder 3-3.

Decoder 3-3 is for decoding each time,
Only when the C input is H, the 0 to 8.16 and 17 outputs become active, and the 0 to 8 outputs send 0.25 to 2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is input to the gates 3-4 to 3-11, and the 0.5 block signal is input to the latch 3-12.
R input of , is supplied to CK human power of D type FF3-13, 1
The block signal is supplied to the CK large input of the D-type FF3-14.

The decoder 3-15, which receives the H5WP (A/100) signal and the rear/previous signal, respectively, outputs the A that is currently being played.
This is for decoding the position of the TF signal, and B-ATF-1, A-ATF-1, B-ATF-2 is used for 0 to 3 outputs.
and A-ATF-2 signal as output, which is sent to the gate 3 above.
-4 and 3-7 as well as gates 3-16 and 3-17.

Table 3-18 to which the H3WP (A/100) signal and the initial signal are input holds the sink detection threshold value, and the held threshold value is switched by the H3WP (A/B) signal and the initial signal. and sets it in the sync detection counter 3-19.

With the H5WP (A/100) signal, each section for sync 1 when playing A head and for sync 2 when playing B head is set, and each section is set at 50% of the number of consecutive sync patterns.
It becomes. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-27 and inverters 3-28 to 3-30.

Then, the sample signal SP2 is applied to the output of the game 1-3-10.
, an erroneous detection signal is output to the output of gate 3-26, a sample signal 5P3A is output to the output of gate 3-4, an ATFEND signal is output to the output of gate 3-27, and a sample signal 5P3B is output to the output of gate 3-7. .

In the above configuration, when the sync detection circuit 202 generates the sampling signal SP1, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK multiplication signal, which become H at the falling edge of the sampling signal SP1. The CY output becomes H every time. The decoder 3-3 decodes the state of the high counter 3-2, and its output becomes H only when the CY ratio output of the 0.25 block counter 3-1 is H.

When the O output of the decoder 3-3 appears, that is, 0.25 blocks after the generation of the sampling signal SPI,
If the crosstalk sample value of one adjacent track is less than 1/2 of the on-track level, OK double signal L
Therefore, the D output of the decoder 3-3 does not appear at the output of the AND gate 3-8 which is input via the OK multiplication signal inverter 3-9. However, if there is no OK double signal, the output of AND gate 3-8 becomes H,
This is output from the OR gate 3-26 as an erroneous detection signal.

When the 1 output of the decoder 3-3 becomes 1 (0.
As a process after 5 blocks, this is ORGATE 3-11
is applied to the input of the sink detection counter 3-19 via the R input of the latch 3-12 and the D-type FF 3-.
13 CK large inputs are also applied.

Since the CY ratio output of the sync detection counter 3-19 is input to the D input of the D-type FF 3-13 via the latch 3-12, it is possible to determine whether there is a detected pulse signal greater than the specified value after 0.5 blocks. This happens every time the D-type FF 3-13 samples the signal. At the same time, the launch 3-12 is reset and the sync detection counter 3-12 is reset.
19, set the threshold value again from Table 3-18.

When the 3 outputs of the decoder 3-3 are 11, processing after one block is performed, and the output is transmitted via the CY ratio output latches 3-12 of the sync detection counters 3-19 to 1) the D-type FF 3-14 applied to the input. After one block, sampling is performed to determine whether or not there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and ;3-30 determines whether or not there is a prescribed detection pulse signal based on the Hyakuho Shita'/EVEN signal. ODD
In this case, both Q outputs of D-type FF313°3-14 are H.
, EVEN, when the Q output of the D-type FF 3-13 is H, the output of the OR gate 3-25 becomes H even if there is a specified detection pulse signal.

In similar processing, when the initial signal is H, the output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore, when the 4 outputs of the decoder 3-3 are H, that is, 1.2
After 5 blocks, when the specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-
An erroneous detection signal of 11 is outputted from the output of 3-26 via 9.

When the 7 output of the decoder 3-3 is H, that is, after 2 blocks, the presence of the specified detection pulse signal and the OK double signal cause the output of the AND gate 3-10 to be used for sampling other adjacent tracks. sampling signal SP
Outputs 2.

Also, after 4 blocks when the 3rd output of the decoder 3-15 is I (and the 16th output of the decoder 3-3 is H) during playback by the head, the sampling signal 5P3A is
During reproduction by the B head, when output 1 of decoder 3-15 is H and output 16 of decoder 16 is H, 5P3B is output and the on-track level is sampled.

Furthermore, when the 17 output of the decoder 3-3 is 11 and the A-head is ATF-2 and the B-head is ATF-1, the ATFEND A signal is output. Then, head to A
Decoder 3 when using ATF-2 with TF-1 or B head
When the 8 outputs of -3 become H, the ATFEND signal is outputted via gates 3-16, 3-6 and 3-27.

FIG. 12 (al-(1)) is a timing chart showing waveforms of each part accompanying the above operation, and corresponding symbols are assigned to each part.

In the above embodiment, the signal level sampled and held in the S/H circuit 103 by the sampling signal SPI from the sync detection circuit 202 and the sampling signal SP3A or 5P3B from the sync detection circuit 202 is used to control the S/H circuit 105a or 105a or 5P3B. The comparator 107 compares the signal level with 1/2 of the signal level sampled and held in the signal level 105b, and the result is converted into an OK signal and inputted to the ATF timing generator 203, and the AND gate 3-10 controls the output of the sampling signal SP2. I try to do that. That is, the difference between the signal level sampled and held by the sampling signal SP1 and the signal level two blocks after the sample and hold is used as an ATF error signal to control whether or not to sample and hold in the S/H circuit 104. .

As a result, when the level sampled and held by the sampling signal SPI is abnormally large, it is determined that this level is not a proper crosstalk of the pilot signal of one adjacent track, and an ATF error signal is not formed based on the abnormal signal. This prevents tracking disturbances.

Similarly to the above, the circuit configuration for preventing tracking disturbance is not limited to this, and various methods can be considered.

FIG. 13 is a circuit diagram showing a variation thereof, in which the comparator 107 connects the output of the differential amplifier 108 and the S/H circuit 10.
5a or 105b and outputs an OK times signal to the ATF timing generator 203 based on the result. This was done based on the fact that if the signal level sampled and held in the S/H circuit 103 is abnormal, the difference between this signal level and the level two blocks later will also be abnormal, as shown in Figure 2. The same effect as that of the circuit can be obtained.

FIG. 14 is a circuit diagram showing another modification, in which the comparator 107 is connected to one of the outputs of the S/H circuit 105a or 105b.
/2 is compared with the output of the S/H circuit 104, and the result is applied to the zero horn of the latch 110. latch 110
stores the state of the D input when the sampling signal SP2 delayed for a certain period of time is applied to the CK large input in the play circuit 111, and sends it to the 0 output. The 0 output is used as a control signal for the switch circuit 112. The switch circuit 112 includes two switches SW1 and SW that are interlocked with each other.
Z, and the a contacts of switches SWI and SWZ are S/H
It is connected to the output of the circuit 104, the common contact of the switch SWI and the b contact of the switch SW2 are connected to the other end of the capacitor 113 whose one end is grounded, and the ATF error signal is output from the common contact of the switch SW2.

This circuit switches the switches SWI and SWZ of the switch circuit 112 to the a contact side when the level difference sampled and held in the S/H circuit 104 is normal, and the S/H circuit 1
04 is output as an ATF error signal, and the capacitor 113 is charged. When the level difference becomes abnormal, switch SWI and SWZ to the b contact side,
The abnormal level difference is not output as an ATF error signal, and the level previously held in the capacitor 113 is output as an ATF error signal.

The same thing can be done only when the level difference is normal.
It is also possible to provide an S/H circuit that samples and holds the same level difference as the sampled and held level difference in the H circuit 104 instead of the capacitor.

In addition, in the illustrated embodiment, the sampling signals 5P3A, 5P
3B, each on-track pilot (S/H circuit 105a that samples and holds the level of No. 8,
105b, but these two S/H circuits are
Alternatively, the on-track pilot signal may be sampled and held in accordance with the sampling signals 5P3A and 5P3B by the single S/H circuit. In this case, the switch circuit 106 is omitted.

In the illustrated embodiment, 1/2 of the level held in the S/H circuits 105a and 105b is input to one input of the comparator 107 via the switch SW2; is not limited to this, and may be, for example, 1/2 or more, 2/3, or more.

〔effect〕

As explained above, according to the present invention, the detected sink 1
If No. 8 is not a regular sync signal, it is possible to perform an operation to detect a regular sync signal again after that, so even if the recording quality of the recording medium improves, stable tracking control can be performed. You can get the effect of

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing main parts of the present invention,
3 is a circuit diagram showing a specific configuration example of a part of FIG. 2, FIGS. 4 and 5 are timing charts showing signal waveforms of each part in FIG. 2, and FIG. A circuit diagram showing a specific configuration of a part in the figure, FIG. 7 is a timing chart diagram showing signal waveforms of each part in FIG. 6, and FIG. 8 shows a specific configuration of another part in FIG. 2. 9 and 10 are timing charts showing the signal waveforms of each part in FIG. 8. FIG. 11 is a circuit diagram showing the specific configuration of still another part in FIG. The figure is a timing chart diagram showing the signal waveforms of each part in Figure 11, Figures 13 and 14 are circuit diagrams each showing a modification of a part of Figure 2, and Figure 15 is the track format of R-DAT. and block format, Figure 16 is R-DAT.
FIG. 17 is a diagram for explaining the principle of tracking control using the track pattern of FIG. 16. IA, IB... Rotating head, 107... Comparator, 202... Sink detection circuit, 2-3... Decoder, 2-10... AND gate, 2-29... A/toge -, 2-32...ATF enable run, 203...ATF timing generator, 3-10...
・And Gate, 3-18...Table, 3-19・
...Sink detection counter.

Claims (1)

[Scope of Claims] A plurality of signals including a tracking pilot signal and a sync signal consisting of a digital signal and a frequency signal with little azimuth effect are recorded in each of a plurality of diagonal tracks in independent recording areas in the longitudinal direction of each track. A recording in which the pilot signals are recorded in three consecutive tracks in a predetermined format, and the pilot signals are recorded in different positions, and the sync signal is recorded in a position corresponding to one adjacent track. at least two rotary heads for reproducing the plurality of signals on the medium, each rotary head having a width greater than the width of each track, and reproducing each track providing an on-track pilot signal and an on-track pilot signal to the output of each rotary head. Crosstalk between pilot signals of both adjacent tracks is obtained, and a capstan servo is controlled based on a level difference in the crosstalk of pilot signals of both adjacent tracks, so that each rotary head scans over each track, sync detection means for detecting a sync signal based on the sync signal frequency component of the output of each rotary head; and a signal for sampling the level of the pilot signal frequency component of the output of each rotary head in response to the detection of the sync signal by the sync detection means. and a second signal that generates a signal for sampling a crosstalk level difference between pilot signals of both adjacent tracks after a certain period of time after the signal is generated by the first signal generating means. generating means; and a first signal generating means in response to the signal generation by the first signal generating signal means.
an operation control means that is switched from a state to a second state to prohibit further signal generation by the first signal generation means and to enable operation of the second signal generation means; and a sync detected by the sync detection means. determination means for determining whether the signal is a regular sync signal, and when the determination means determines that the signal is not a regular sync signal, the operation control means is switched from the second state to the first state. , A digital signal reproducing device characterized in that the first signal generating means can generate a signal.