JP2566225B2 - Digital signal recording / reproducing device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention converts an audio signal into a PCM signal, records it as a single diagonal track on a recording medium by a rotary head for each unit time, and reproduces it. The present invention relates to a digital signal recording / reproducing device which is suitable for use.

[Technical background of the invention and its problems]

A device for recording and reproducing an audio signal on a magnetic tape by forming a diagonal track for each unit time by a helical scan type rotary head, and converting the audio signal into PCM when reproducing. There is a digital signal recording / reproducing device called R-DAT (rotary head type digital audio tape recorder).

The format of the track actually recorded in the R-DAT has a pattern as shown in FIG. 12 (a), and the frequency of each of MARGIN, PLL, and POSTAMBLE is 1 / 2f _M (f
_M = 9.4MHz), frequency of IBG is a 1 / 6f _M. The SUB and PCM are composed of blocks as shown in FIG. 12 (b). SYNC is fixed to 9 bits, and the rest have various patterns depending on the location, voice signal, and the like. In the case of SUB, this block is repeated eight times, and in the case of PCM, this block is repeated 128 times. The numerical values in FIG. 12 (a) represent the number of blocks occupied by each area.

Areas of ATF1 and ATF2 arranged between SUB-1 and PCM and between PCM and SUB-2 (ATF: Automatic Track Findin
The item g) is for enabling the tracking control that causes the rotary head to scan the recording track during reproduction correctly by the output of the rotary head without providing a special head.

That is, in the ATF area, the PCM signal is time-axis compressed to 2
When forming tracks on a magnetic tape diagonally by a rotating head without a guard band and recording, the recording area is independent of the PCM signal at the beginning and end of each track, and tracking pilot signals are respectively provided. Record,
During reproduction, the rotary head, which has a scanning width wider than the width of the track, scans a recording track, and the rotary head is used to control the tracking of the rotary head by reproducing output of pilot signals from both adjacent tracks of the track being scanned. It

And the track pattern for this ATF is the 13th
It is determined as shown in the figure, and the case where the illustrated pattern is a drum diameter of 30 mm, a drum winding angle of 90 °, and a rotation speed of 2000 rpm will be described.

ATF1 and ATF2 on the front and back of each track
Has a low-frequency signal f ₁ with little azimuth effect as a pilot signal for tracking, which detects the level of crosstalk from both adjacent tracks during playback, and the level of the crosstalk component of both adjacent tracks. It is used to obtain the difference as a tracking error signal. A low frequency signal of f _M / 72 (130 KHz) is used as the pilot signal f ₁ .

Also ATF1 and ATF2 are sync signals to determine the position of the pilot signal f ₁ is recorded is recorded. Since the on-track and the adjacent track cannot be distinguished from each other if there is crosstalk in the sync signal, a frequency having an azimuth effect and a pattern which does not exist in the PCM signal is selected. When the head corresponding to + azimuth is A and the head corresponding to −azimuth is B, the sync signals are different from each other in order to distinguish the A head and the B head, and the frequency is different for the A head. f _M / 18
The sync 1 signal f ₂ of (= 522 KHz) and the sync 2 signal f ₃ of frequency f _M / 12 (= 784 KHz) are recorded at predetermined positions for the B head.

In the R-DAT, an erasing head is not provided, and rewriting of a signal is performed by so-called overwriting in which data is overwritten on the previous recording. Therefore, the erase signal f ₄ having the frequency f _{M /} 6 (= 1.56 MHz) is recorded at a predetermined position for erasing the pilot signal f ₁ , sync 1 signal f _2, and sync 2 signal f ₃ of the previous recording. It

The positions of the ATF pilot signal are different on the on-track and on both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal on both adjacent tracks are temporally different, and three types of levels are sampled respectively. Are arranged so that they can.

Five blocks are assigned to each of the ATF areas of ATF1 and ATF2, and the pilot signal f ₁ is recorded in two of the blocks. The sync signals f ₂ and f ₃ are recorded using one block or 0.5 blocks from the center of the position where one adjacent track is recorded. The pilot signal f ₁ of the other adjacent track is recorded such that the center thereof is located two blocks after the beginning of the sync signal recorded on the on-track. The sync signal of one block is assigned to the odd frame and the sync signal of 0.5 block is assigned to the even frame.

As described above, in the ATF, the sync signal frequency differs depending on the A head and the B head, and the sync signal recording length differs between the odd frame and the even frame. Therefore, different ATFs are given to all four consecutive tracks, so that they can be distinguished. The ATF pattern as described above is a 4-track completion type, which is repeated every 4 tracks.

By the way, in order to perform recording in the format as shown in FIG. 12 (a) on a magnetic tape with two rotary heads, servo control of a drum motor for rotating a drum provided with the two rotary heads and rotary heads The recording start position may be specified by measuring the time based on a signal from a pulse generator (PG) provided on the drum for generating a signal for use in switching the recording. This is because the positional relationship between the rotary head and the PG in the recording device is predetermined during recording.

On the other hand, when the magnetic head recorded in the format shown in FIG. 12 (a) is reproduced by the rotary head, an RF signal as shown in FIG. 14 (a) is obtained from the rotary head.
When this RF signal is obtained, for example, by reproducing the odd frame track (A) in FIG. 13, a pilot signal f ₁ as shown in (b) is obtained by passing it through a bandpass filter (BPF) of 130 KHz. Is obtained.

Section I is due to the on-track pilot signal,
The sections II and III are due to the crosstalk of the pilot signals of (B) odd frame tracks and (B) even frame tracks. When the rotary head is scanning on the track correctly, the intervals II and III are originally
Envelope level, ie, (c) VII and VIII
Should be equal, but if there is a track deviation, VII ≠ VII
It becomes I, and the amount and direction of the displacement of the rotary head with respect to the on-track can be known from its size and polarity. Therefore, VII and VII
The difference in I activates the capstan servo to fine-tune the tape speed, which allows the rotary head to run on track.

In order to perform the above operation, it is necessary to detect a sync signal at a predetermined position and accurately sample the VII and VIII levels. However, the PCM signals in the SUB and PCM areas before and after the ATF area are pilot signals.
It has the same frequency components as f ₁ and sync signals f ₂ and f ₃ . Therefore, the signal processing unit that should operate in the ATF area is SU
It is necessary to set the window correctly so that it does not work in the B and PCM areas. The same applies to SUB and P
It can be said about the commercial area.

Therefore, it is considered to set the window based on the signal from the pulse generator (PG).

However, with this method, compatibility between devices having different positional relationships between the rotary head and the PG is lost. Even in the same model or the same device, the position of the window with respect to each rotary head will not be constant due to variations in manufacturing, aging, etc. Therefore, it is necessary to set the window wide in view of tolerance. In this way, malfunctions are likely to occur. Of course, it is possible to set a narrow window to some extent by adjusting the window creation for each drum and head, but the adjustment work is troublesome and costly, and there is still a problem in terms of compatibility with other devices. Remain.

In order to solve such a problem, it is sufficient to control the processing time point of each signal with reference to the reproduction signal which is always in a fixed format. For this purpose, the output signal of the rotary head after the rotary head switching is performed. Therefore, it is necessary to detect the head portion of the reproduction signal.

However, since the output signal of the rotary head contains noise when the rotary head is switched, there is a risk that a so-called erroneous operation of detecting this as the head portion of the reproduction signal may occur.

〔Purpose〕

In view of the above-mentioned problems, the present invention provides a digital signal recording / reproducing apparatus capable of detecting a reproduction signal without malfunction and using a timing means for determining a recording start point at the time of recording with a simple configuration. It is intended to be provided.

[Outline of Invention]

A digital signal recording / reproducing apparatus according to the present invention made to achieve the above object comprises a plurality of diagonal tracks formed on a recording medium, and a plurality of tracks each including a digital signal in which an audio signal is converted into a PCM signal and time-axis compressed. At least two recording / reproducing rotary heads for reproducing the plurality of signals on the recording medium by recording the signals in a predetermined format in the recording area independently in the longitudinal direction of each track, and the two recording / reproducing rotary heads. At least one pulse generating means which is provided in a predetermined positional relationship with respect to the recording / reproducing rotary head and rotates together with the rotary head to generate a pulse for each rotation, and the pulse from the pulse generating means is provided. Accordingly, the two rotary heads are alternately switched, and a plurality of signals are recorded on each track by each rotary head during recording,
In a case where a plurality of signals are reproduced from each track by each rotary head during reproduction, during recording, clocking is started in response to a pulse from the pulse generating means, and a time-coded encoded data processing unit for a predetermined first time is recorded. Timing means for generating a recording start signal for designating a signal processing point in time, and the timing of the timing means is started in response to the pulse from the pulse generating means at the time of reproduction to measure a predetermined second time. And a control unit for generating a reproduction start signal for designating a signal processing time point in the decoded data processing unit.

This makes it possible to obtain a reproduction signal that does not include noise when the rotary head is switched, with a simple configuration.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of an apparatus according to the present invention configured as a digital signal recording / reproducing apparatus.

In the figure, reference numeral 1 denotes a rotary drum having a diameter of 30φ, and the rotary drum 1 has an A head 1A for recording / reproducing + azimuth and a −
Two rotating heads with B head 1B which records and reproduces azimuth
Two pulse generators (PG) PGAs are placed 180 degrees apart and are located in the middle of A head 1A and B head 1B.
And PGB are arranged.

Reference numeral 2 is a crystal oscillator that generates a basic clock f _{M of} 9.4 MHz, and the basic clock f _M is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) for controlling the system, which outputs a PB / ▲ ▼ switching signal to control switching of the toggle switch 4 including switches SW1 and SW2.

Reference numeral 5 is a reference signal generator, which generates reference signals of XHz (66Hz: 2PG), YHz (depending on the number of capstan motor FGs) and ZHz based on the basic clock f _M applied to the CK input. .

A drum servo 6 servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on the reference signal ZHz under the control of the system controller 3. Reference numeral 8 denotes a capstan servo which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when the switch 4 is switched to the b contact side by the system controller 3 and the switch 4 is switched to the a contact side. During reproduction, the rotation of the capstan motor is servo-controlled based on the track shift amount.

9 is an HSWP (A /) signal generator, which is 2 on the drum 1.
A head 1A and B head based on pulses from one PG
Generate HSWP (A /) signal to switch between 1B and HSWP
The (A /) signal becomes H for the A head and L for the B head, which is also supplied to each part of the system.

Reference numeral 10 is a phase inversion detection circuit, to which the basic clock f _M and HSWP (A /) signal applied to the CK input are input, and the output is supplied to the S input of the initial flag latch 11. The CY output of the initial counter 12 is input to the R input of the initial flag latch 11, and the Q output is supplied to the R input of the initial counter 12.

The initial counter 12 is set with a threshold value from the table 13 under the control of the PB / ▲ signal from the system controller 3, and the CY output becomes H by counting the set value. The
CY output is applied via inverter 13a PB / ▲
▼ Input to the encode data processing unit 18 via the AND gate 13b which is opened / closed by a signal, and PB / ▲
The signal is supplied to the S input of the head touch window flag latch 14 via an AND gate 13c which is opened / closed by a signal.

The head touch window flag latch 14 is for generating a window for inhibiting the head touch detection operation during noise during head switching. The Q output is input as an ON signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from the section 17.

Reference numeral 15 is a reproduction amplifier, which amplifies the signals from the rotary heads 1A and 1B and supplies the signals to a decode data processing unit 17 described later. Reference numeral 16 denotes a recording amplifier, which receives recording data from an encode data processing unit 18 described later based on the HSWP (A /) signal and supplies the recording data to the rotary heads 1A and 1B via a switch SW1.

The decoded data processing unit 17 extracts data from the RF signal from the reproduction amplifier 15, performs 10/8 conversion (demodulation), deinterleaving, error correction, etc., and sends the data to the D / A conversion unit, and also detects head touch. , ATF sync detection, tracking error detection, etc., and track deviation signal generator 17a
Supplies an error signal to the capstan servo 8.

The encoded data processing unit 18 interleaves, adds parity, 8/10 conversion, ATF for A / D converted data.
The signal is added and then supplied to the recording amplifier 16.

In the above configuration, the system controller 3
When the PB / ▲ ▼ signal is L, the recording operation is performed.

Because the PB / ▲ ▼ signal is L, the switch 4
Is switched to the b contact side, the reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied to the reference of the reference signal YHz, and tracking is controlled.

HSWP (A /) output from HSWP (A /) generator 9 based on the pulse generated by PGA and PGB by rotation of drum 1.
The signal is H when the A head is 1A and is L when the B head is 1B. This HSWP (A /) signal is input to the phase inversion detection circuit 10,
When the level of the HSWP (A /) signal changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H only for one basic clock period.

In response to the rise of the output of the phase inversion detection circuit 10 from L to H, the initial flag latch 11 is set and its Q output becomes H. As a result, the initial counter 12 starts the counting operation. In this example, the initial counter 12 uses the set value from Table 13 for 3.75ms
When the number of basic clocks f _M corresponding to a fixed time corresponding to is counted, its CY output rises, which resets the initial flag latch 11 and
The rising edge of the CY output is applied to the encode data processing unit 18 as a recording start signal. Based on this recording start signal, the encoded data processing unit 18 outputs recording data in a predetermined format.

Next, when the PB / ▲ ▼ signal from the system controller 3 is H, the switch 4 is set to the a side and the rotary head
1A and 1B are connected to the reproduction amplifier 15, and the RF signal is supplied to the decoded data processing unit 17.

The capstan servo 8 operates based on the track shift amount supplied from the decode data processing unit 17. The track shift amount is an ATF error signal according to the level difference of the crosstalk amplitude of the pilot signals of both adjacent tracks,
Details will be described later.

The HSWP (A /) generator 9 and the phase inversion detection circuit 10 operate in the same manner as during recording, but the initial counter 12 becomes a counter in the reproduction mode according to the set value from the table 13, and the count value corresponds to, for example, 100 μs to 1 ms. CY output becomes H when the value reaches. This prohibits the head touch operation described later while noise is generated when the heads are switched, and after a certain period of time, the head touch window flag latch 14 is set via the AND gate 13 to set its Q output. This is because it is set to H and an ON signal for head touch detection is output. The ON signal from the head touch window flag latch 14 is head touched in the decode data processing unit 17, that is, the tape T and the head 1A or
When it is detected that 1B touches and outputs an RF signal, the head touch window flag latch 14 is cleared,
The ON signal becomes L.

Hereinafter, details of a portion particularly related to tracking control in the decoded data processing unit 17 will be described with reference to the block diagram of FIG.

In the figure, an upper part is an analog system and a lower part is a digital system from the one-dot chain line. The analog system includes a reproduction amplifier 15, a bandpass filter (BPF) 101, an envelope detector 102, a first sample hold (S / H) circuit 103, a second S / H circuit 104, and a third S / H.
H circuits 105a and 105b, toggle switch 106, comparator
107, differential amplifier 108, level correction circuit 109, and resistor R
_It consists of _{1 to} R ₄ .

On the other hand, the digital system includes the crystal oscillator 2, the head touch detection circuit 201, the sync detection circuit 202, and the ATF timing generator 20.
3, reproduction flag latch 204, system counter 205, timing generator 206, 1/2 divider 207, ATF initial flag latch 208, power-on reset circuit 209, latch circuit 210, protection counter 211, noise flag latch 212, latch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, in the analog system, the RF signal from the rotary heads 1A and 1B (FIG. 1) is input to the input of the reproduction amplifier 15, and the output is input to each input of the BPF 101, the head touch detection circuit 215, and the sync detection circuit 216. Is being supplied.

The BPF 101 passes only the 130 KHz component in the RF signal and inputs it to the envelope detector 102. Envelope detector 1
02 envelope-detects the 130 KHz component, and this is the S / H circuit 1
It is applied to each input of 03, 105a, 105b and the + input of the differential amplifier 108.

The S / H circuit 103 uses the sampling signal SP1 applied from the sync detection circuit 202 to the C input to detect the envelope detector 1
The output of 02 is sample-held and this is
7 and the negative input of the differential amplifier 108. What is sampled and held by the S / H circuit 103 is the DC level of the crosstalk of the pilot signals of one adjacent track.

The S / H circuit 104 is applied with a signal whose level is adjusted by the level adjusting circuit 109, samples and holds this by the sampling signal SP2 from the ATF timing generator 203, and ATF is applied to the capstan servo 8 (FIG. 1). It is supplied as an error signal. The error signal is the DC level difference of the crosstalk on both adjacent tracks.

The S / H circuit 105a outputs the output from the envelope detector 102 to the AT.
The sampling signal SP3A from the F timing generator 203 is used to sample and hold, and this is output to one end of the resistor R ₁ and the a contact of the switch SW1 of the toggle switch 106. S / H circuit 1
What is sample-held by 05a is the DC level of the on-track pilot signal during A track playback.

The S / H circuit 105b outputs the output from the envelope detector 102 to the AT.
Sampled and held by a sampling signal SP3B from F timing generator 203, and outputs it to the contact b of the switch SW1 of the one end and the toggle switch 106 of the resistor R _3. S / H circuit 1
What is sample-held by 05b is the DC level of the on-track pilot signal during B track reproduction.

The resistors R _{1 to} R ₄ have the same value, and are for dividing the outputs of the S / H circuits 105 a and 105 b applied to _one ends of the resistors R ₁ and R ₃ , respectively. The interconnection point of resistors R ₁ and R _{2 and} the interconnection point of resistors R ₃ and R ₄ are toggle switches 106.
The switch SW2 is connected to the a-contact and the b-contact, respectively, and at each interconnection point, a half level of the sample hold value of each S / H circuit can be obtained.

The toggle switch 106 is controlled by the HSWP (A /) signal and is switched to the a side when the HSWP (A /) signal is H and to the b side when the HSWP (A /) signal is L.

Comparator 107 has S / H circuits 105a and 105b at one input.
1/2 level of the output of the S / H circuit 103 is applied to the other input through the resistors R _{1 to} R ₄ and the switch SW 2. The output of the comparator 107 becomes H when 1/2 of the sample hold value of the S / H circuits 105a and 105b is larger than the output level of the S / H circuit 103, and this is supplied to the input of the ATF timing generator 203 as an OK signal. To do.

The differential amplifier 108 is an S / H circuit applied to the output of the envelope detector 102 applied to the + input and to the − input.
The difference from the output of 103 is calculated and input to the level adjustment circuit 109. That is, when the output of the envelope detector 102 outputs the DC level of the crosstalk of the other adjacent track, the difference between the crosstalks of the adjacent tracks, that is, the track shift amount is output.

The level adjusting circuit 109 changes the amplification degree, for example, in inverse proportion to the output levels of the S / H circuits 105a and 105b.
Rotating head 1 by adjusting the signal level from 8
Correct the output variation of A and 1B.

Next, the digital system will be described. The head touch detection circuit 201 includes a head touch window flag latch 14
The ON signal from (Fig. 1) and the basic clock f _M
Detects that an RF signal has been input, and reproduces the flag latch
A signal is supplied to the S input of 204, which will be described in detail later.

The sync detection circuit 202 uses RF signal, HSWP (A /) signal,
The ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise flag latch 212, the basic clock f _M from the crystal oscillator 2, and the enable clear signal from the OR gate 216 are input. , And sends the sampling signal SP1, the enable signal and the detection pulse signal to its output. The sampling signal SP1 is input to the C input of the S / H circuit 103 and the R input of the latch 210, and the enable signal and the detection pulse signal are input to the ATF timing generation circuit 203, respectively. The sync detection circuit 202, after converting the RF signal to a digital signal, detects the beginning of the ATF sync patterns SY1 and SY2 of the rotary heads 1A and 1B, outputs the sampling signal SP1, and then outputs the sync signals to the continuously detected syncs. It operates so as to output a detection pulse signal, which will be described in detail later.

The ATF timing circuit 203 outputs the OK signal which is the output of the comparator 107 and the Q output of the 1/2 frequency divider 207 which is ▲ ▼ / E.
VEN signal, initial signal which is Q output of ATF initial flag latch 208, enable signal and detection pulse signal from sync detection circuit 202, timing generator
From 206 The enable clear signal from the OR gate 216 and the basic clock f _M from the crystal oscillator 2 are input, and the sampling signals SP2, SP3A, SP3B, erroneous detection signals, and ATF are output to the outputs.
Send the END signal. Sampling signal SP2 is S / H circuit 104
To the C input of the ATF initial flag latch 208, the sampling signal SP3A to the C input of the S / H circuit 105a, the sampling signal SP3B to the C input of the S / H circuit 105b, and the false detection signal to the S input of the latch 210. The ATFEND signal is input to one input of the OR gates 216 and the CK input of the false detection counter 214, and the ATFEND signal is input to one input of the OR gates 216 and 217, respectively.

The ATF timing generator 203 receives an enable signal from the sync detection circuit 202, enables a timer counter (not shown) for timing generation when the signal is H, and outputs a detection pulse signal from the sync detection circuit 202. After receiving and counting it, if the detection pulse exceeds the specified value by the specified time, sampling signals SP2, SP3A, SP3B
Is output, and when the OK signal that is less than the specified value or the output of the comparator 107 is at the L level, it operates so as to output an erroneous detection signal, which will be described in detail.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of R-DAT channel bit data, and outputs the basic clock f _M. The basic clock f _M is the head touch detection circuit 20.
1, applied to the CK inputs of the sync detection circuit 202, the ATF timing generator 203, the system counter 205, and the protection counter 211.

The latches 204, 208, 210 and 213 are formed of RS flip-flops whose Q output is H in response to the rising edge of the S input and whose Q output is L in response to the rising edge of the R input.

The reproduction flag latch 204 has an S input for the output of the head touch detection circuit 201 and an R input for the timing generator 206.
The END signal which is the output of each of the above is input, and its Q output is input to the R input of the system counter 205. When the Q output of the reproduction flag latch 204 is H, the reproduction operation is in progress.

The system counter 205 has a playback flag latch 2 on the R input.
The Q output of 04 is input to the CK input of the basic clock f _M , and its outputs Q _{0 to} Q _X are input to the timing generator 206. The system counter 205 is for roughly indicating the position where each signal is recorded on the track.

The timing generator 206 is based on the Q ₁ -Q _X outputs from the system counter and outputs STF window set signals at its outputs, Generates a window clear signal and an END signal, sends an ATF window set signal to the sync detection circuit 202, To ATF timing generator 203, window clear signal to OR gate 217, and END signal playback flag latch
Supply to the R input of 204 respectively. The timing generator 206 decodes the output of the system counter 205 and generates the timing required for each unit.

The 1/2 frequency divider 207 divides the HSWP (A /) signal applied to the CK input by 1/2 to generate a ▲ ▼ / EVEN signal at the Q output,
This is supplied to the ATF timing generator 203. The Q output of the ATF initial flag latch 208 is input to the R input of the 1/2 frequency divider.

In the ATF initial flag latch 208, the sampling signal SP2 from the ATF timing generator 203 is input to the S input, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is the R input of the 1/2 frequency divider 207. Is input to the ATF timing generator 203. The ATF initial flag latch 208 generates a flag indicating that the capstan servo by the ATF is being applied.

The power-on reset circuit 209 outputs H when the power is turned on.
Becomes

The latch 210 has its S input inputted with the erroneous detection signal from the ATF timing generator 203, its R input inputted with the sampling signal SP1 from the sync detection circuit 202, and its Q output inputted with the R input of the protection counter 211. When the latch 210 is erroneously detected, the Q output becomes H and is reset according to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain time from an erroneous detection, and counts the basic clock f _M applied to the CK input only when the R input is H, and is cleared by L of the R input. The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise flag latch 212 is for temporarily storing whether noise is being reproduced or not, and is composed of a D-type flip-flop. The latch 212 has a D input for the Q output of the latch 213 and a CK input for the sampling counter 2
The 15 CY outputs are respectively input, and the Q output is supplied to the sync detection circuit 02 as a noise signal.

The latch 213 receives the CY output of the false detection counter 214 at the S input,
The CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise flag latch 212.

The false detection counter 214 uses the ATF timing generator 20 for the CK input.
False detection signal from 3 is input to sampling counter 2
The 15 CY outputs are respectively input, and the CY output is supplied to the S input of the latch 213. The erroneous detection counter 214 counts the number of times the sampling signal SP1 is erroneously detected in a certain period, and when it exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives the HSWP (A /) signal at the CK input, the CY output at the R input of the false detection counter 214,
The R input of the latch 213 and the noise flag latch 212
It is supplied to each CK input.

The OR gate 216 receives the erroneous detection signal and the ATFEND signal from the ATF timing generator 203 and the CY output of the protection counter 211, and sends an enable clear signal to the sync detection circuit 202 and the ATF timing generator 203 at its output.

The OR gate 217 is a window clear signal from the timing generator 206 and an AT from the ATF timing generator 203.
The FEND signal and the CY output from the protection counter 211 are respectively input, and the ATF window off signal to the sync detection circuit 202 is sent to the output.

In the above configuration, the RF signal is supplied to the head touch detection circuit 201 and the sync detection circuit 202 via the reproduction amplifier 15 and the BPF 101. RF supplied to BPF101
Only the 130 KHz component of the signal is passed. The amplitude level of the 130 KHz component is converted to a DC level by the envelope detector 102, and then applied to the respective inputs of the S / H circuits 103, 105a and 105b and the + input of the differential amplifier 108.

The envelope detector 102 sequentially outputs the crosstalk of the pilot signal of one adjacent track and the DC level of the amplitude of the crosstalk of the pilot signal of the other adjacent track in order in time series. The DC level of the on-track pilot signal amplitude is output before or after the signal.

The S / H circuit 103 outputs the pilot signal of one adjacent track.
DC level is the sampling signal S from the sync detection circuit 202
Sample and hold at the timing of P1. The crosstalk level of the one adjacent track sampled and held is applied to the minus inputs of the comparator 107 and the differential amplifier 108.

The S / H circuit 105a displays the DC level of the on-track pilot signal during playback of the + A azimuth A track,
-Samples and holds the DC level of the on-track pilot signal during reproduction of the azimuth B track. The output of the S / H circuit 105a, that is, the DC level of the on-track pilot signal is supplied to the control input of the level adjustment circuit 109 via the a contact of the switch SW1 of the toggle switch 106, and the resistors R ₁ and R ₂ are also supplied. The voltage is divided by 1/2 by the comparator 107 via the contact a of switch SW2.
Is supplied to one of the inputs. Similarly, the output of the S / H circuit 105b is supplied to the level adjusting circuit 109 via the b contact of the switch SW1.
Further, after being divided into ½ by the resistors R ₃ and R ₄ , the voltage is supplied to one input of the comparator 107 via the b contact of the switch SW2.

The OK signal of the comparator 107 becomes H when the level input via the switch SW2 is higher than the input from the S / H circuit 103. That is, it is determined that the crosstalk level of one adjacent track is correctly sampled. In the opposite case, it is determined that the on-track level is sampled. Therefore, when the OK signal is L, it is determined that the sync is erroneously detected. This OK signal is supplied to the ATF timing generator 203.

In the differential amplifier 108, when the envelope detector 102 outputs the DC level of the crosstalk amplitude of the other adjacent track, the DC level of the crosstalk amplitude of the one adjacent track is input to the-input. Therefore, a difference in DC level of crosstalk between adjacent tracks, that is, a track shift amount is obtained at the output, and this is input to the level adjustment circuit 109.

The output of the S / H circuits 105a and 105b is applied as a control input to the level adjusting circuit 109. When the control input is large, the level of the input signal is lowered, and when the control input is small, the level is raised and output. In short, the level adjusting circuit 109 automatically corrects the variation in the outputs of the two rotary heads and inputs the corrected output to the next S / H circuit 104. The S / H circuit 104 samples and holds the deviation amount of both adjacent tracks after correction by the sampling signal SP2. The output of the S / H circuit 104 is supplied to the capstan servo 8.

FIGS. 3 (a) to 3 (i) are timing charts showing the signal waveforms generated in the respective parts by the above operation, corresponding to the reference numerals assigned to the respective parts.

The HSWP (A /) signal shown in FIG. 3 (b) becomes H when reproducing by the A head 1A of + azimuth, and becomes L when reproducing by the B head 1B. When the head is switched, the phase of the HSWP (A /) signal is inverted. When the phase is inverted, the Q output of the initial flag latch 11 (Fig. 1) becomes H, and the initial counter 12 (Fig. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is judged that the tape has passed the noisy portion, and the head touch window flag latch 14 (Fig. 1) is set to set the Q value.
Set the output to H. When the Q output of the head touch window flag latch 14 becomes H, the head touch detection circuit 201
Works.

When the head touch detection circuit 201 detects that the tape and the head are in contact with each other and the RF signal is reproduced, the output becomes H, and the reproduction flag latch 204 is set to set the Q output to H. When the Q output of the reproduction flag latch 204 becomes H, the system counter 205 starts counting operation. Based on this time point, the system counter 205 can make a rough judgment about the recorded position of each signal on the tape. Timing generator 206
Is ATF-1, based on the Q _{0 to} Q _X outputs of the system counter 205.
The ATF window set signal is supplied to the singing detection circuit 202 shortly before ATF-2 is recorded.

The sync detection circuit 202 converts the RF signal into a digital signal, and then sync 1 (= f ₂ ) for reproduction by the A head 1A
Then, the sync 2 (= f ₃ ) pattern in the case of the B head 1B is detected for each sync based on the fact that the relationship between the frames is as shown in the table below.

When the sync detection circuit 202 detects four syncs in the case of normal or five syncs in the case of noisy, the sampling signal SP1 is output and the S / H circuit 103 outputs the crossing of the pilot signal f1 of _one adjacent track. The talk level is sampled and held, and the enable signal is supplied to the ATF timing generator 203. Then, the detection pulse signal is supplied to the ATF timing generator 203 each time a continuous sync is detected.

The ATF timing generator 203 operates a sync detection counter and a timer according to H of the enable signal from the sync detection circuit 202. The ATF timing generator outputs 0 after the sampling signal SP1 is output from the sync detection circuit 202.
After 25 blocks, it is checked by the sampling signal SP1 whether the crosstalk of the adjacent track is sampled and held correctly. Next, after 1.25 blocks, it is judged whether or not the sync is detected more than the specified value. If it is more than the specified value, it is determined that the sync is correctly detected, and two blocks later, the sampling signal SP2 is supplied to the S / H circuit 104, and both adjacent tracks are detected. The crosstalk level difference is sampled and held, and its output is supplied to the capstan servo 8 as a track shift amount.

Further, when the on-track pilot signal f ₁ exists after the sync, the ATF signal is reproduced when the A head 1A reproduces.
-2, because it is ATF-1 at the time of B head reproduction,
In this case, the sampling signal after 4 blocks each
SP3A and SP3B are output, and this is S / H circuit 105a and S / H105b
To sample and hold the level of the on-track pilot signal being reproduced by each head.

When the series of operations described above are correctly performed, the ATFEND signal is output, and this is supplied to the sync detection circuit 202 and the ATF timing generator 203 as an enable clear signal via the OR gate 216. ATFEND signal is also OR gate 2
Sync detection circuit 20 as a window-off signal via 17
2, the window for sync detection by the sync detection circuit 202 disappears accordingly, and the operation of detecting the pattern of the sync signal is stopped.

In the case of mis-sampling, that is, when the output of the comparator 107 is L and it is determined that the S / H circuit 103 has sampled and held the level of the on-track pilot signal, and when the sync is less than the specified value, the false detection signal is set to H. Then, the Q output of the latch 210 is set to H and the count operation of the protection counter 211 is performed, and the false detection counter 214 is set to +
1 motion is performed. When the erroneous detection signal becomes H, the enable clear signal to the sync detection circuit 202 and the ATF timing generator 203 also becomes H via the OR gate 216. When the enable clear signal becomes H, the sync detection circuit 202 performs the operation of detecting the sync again from the beginning, and outputs the sampling signal SP1 again when the sync is detected. Meanwhile, the ATF timing generator 203 sets the sync detection counter and the timer to the initial state. As described above, when the sync detection circuit 202 outputs the sampling signal SP1 again, the latch 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the false detection signal is output once, C of the protection counter 211
After the Y output becomes H, that is, after a specified time (2.5 blocks), the sync detection circuit 202 is passed through the OR gate 216.
Also, the enable clear signal to the ATF timing generator 203 becomes H, and the operation is stopped.

Further, the sampling counter 215 becomes +1 at the rising edge of the HSWP (A /) signal, which means that the tape is managed for a certain length, and if the erroneous detection exceeds a certain level during that period, the erroneous detection counter 214 The CY output becomes H, whereby the Q output of the noise flag latch 213 is set to H and the sync detection circuit 202 is informed that the tape is noisy.

Also, the window clear signal from the timing generator 206 causes the ATF window off signal to the sync detection circuit 202 via the OR gate 217 to become H, which is for a large measure against dropout.

4 (a) to (c) and (A) to (H) are timing charts showing the outline of the signal waveform of each part of the digital system after the initial flag latch 11 is set at the time of reproduction, Corresponding numerals are given in FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific configuration example of the above-mentioned head touch detection circuit 201.

In the figure, the comparator 1-1 has an RF signal input to one input and a reference voltage + V input to the other input. The RF signal is input to one input of the comparator 1-2, and the reference voltage -V is input to the other input. The outputs of the comparators 1-1 and 1-2 are OR gates 1-
3, D-type flip-flop (FF) 1 via resistor 1-4
It is connected to the D input of -5, and is also a capacitor
Is connected to ground via.

In the D type FF1-5, the basic clock f _M is input to the CK input,
The Q output is connected to the input of the AND gate 1-7, and the output is connected to the input of the AND gate 1-8.

The basic clock f _M is input to the inputs of the AND gates 1-7 and 1-8, and the respective outputs are connected to the UP input and the DOWN input of the up / down counter 1-9, respectively. The Q _A -Q _D output of the up / down counter 1-9 is input to the AND gate 1-8 via the OR gate 1-10, and CY
The outputs are connected to the CK inputs of D-type FF1-11 respectively. The D input of the D type FF1-11 is connected to V _CC , and the Q output is the output of the touch detection circuit 201.

The Q output of the head touch window flag latch 14 (FIG. 1) is applied to the R inputs of the up / down counter 1-9 and the D type FF 1-11.

In the above configuration, the output of the comparator 1-1 becomes H when the level of the RF signal is higher than + V, and becomes L when the level of the RF signal is low. The output of the comparator 1-2 becomes H when the level of the RF signal is higher than -V to one side, and becomes L when the level is low. That is,
When the RF signal is not within the range of ± V, the output of the OR gate 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 form an integrator circuit, and the integrator circuit absorbs noise and the like in the output of the OR gate 1-3. The output of the OR gate 1-3 from which spike noise has been removed by the integrating circuit is a D-type FF1.
Applied to the D input of -5.

D-type FF1-5 is the basic clock f applied to the CK input
The state of the D input is sampled by _M and the state is output to the Q output. The output is an inverted output of the Q output. When the Q output of the D type FF1-5 is applied to the other input of the AND gate 1-7 in which the basic clock f _M is applied to one input, and the Q output of the D type FF1-5 is H, Up-down counter 1-9 via AND gate 1-7
The basic clock f _M is input to the UP input of. Therefore, when the Q output of the head touch window flag latch 14 is H and the window is standing and the Q output of the D-type FF1-5 is H, the up / down counter 1-9 outputs the basic clock f _M.
Upcount.

When the Q output of D type FF1-5 is L, that is, when the level of the RF signal is within ± V and it is judged that there is no signal,
The output becomes H, and in such a state, when any of Q _{A to} Q _D of the up / down counter 1-9 is H, that is, when the counter is not 0, the basic clock f _M goes down through the AND gate 1-8. When applied to the input, the up / down counter 1-9 performs a down count operation. When the counter contents are 0 and all the outputs of Q _{A to} Q _D are L by this down count or reset, the output of the OR gate 1-10 becomes L and the AND gate 1-8 becomes The basic clock f _M is not supplied to the DOWN input because it is closed.

When a carry occurs due to the up-counting of the up-down counter 1-9 and the CY output becomes H, the D-type FF 1-11 stores the state of the D input by this rising. Since the D input is H, the Q output becomes H.

FIGS. 6 (a) to 6 (j) are timing charts showing waveforms of respective parts of the head touch detection circuit shown in FIG. 5 when the RF signal shown in FIG. 6 (a) is input.

The RF signal continuously has an amplitude larger than ± V in the signaled state, and almost no amplitude larger than ± V in the signalless state, that is, when the head is not in contact with the tape. In addition, ± V is set to a value that can clearly distinguish the signal and the noise.

In response to the RF signal input as shown in (a), the output of the comparator 1-1 has a waveform as shown in (b), and the output of the comparator 1-2 has a waveform as shown in (c). Appears. And in the output of OR gate 1-3,
A waveform as shown in (d) which is the logical sum of the waveforms of (b) and (c) appears. As is clear from the waveform of (d), there are gate leaks in the outputs of the gates 1-3. This gate leakage is removed by the integration circuit, and D-type FF1
A signal having a waveform as shown in (e) is input to the -5 input.

As a result, a waveform as shown in (f) appears in the Q output of the D-type FF1-5, and the AND gate 1-
When the basic clock f _M passes through 7, a signal as shown in (g) appears at the outputs of the AND gates 1-7. On the other hand, a signal as shown in (h) appears at the output of the AND gate 1-8.

It should be noted that noise components slightly exceeding ± V and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears in a single shot, it cannot be removed by the integrating circuit.

Signals (g) and (h) are up / down counters 1-9
Applied to the UP input and the DOWN input, respectively. When the up / down counter 1-9 counts a predetermined number (i)
The carry as shown in FIG. 3 is sent to the CY output, and in response to this, the D type FF1-11 stores the D input, and the Q output rises as shown in (j).

As described above, the small noise and the gate leakage are integrated by the integrating circuit, and the large noise is up-down counter 1-
It is removed by the management of the time width by 9, and it is surely judged whether the signal is actually reproduced by the contact between the tape and the head or the signal is not reproduced by the non-contact. That is, the head touch is detected.

FIG. 7 shows a specific configuration example of the sync detection circuit 202.

An RF signal, HSWP (A /) signal, basic clock f _M , ATF window set signal, ATF window clear signal, noise signal and enable clear signal are input to the sync detection circuit 202.

ATF supplied with RF signal from playback amplifier 15 (Fig. 1)
Equalizer 2-1 is ATF sync signal band 400KHz ~ 900KH
It emphasizes z and outputs it to the limiter 2-2. Limiter 2-
2 is set to H when the amplitude of the signal is larger than the specified level, and is set to L when the amplitude is smaller than the specified level to convert the RF signal into a digital signal.

The output of the limiter 2-2 is supplied to the D input of the D-type FF2-3 in which the basic clock f _M is input to the CK input and also to one input of the exclusive (E) OR gate 2-4. There is. The Q output of the D type FF2-3 is supplied to the other input of the E or gate 2-4, and the EOR gate 2-4 and the D type FF2-3 constitute a phase inversion detection circuit.

As for the ATF window set signal, the ATF window clear signal is input to the R input.
The ATF window signal is supplied from the Q output of the ATF window latch 2-5.

The output of the EOR gate 2-4 is the basic clock f _{M at} the CK input and the ATF from the ATF window latch 2-5 at the R input.
The window signal is supplied to the D input of the 11-stage shift register 2-6 to which each is input. 11-stage shift register 2
The Q ₁ output of −6 is sent to the AND gates 2-8 and 2-9 via the inverter 2-7, and the Q _{2 to} Q ₅ outputs are sent to the AND gates 2-8 and 2-9, and the Q _{6 to} Q ₈ outputs. Output is NOR gate 2
The outputs of Q _{9 to} Q ₁₁ are supplied to the NOR gates -10 and 2-9, respectively.
Are supplied to AND gates 2-8 and 2-9, respectively. The input of AND gates 2-8 and 2-9 is HSWP (A /) before and after being inverted by the inverter 2-12.
Signals are supplied respectively. The outputs of the AND gates 2-8 and 2-9 are supplied to the input of the OR gate 2-13.

The output of the OR gate 2-13 is supplied to the D input of the 29-stage shift register 2-14 whose basic clock f _M is input to the CK input. The Q ₁ output of the 29-stage shift register 2-14 is input to the AND gates 2-15 to 2-20, and the Q _{6 to} Q ₈ outputs which become high when the sink 2 is input to the input of the OR gate 2-21. Q _{9 to} Q ₁₁ output which becomes H when it is at the input of the OR gate 2-22, and Q _{12 to} Q ₁₄ output which becomes H when it is at sink 2 are at the input of the OR gate 2-23 and H at both sync 1 and sync 2 Q _{18 to} Q ₂₀ outputs are to the input of the OR gate 2-24, and Q _{27 to} Q ₂₉ outputs that are H at the time of sink 1 are OR gates 2 to 25.
Is supplied to each input.

The output of the OR gate 2-21 is AND gates 2-16 and 2
The input of -18 and the input of OR gate 2-26, the output of OR gate 2-22 is the input of AND gates 2-15 and 2-17 and the input of OR gate 2-27, and the output of OR gate 2-23 is the AND gate 2. The inputs of -16 and 2-18 and the input of OR gate 2-26, the output of OR gate 2-24 to the inputs of AND gates 2-15 to 2-18 and the input of OR gate 2-27, and the input of OR gate 2-25. The outputs are respectively supplied to the inputs of the AND gate 2-15. The outputs of OR gates 2-26 and 2-27 are AND gates 2-20 and 2-27.
Supplied to each of the 19 inputs.

HSWP is provided for the AND gates 2-15, 2-17 and 2-19.
(A /) signal is AND gates 2-16, 2-18 and 2-20
The HSWP (A /) signal inverted by the inverter 2-12 is supplied to each. The AND gates 2-15 and 2-16 are supplied with the noise signal, and the AND gates 2-17 and 2-18 are supplied with the noise signal inverted by the inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28, and the output of the OR gate-28 is output as a detection pulse signal via the AND gate 2-29.
On the other hand, the outputs of the AND gates 2-15 to 2-18 are supplied to the OR gate 2-30, and the output of the OR gate 2-30 is output as the sampling signal SP1 via the AND gate 2-31 and also to the R input. The enable clear signal is supplied to the S input of the ATF enable latch 2-32. The Q output of the ATF enable latch 2-32 is output as an enable signal and is also supplied to the input of the AND gate 2-29. Output is AND gate 2-15 to 2-18
And 2-31 inputs to control its opening and closing.

With the above configuration, the sync detection circuit 202 operates as follows.

The limiter 2-2 outputs the digital signals corresponding to the sync 1 and sync 2 for the ATF in the RF signal, and the output of the EOR gate 2-4 becomes 1 in response to the phase inversion of the digital signal.
It becomes L for the clock. The output of this EOR gate 2-4 is D
The shift register 2-6 applied to the input responds to the rise of the basic clock f _M applied to the CK input when the window signal from the ATF window latch 2-5 applied to the R input is H. It takes in the D input, sends it to the Q ₁ output, and then sequentially shifts at each rising edge of the basic clock f _M ,
Send to Q _{2 to} Q ₁₁ outputs. That is, the shift register 2
-6 sends the Q ₁ to Q ₁₁ outputs 1-11 delayed clocks the output of the EOR gate 2-4.

When the output of Q ₁ is L, that is, when there is a change, this is transmitted through the inverter 2-7 to the AND gates 2-8 and 2
Is applied to -9, any one of Q ₆ to Q ₈ output becomes L, and to one input of the AND gate 2-8 through the NAND gate 2-10 H. For Q ₂ to Q ₅ output is H when there is no change. At this time, when the HSWP (A /) signal is L, the AND gate 2-8 is passed through the inverter 2-12.
H is applied to the input of.

In such a state, all inputs of the AND gate 2-8 become H and outputs become H. Therefore, when this condition is not satisfied, the output remains L, does not change in at least 4 clocks, changes in 5 to 7 clock periods, and HSWP (A /
) When the signal is L and the reproduction by the B head 1B is being performed, 1/2 cycle of the sync 2 signal is detected. Actually, since it is the sync 2 signal f ₃ (= 784 KHz, f _M / 12), the length that does not change is 6 clocks, but there is a margin of ± 1 clock due to clock timing, jitter, etc. It has.

1/2 of sync 2 signal from the output of AND gate 2-8
A pulse having a 1-clock period L in each cycle is output.
Also, from the output of the AND gate 2-9, the sync 1 signal f ₂ (= 520KHz, f _M / 18) is processed by the same process as the sync 2 and HSW.
The P (A /) signal is H, that is, detected when the A head 1A is reproducing, and is output from the AND gate 2-9. Note that the period without change is 7 clocks, and 8 to 10
Changes occur between clocks.

The sync 2 signal is output from the AND gate 2-8 when HSWP (A /) is L, and the sync 1 signal is output from the AND gate 2-9 when the HSWP (A /) signal is H via the OR gate 2-13. , The D input of the shift register 2-14.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock, sends it to the Q ₁ output, and thereafter shifts every time the clock is applied and sends it to the Q _{2 to} Q ₂₉ outputs. That is, the Q _{1 to} Q ₂₉ outputs are delayed by _{1 to 29} clocks and D
The input status is output.

If there is a change in the Q ₁ output of the shift register 2-14,
Q ₁ output goes high. Sync 2 signal (f ₃ = 780KHz, 1/12
In the case of f _M ), the output of the OR gate 2-21 becomes H when there is a change 1/2 cycle before with reference to the Q ₁ output. Also, 1
If there is a change before the cycle, the output of the OR gate 2-23 becomes H. Therefore, the output of OR gate 2-26 is 1/2 and / or
Alternatively, it becomes H when there is a change one cycle before. The output of the OR gate 2-26 is the Q ₁ output of the shift register 2-14 and HS.
It is applied to the input of the AND gate 2-20 together with the WP (A /) signal. That is, in the case of the sink 2, one clock is delayed after the sink 2 is detected by the AND gate 2-8.
An output appears at the Q ₁ output. At this time, the change of 1/2 cycle before is performed through the OR gates 2-21 and 2-26, and the change of 1 cycle before is performed through the OR gates 2-23 and 2-26. When applied to the inputs of the gate 2-20 at the same time, the output of the AND gate 2-20 becomes H, and accordingly the OR gate 2
-28 output goes high.

The outputs of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 become H when the sink 2 is set. Therefore, when the noise signal is L, the AND gate 2-18 Becomes H, which is output as the sampling signal SP1 through the OR gate 2-30 and the AND gate 2-31, and is applied to the S input of the ATF enable latch 2-32, and the Q of the ATF enable latch 2-32. The output becomes H and the output becomes L. The Q output is output as an enable signal and is also applied to the AND gate 2-29 so that the detection pulse signal can be output thereafter through the AND gate 2-29.

In the case of the sink 2, when the noise signal is H, the output of the AND gate 2-16 becomes H, and the same operation is performed.

On the other hand, in the case of sink 1, the outputs of the OR gates 2-22, 2-24 and 2-25 are H, and when the noise signal is L, the output of the AND gate 2-17 is H and the noise signal is H. Then the output of AND gate 2-15 becomes H,
The same is done as described above.

That is, the sync detection determination is switched between three points and four points according to the noise signal.

8 (a) to 8 (g) are timing charts showing the waveforms of the respective parts when the sink 2 is detected, and the corresponding reference numerals are given in FIG.

9 (A) to 9 (E) are timing charts showing the waveforms of the respective parts when the sink 1 is detected, and the corresponding reference numerals are given in the drawings.

FIG. 10 shows a specific configuration example of the ATF timing generator 203.

The ATF timing generator 203 has ▲ ▼ / EVEN signal, basic clock f _M , HSWP (A /) signal, enable signal, enable clear signal, The OK signal, the initial signal, and the detection pulse signal are input.

Enable signal at E input, basic clock f _{M at} CK input,
Then, the 0.25 block counter 3-1 to which the enable clear signal is input to the R input respectively makes the CY output H when performing the count corresponding to 9.5 μs, which is the E input of the high counter 3-2 and the decoder 3 -3 is input to each C input.

In the high counter 3-2, the basic clock f _M is input to the CK input, and the enable clear signal is input to the R input.
Count up every 0.25 block. The counter 3-
2 ^{_{Q 0 ~Q 3 (2 0 ~2}} 3) output is input to the decoder 3-3.

The decoder 3-3 is for decoding each time, and outputs 0 to 8, 16 and 17 are active only when the C input is H, and 0.25 to 2.25 block signals are output from the 0 to 8 output every 0.25 block. In addition, 4 block signals and 4.25 block signals are output from the 16 and 17 outputs, respectively.

The output of the decoder 3-3 is input to the gates 3-4 to 3-11, and the 0.5 block signal is R of the latch 3-12.
The input is supplied to the CK input of the D-type FF3-13, and one block signal is supplied to the CK input of the D-type FF3-14.

With HSWP (A /) signal Is input to the decoder 3-15, which is for decoding the position of the currently reproduced ATF signal.
~ 3 outputs B-ATF-1, A-ATF-1, B-ATF-2 and A-A
The TF-2 signal is output, and this is output to the gates 3-4 and 3-
In addition to No. 7, it is supplied to the gates 3-16 and 3-17.

Table 3-18 to which the HSWP (A /) signal and initial signal are input holds the singing detection threshold value, and the threshold value that is held is switched by the HSWP (A /) signal and the initial signal to synchronize. Set it in the detection counter 3-19. The HSWP (A /) signal sets the respective values for the sync 1 when reproducing the A head and for the sync 2 when reproducing the B head, and each value is 50% of the number of continuous sync patterns. However, when the initial signal is L, it is 60
%. The sync detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

The ATF timing generator 203 has a gate 3-
It has 20 to 3-27 and inverters 3-28 to 3-30.

Then, the output of the gate 3-10 is the sample signal SP2, the output of the gate 3-26 is an erroneous detection signal, the output of the gate 3-4 is the sample signal SP3A, the output of the gate 3-27 is the ATFEND signal,
Then, the sample signal SP3B is output to the output of each gate 3-7.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SP1, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK signal which become H due to the fall of the sampling signal SP1, and the CY block for each 0.25 block.
The output goes high. The decoder 3-3 has a high counter 3-
The state of 2 is decoded and the 0.25 block counter 3-1
The output becomes H only when the CY output is H.

When the 0 output of the decoder 3-3 appears, that is, 0.25 block after the generation of the sampling signal SP1, the crosstalk sample value of one adjacent track is equal to or less than 1/2 of the on-track level. Since it is L, the decoder 3-3 outputs to the output of the AND gate 3-8 to which the OK signal is input via the inverter 3-9.
D output does not appear. However, when there is no OK signal, the output of the AND gate 3-8 becomes H, and this is output from the OR gate 3-26 as an erroneous detection signal.

When 1 output of the decoder 3-3 becomes H, 0.5
As post-block processing, this is applied to the L input of the sync detection counter 3-19 via the OR gate 3-11, and also to the R input of the latch 3-12 and the CK input of the D-type FF3-13. .

Since the CY output of the sync detection counter 3-19 is input to the D input of the D type FF3-13 via the latch 3-12, whether or not there is a detection pulse signal above the specified value after 0.5 block. It will be sampled by D type FF3-13. At the same time, the latch 3-12 is reset and the threshold value from the table 3-18 is set again in the sync detection counter 3-19.

When the three outputs of the decoder 3-3 are H, the processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D input via the latch 3-12.
-14 is made to sample whether there is a specified value detection pulse after 1 block.

The combination circuit of the gates 3-20, 3-21, 3-23 and 3-30 determines whether or not there is a specified detection pulse signal based on the ▲ ▼ / EVEN signal. D type F for ODD
Both Q outputs of F3-13 and 3-14 are H, D-type FF in case of EVEN
When the Q output of 3-13 is H, the output of the OR gate 3-25 becomes H, because there is a specified detection pulse signal.

In the same process, if the initial signal is H,
The output of the OR gate 3-25 becomes H through the inverter 3-29 and the AND gate 3-22.

When the sync detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore, when the four outputs of the decoder 3-3 are H, that is, after 1.25 blocks, when the specified number of detection pulse signals are not detected, the OR gate 3-26 of the OR gate 3-26 is passed through the inverter 3-28 and the AND gate 3-9. An erroneous detection signal of H is output from the output.

When the 7 output of the decoder 3-3 is H, that is, after two blocks, the output of the AND gate 3-10 is used to sample another adjacent track due to the presence of the specified detection pulse signal and the OK signal. Outputs sampling signal SP2.

Further, after 4 blocks in which the 3 outputs of the decoder 3-15 are H and the 16 outputs of the decoder 3-3 are H during reproduction by the A head, the sampling signal SP3A is reproduced by the decoder 3 during reproduction by the B head. When 1 output of -15 is H and 16 outputs of the decoder are H, SP3B is output,
Lets you sample the on-track level.

Further, when 17 outputs of the decoder 3-3 are H, A head is ATF-2, and B head is ATF-1, gate 3-
The ATFEND signal is output via 17,3-5 and 3-27.
When 8 outputs of the decoder 3-3 become H when the A head is ATF-1 or the B head is ATF-2, the gate 3-1
The ATFEND signal is output via 6, 3-6 and 3-27.

FIGS. 11 (a) to 11 (l) are timing charts showing the waveforms of the respective parts associated with the above operation, and the corresponding symbols are assigned to the respective parts.

It should be noted that in the above-described embodiment, only the operation of the ATF signal processing unit is controlled on the basis of the head portion of the reproduction signal.
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as PCM and SUB-2.

[Effect]

As described above, according to the present invention, the timing of the timing means for starting the timing according to the pulse from the recording pulse generation means and generating the recording start signal after the predetermined first time is also reproduced. Since the reproduction start signal is generated after the start of the pulse in accordance with the pulse from the pulse generating means and the time measuring means measures the second predetermined time, the output signal including the noise at the time of switching the rotary heads is generated. It becomes possible to obtain the removed signal, and the structure is simplified because the time measuring means used for designating the recording start position at the time of recording is used as means for this purpose.

[Brief description of drawings]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, and FIG. 2 is a block diagram showing the essential parts of the present invention.
3 and 4 are timing charts showing signal waveforms of respective parts in FIG. 2, FIG. 5 is a circuit diagram showing a specific configuration of a part of FIG. 2, and FIG. 6 is FIG. 7 is a timing chart showing the signal waveform of each part of FIG. 7, FIG. 7 is a block diagram showing the concrete structure of the other part in FIG. 2, and FIGS. 8 and 9 are the signal waveforms of each part in FIG. FIG. 10 shows a timing chart, FIG. 10 is a circuit diagram showing a concrete structure of still another part of FIG. 2, FIG. 11 is a timing chart showing signal waveforms of respective parts in FIG. 10, and FIG. FIG. 13 is a diagram showing a track format and a block format of R-DAT,
FIG. 14 is a diagram showing an ATF track pattern of R-DAT, and FIG. 14 is a diagram for explaining the principle of tracking control by the track pattern of FIG. 1A, 1B …… Rotary head, PGA, PGB …… Pulse generator, 3 …… System controller, 12 …… Initial counter, 13 …… Table, 13b, 13c …… And gate, 1
7 ... Decode data processing unit, 18 ... Encode data processing unit.

Claims (1)

(57) [Claims] 1. A plurality of oblique tracks are formed on a recording medium, and a plurality of signals including a digital signal obtained by converting an audio signal into a PCM signal into a PCM signal and time-axis-compressed to each track have independent recording areas in the longitudinal direction of each track. At least two recording / reproducing rotary heads for recording in a predetermined format and reproducing the plurality of signals on the recording medium, and a predetermined positional relationship with respect to the two recording / reproducing rotary heads. And at least one pulse generating means for rotating together with the rotary head to generate a pulse for each rotation, the two rotary heads are alternately switched according to the pulse from the pulse generating means, and at the time of recording each time. In the case where a rotary head records multiple signals on each track and each rotary head reproduces multiple signals from each track during playback, A clocking means for starting clocking in response to a pulse from the pulse generating means, and generating a recording start signal for designating a signal processing time point in the timed encoded data processing section for a predetermined first time; Time reproduction is started in response to the pulse from the pulse generating means, and the time counting means is started, and after the predetermined second time is counted, the time counting means is started to specify a signal processing time point in the decode data processing unit. A digital signal recording / reproducing apparatus comprising: a control unit for generating a signal.