JP2531631B2 - Digital signal playback device - Google Patents

Description

Description: TECHNICAL FIELD The present invention converts an audio signal into a PCM signal and reproduces a digital signal recorded as one diagonal track on a recording medium by a rotary head for each unit time. The present invention relates to a digital signal reproducing device suitable for the operation.

[Technical background of the invention and its problems]

A device for recording and reproducing an audio signal on a magnetic tape by forming a diagonal track for each unit time by a helical scan type rotary head, and converting the audio signal into PCM when reproducing. DAT (rotary head type digital audio
There is a digital signal recording / reproducing device called a tape recorder.

The format of the track actually recorded in the R-DAT has a pattern as shown in Fig. 12 (a), and the frequency of each of MARGIN, PLL, and POSTAMBLE is 1 / 2f _M (f
_M = 9.4MHz), frequency of IBG is a 1 / 6f _M. The SUB and PCM are composed of blocks as shown in FIG. 12 (b). SYNC is fixed to 9 bits, and the rest have various patterns depending on the location, voice signal, and the like. In the case of SUB, this block is repeated eight times, and in the case of PCM, this block is repeated 128 times. The numerical values in FIG. 12 (a) represent the number of blocks occupied by each area.

Located between SUB-1 and PCM and between PCM and SUB-2
Area of ATF1 and ATF2 (ATF: Automatic Track Finding)
Is to enable tracking control so that the rotary head correctly scans the recording track during reproduction by the output of the rotary head without providing a special head.

That is, in the ATF area, the PCM signal is time-axis compressed to 2
When forming tracks on a magnetic tape diagonally by a rotating head without a guard band and recording, the recording area is independent of the PCM signal at the beginning and end of each track, and tracking pilot signals are respectively provided. Record,
During reproduction, the rotary head, which has a scanning width wider than the width of the track, scans a recording track, and the rotary head is used to control the tracking of the rotary head by reproducing output of pilot signals from both adjacent tracks of the track being scanned. It

And the track pattern for this ATF is the 13th
It is determined as shown in the figure, and the case where the illustrated pattern has a drum diameter of 30 mm, a drum winding angle of 90 °, and a rotation speed of 2000 rpm will be described.

ATF1 and ATF2 on the front and back of each track
Has a low-frequency signal f ₁ with little azimuth effect as a pilot signal for tracking, which detects the level of crosstalk from both adjacent tracks during playback, and the level of the crosstalk component of both adjacent tracks. It is used to obtain the difference as a tracking error signal. A low frequency signal of f _M / 72 (130 KHz) is used as the pilot signal f ₁ .

Also ATF1 and ATF2 are sync signals to determine the position of the pilot signal f ₁ is recorded is recorded. Since the on-track and the adjacent track cannot be distinguished from each other if there is crosstalk in the sync signal, a frequency having an azimuth effect and a pattern which does not exist in the PCM signal is selected. When the head corresponding to + azimuth is A and the head corresponding to −azimuth is B, the sync signals are different from each other in order to distinguish the A head and the B head, and the frequency is different for the A head. f _M / 18
The sync 1 signal f ₂ of (= 522 KHz) and the sync 2 signal f ₃ of frequency f _M / 12 (= 784 KHz) are recorded at predetermined positions for the B head.

In the R-DAT, an erasing head is not provided, and rewriting of a signal is performed by so-called overwriting, which overwrites the previous recording. Therefore, the erase signal f ₄ having the frequency f _{M /} 6 (= 1.56 MHz) is recorded at a predetermined position for erasing the pilot signal f ₁ , sync 1 signal f _2, and sync 2 signal f ₃ of the previous recording. It

The positions of the ATF pilot signal are different on the on-track and on both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal on both adjacent tracks are temporally different, and three types of levels are sampled respectively. Are arranged so that they can.

Five blocks are assigned to each of the ATF areas of ATF1 and ATF2, and the pilot signal f ₁ is recorded in two of the blocks. The sync signals f ₂ and f ₃ are recorded using one block or 0.5 blocks from the center of the position where one adjacent track is recorded. The pilot signal f ₁ of the other adjacent track is recorded such that the center thereof is located two blocks after the beginning of the sync signal recorded on the on-track. The sync signal of one block is assigned to the odd frame and the sync signal of 0.5 block is assigned to the even frame.

As described above, in the ATF, the sync signal frequency differs depending on the A head and the B head, and the sync signal recording length differs between the odd frame and the even frame. Therefore, different ATFs are given to all four consecutive tracks, so that they can be distinguished. The ATF pattern as described above is a 4-track completion type, which is repeated every 4 tracks.

By the way, when a magnetic tape recorded in a format as shown in FIG. 12 (a) is reproduced by a rotary head, an RF signal as shown in FIG. 14 (a) is obtained from the rotary head. If this RF signal is obtained, for example, by reproducing the odd frame track (A) in FIG. 13, 130 KHz
By passing the band pass filter (BPF) of
A pilot signal f ₁ as shown in (b) is obtained.

Section I is due to the on-track pilot signal,
The sections II and III are due to the crosstalk of the pilot signals of (B) odd frame tracks and (B) even frame tracks. When the rotary head is scanning on the track correctly, the intervals II and III are originally
Envelope level, ie, (c) VII and VIII
Should be equal, but if there is a track deviation, VII ≠ VII
It becomes I, and the amount and direction of the displacement of the rotary head with respect to the on-track can be known from its size and polarity. Therefore, VII and VII
The difference in I activates the capstan servo to fine-tune the tape speed, which allows the rotary head to run on track.

In order to perform the above-described operation, it is necessary to accurately detect the sync signal at the predetermined position and sample the VII and VIII levels. However, since the R-DAT does not have an erasing head as described above and performs the second and third recording by overwriting, it correctly detects the sync signal, samples VII and VIII, and corrects the error. Sometimes it was not possible to generate a signal.

That is, in R-DAT, recording is ± 2 from the center of the PCM area.
It is supposed to be done within a block. The recording level of the pilot signal f ₁ (= 130 KHz) is set to be slightly lower than the levels of other signals. This is because the lower the frequency of the signal is, the deeper the recording level on the tape is, and the pilot signal f ₁ recorded before the overwrite can be erased by the erase signal. However, by lowering the level of the pilot signal f ₁ in this way, when the pilot signal f ₁ is newly recorded at the previously recorded sync signal f ₂ or f ₃ , the previous sync signal is completely erased. It may remain without it.

Specifically, when the later recording is performed earlier than the previous recording, the sync signal of the later recording always precedes the unerased sync signal of the previous recording on the track. Therefore, this does not cause a problem, but when the subsequent recording is shifted backward, the unerased sync signal precedes the sync signal of the subsequent recording. An example of this is the case where there is a shift within the range of 1 to 2 blocks later.
For F-1, (A) even frame, (A) odd frame, for ATF-2 (B) even frame,
(B) In the odd-numbered frame, part or all of the sync signals f ₂ and f ₃ of the previous recording are erased in the part of the pilot signal f ₁ .

When this happens, the level of the frequency component of the pilot signal in the reproduced RF signal at that time is sampled according to the sync signal of the previous recording. This pilot signal should originally be at the crosstalk level of the sampling signal of one adjacent track, but the above-described frequency component to be sampled is the on-track pilot signal itself, and the level obtained by the sampling is a very large value. Becomes After that, the frequency component of the pilot signal in the reproduced RF signal after two blocks is sampled, the difference between this sampled value and the sampled value two blocks before is taken, and this level difference is used as the track deviation amount to control the capstan servo. However, since the sampled earlier is the on-track level, not the cross-talk level of the adjacent track, a very large level difference far from the actual track deviation amount can be obtained. If this happens, the capstan servo will be disturbed and the tape running will be adversely affected.

[Object of the Invention]

The present invention solves the above-mentioned problems and enables the tracking control to be normally performed without malfunction even if the sync signal of the previous recording is erased and left at a position preceding the sync signal of the subsequent recording by overwriting. It is an object of the present invention to provide a digital signal reproducing device that has

[Outline of Invention]

The present invention has been made to achieve the above-described object, and the level of the pilot signal frequency component in the output signal of each rotary head has a predetermined relationship with the level of the on-track pilot signal which is being sampled and held. If it is determined that it is not due to the pilot signals of both adjacent tracks, the sync signal detection is prohibited, and an error occurs due to the level difference between the level of the on-track pilot signal and the level after a certain time due to false detection of the sync signal. Disturbance of the capstan servo is prevented by preventing the capstan servo control from occurring.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of an apparatus according to the present invention configured as a digital signal recording / reproducing apparatus.

In the figure, reference numeral 1 denotes a rotary drum having a diameter of 30φ, and the rotary drum 1 has an A head 1A for recording / reproducing + azimuth and a −
Two rotating heads with B head 1B which records and reproduces azimuth
Two pulse generators (PG) PGAs are placed 180 ° apart and at the intermediate position between A head 1A and B head 1B.
And PGB are arranged.

Reference numeral 2 is a crystal oscillator that generates a basic clock f _{M of} 9.4 MHz, and the basic clock f _M is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) for controlling the system, which outputs a PB / ▲ ▼ switching signal to control switching of the toggle switch 4 including switches SW1 and SW2.

Reference numeral 5 is a reference signal generator, which generates reference signals of XHz (66Hz: 2PG), YHz (depending on the number of capstan motor FGs) and ZHz based on the basic clock f _M applied to the CK input. .

A drum servo 6 servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on the reference signal ZHz under the control of the system controller 3. Reference numeral 8 denotes a capstan servo which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when the switch 4 is switched to the b contact side by the system controller 3 and the switch 4 is switched to the a contact side. During reproduction, the rotation of the capstan motor is servo-controlled based on the track shift amount.

9 is an HSWP (A /) signal generator, which is 2 on the drum 1.
A head 1A and B head based on pulses from one PG
Generate HSWP (A /) signal to switch between 1B and HSWP
The (A /) signal becomes H for the A head and L for the B head, which is also supplied to each part of the system.

Reference numeral 10 is a phase inversion detection circuit, to which the basic clock f _M and HSWP (A /) signal applied to the CK input are input, and the output is supplied to the S input of the initial flag latch 11. The CY output of the initial counter 12 is input to the R input of the initial flag latch 11, and the Q output is supplied to the R input of the initial counter 12.

The initial counter 12 is set with a threshold value from the table 13 under the control of the PB / ▲ signal from the system controller 3, and the CY output becomes H by counting the set value. The
CY output is applied via inverter 13a PB / ▲
▼ Input to the encode data processing unit 18 via the AND gate 13b which is opened / closed by a signal, and PB / ▲
The signal is supplied to the S input of the head touch window flag latch 14 through the opening and closing AND gate 13c by a signal.

The head touch window flag latch 14 is for generating a window for inhibiting the head touch detection operation during noise during head switching. The Q output is input as an ON signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from the section 17.

Reference numeral 15 is a reproduction amplifier, which amplifies the signals from the rotary heads 1A and 1B and supplies the signals to a decode data processing unit 17 described later. Reference numeral 16 denotes a recording amplifier, which receives recording data from an encode data processing unit 18 described later based on the HSWP (A /) signal and supplies the recording data to the rotary heads 1A and 1B via a switch SW1.

The decoded data processing unit 17 extracts data from the RF signal from the reproduction amplifier 15, performs 10/8 conversion (demodulation), deinterleaving, error correction, etc., and sends the data to the D / A conversion unit, and also detects head touch. , ATF sync detection, tracking error detection, etc., and track deviation signal generator 17a
Supplies an error signal to the capstan servo 8.

The encoded data processing unit 18 interleaves, adds parity, 8/10 conversion, ATF for A / D converted data.
The signal is added and then supplied to the recording amplifier 16.

In the above configuration, the system controller 3
When the PB / ▲ ▼ signal is L, the recording operation is performed.

Switch 4 because PB / ▲ ▼ signal is L
Is switched to the b contact side, the reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, and the capstan servo is applied based on the reference signal YHz to control the tracking.

HSWP (A /) output from HSWP (A /) generator 9 based on the pulse generated by PGA and PGB by rotation of drum 1.
The signal is H when the A head is 1A and is L when the B head is 1B. This HSWP (A /) signal is input to the phase inversion detection circuit 10,
When the level of the HSWP (A /) signal changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H only for one basic clock period.

In response to the rise of the output of the phase inversion detection circuit 10 from L to H, the initial flag latch 11 is set and its Q output becomes H. As a result, the initial counter 12 starts the counting operation. In this example, the initial counter 12 uses the set value from Table 13 for 3.75ms
When the number of basic clocks f _M corresponding to a certain period corresponding to is counted, the CY output thereof rises, which resets the initial flag latch 11 and
The rising edge of the CY output is applied to the encode data processing unit 18 as a recording start signal. Based on this recording start signal, the encoded data processing unit 18 outputs recording data in a predetermined format.

Next, when the PB / ▲ ▼ signal from the system controller 3 is H, the switch 4 is set to the a side and the rotary head
1A and 1B are connected to the reproduction amplifier 15, and the RF signal is supplied to the decoded data processing unit 17.

The capstan servo 8 operates based on the track shift amount supplied from the decode data processing unit 17. The track shift amount is an ATF error signal according to the level difference of the crosstalk amplitude of the pilot signals of both adjacent tracks,
Details will be described later.

The HSWP (A /) generator 9 and the phase inversion detection circuit 10 operate in the same way as during recording, but the initial counter 12 becomes a counter in the reproduction mode according to the set value from the table 13, and the count value corresponds to 100 μs / 1 ms, for example. CY output becomes H when the value reaches. This prohibits the head touch operation described later while noise is generated when the heads are switched, and after a certain period of time, the head touch window flag latch 14 is set via the AND gate 13 to set its Q output. This is because it is set to H and an ON signal for head touch detection is output. The ON signal from the head touch window flag latch 14 is touched by the decode data processing unit 17, that is, the tape T and the head 1A or 1B.
When it is detected that the contact occurs with the output of the RF signal, the head touch window flag latch 14 is cleared and the ON signal becomes L.

Hereinafter, details of a portion particularly related to tracking control in the decoded data processing unit 17 will be described with reference to the block diagram of FIG.

In the figure, an upper part is an analog system and a lower part is a digital system from the one-dot chain line. The analog system includes a reproduction amplifier 15, a bandpass filter (BPF) 101, an envelope detector 102, a first sample hold (S / H) circuit 103, a second S / H circuit 104, and a third S / H.
H circuits 105a and 105b, toggle switch 106, comparator
107, differential amplifier 108, level correction circuit 109, and resistor R
_It consists of _{1 to} R ₄ .

On the other hand, the digital system includes the crystal oscillator 2, the head touch detection circuit 201, the sync detection circuit 202, and the ATF timing generator 20.
3, playback flag latch 204, system counter 205, timing generator 206, 1/2 divider 207, ATF initial flag latch 208, power-on reset circuit 209, latch circuit 210, protection counter 211, noise flag latch 212, latch 213, an erroneous detection counter 214, a sampling counter 215, OR gates 216 to 218, and an inverter 219.

First, in the analog system, the RF signal from the rotary heads 1A and 1B (FIG. 1) is input to the input of the reproduction amplifier 15, and the output is input to each input of the BPF 101, the head touch detection circuit 215, and the sync detection circuit 216. Is being supplied.

The BPF 101 passes only the 130 KHz component in the RF signal and inputs it to the envelope detector 102. Envelope detector 1
02 detects the 130 KHz component by envelope detection, and this is the S / H circuit 1
It is applied to each input of 03, 105a, 105b and the + input of the differential amplifier 108.

The S / H circuit 103 uses the sampling signal SP1 applied to the C input from the sync detection circuit 202 to determine the envelope detector 1
The output of 02 is sample-held and this is
7 and the negative input of the differential amplifier 108. What is sampled and held by the S / H circuit 103 is the DC level of the crosstalk of the pilot signals of one adjacent track.

The S / H circuit 104 is applied with a signal whose level is adjusted by the level adjusting circuit 109, samples and holds this by the sampling signal SP2 from the ATF timing generator 203, and ATF is applied to the capstan servo 8 (FIG. 1). It is supplied as an error signal. The error signal is the DC level difference of the crosstalk on both adjacent tracks.

The S / H circuit 105a outputs the output from the envelope detector 102 to the AT.
The sampling signal SP3A from the F timing generator 203 is used to sample and hold, and this is output to one end of the resistor R ₁ and the a contact of the switch SW1 of the toggle switch 106. S / H circuit 1
What is sample-held by 05a is the DC level of the on-track pilot signal during A track playback.

The S / H circuit 105b outputs the output from the envelope detector 102 to the AT.
Sampled and held by a sampling signal SP3B from F timing generator 203, and outputs it to the contact b of the switch SW1 of the one end and the toggle switch 106 of the resistor R _3. S / H circuit 1
What is sample-held by 05b is the DC level of the on-track pilot signal during B track reproduction.

The resistors R _{1 to} R ₄ have the same value, and are for dividing the outputs of the S / H circuits 105 a and 105 b applied to _one ends of the resistors R ₁ and R ₃ , respectively. The interconnection point of resistors R ₁ and R _{2 and} the interconnection point of resistors R ₃ and R ₄ are toggle switches 106.
The switch SW2 is connected to the a-contact and the b-contact, respectively, and at each interconnection point, a half level of the sample hold value of each S / H circuit can be obtained.

The toggle switch 106 is controlled by the HSWP (A /) signal and is switched to the a side when the HSWP (A /) signal is H and to the b side when the HSWP (A /) signal is L.

Comparator 107 has S / H circuits 105a and 105b at one input.
1/2 level of the output of the envelope detector 102 is applied to the other input through the resistors R _{1 to} R ₄ and the switch SW 2.
Is applied. The output of the comparator 107 becomes H when 1/2 of the sample and hold values of the S / H circuits 105a and 105b is smaller than the output level of the envelope detector 102, and this is supplied to the input of the OR gate 217 and also via the inverter 219. Supply to the input of OR gate 218.

The differential amplifier 108 is an S / H circuit applied to the output of the envelope detector 102 applied to the + input and to the − input.
The difference from the output of 103 is calculated and input to the level adjustment circuit 109. That is, when the output of the envelope detector 102 outputs the DC level of the crosstalk of the other adjacent track, the difference between the crosstalks of the adjacent tracks, that is, the track shift amount is output.

The level adjusting circuit 109 changes the amplification degree, for example, in inverse proportion to the output levels of the S / H circuits 105a and 105b.
Rotating head 1 by adjusting the signal level from 8
Correct the output variation of A and 1B.

Next, the digital system will be described. The head touch detection circuit 201 includes a head touch window flag latch 14
The ON signal from (Fig. 1) and the basic clock f _M
Detects that an RF signal has been input, and reproduces the flag latch
A signal is supplied to the S input of 204, which will be described in detail later.

The sync detection circuit 202 uses RF signal, HSWP (A /) signal,
The ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise flag latch 212, the basic clock f _M from the crystal oscillator 2, and the enable clear signal from the OR gate 216 are input. , And sends the sampling signal SP1, the enable signal and the detection pulse signal to its output. The sampling signal SP1 is input to the C input of the S / H circuit 103 and the R input of the latch 210, and the enable signal and the detection pulse signal are input to the ATF timing generation circuit 203, respectively. The sync detection circuit 202, after converting the RF signal to a digital signal, detects the beginning of the ATF sync patterns SY1 and SY2 of the rotary heads 1A and 1B, outputs the sampling signal SP1, and then outputs the sync signals to the continuously detected syncs. It operates so as to output a detection pulse signal, which will be described in detail later.

The ATF timing circuit 203 is the Q output of the 1/2 frequency divider 207, the ▲ ▼ / EVEN signal, and the ATF initial flag latch.
Initial signal that is Q output of 208, sync detection circuit 202
Enable signal and detection pulse signal from, after / from timing generator 206 The signal, the enable clear signal from the OR gate 216, and the basic clock f _M from the crystal oscillator 2 are input, and sampling signals SP2, SP3A, SP3B, erroneous detection signals,
And sends the ATFEND signal. Sampling signal SP2 is S / H
To the C input of the circuit 104 and the S input of the ATF initial flag latch 208, the sampling signal SP3A is to the C input of the S / H circuit 105a, and the sampling signal SP3B is to the C input of the S / H circuit 105b.
The false detection signal is input to the S input of the latch 210, one input of the OR gate 216 and the CK input of the false detection counter 214, and the ATFEND signal is input to one input of the OR gates 216 and 217, respectively.

The ATF timing generator 203 receives an enable signal from the sync detection circuit 202, enables a timer counter (not shown) for timing generation when the signal is H, and outputs a detection pulse signal from the sync detection circuit 202. After receiving and counting it, if the detection pulse exceeds the specified value by the specified time, sampling signals SP2, SP3A, SP3B
Is output, and when the OK signal that is less than the specified value or the output of the comparator 107 is at the L level, it operates so as to output an erroneous detection signal.

The crystal oscillator 2 oscillates at a transmission rate of R-DAT channel bit data of 9.4 MHz and outputs a basic clock f _M. The basic clock f _M is the head touch detection circuit 201,
It is applied to the CK inputs of the sync detection circuit 202, the ATF timing generator 203, the system counter 205, and the protection counter 211, respectively.

The latches 204, 208, 210 and 213 are formed of RS flip-flops whose Q output is H in response to the rising edge of the S input and whose Q output is L in response to the rising edge of the R input.

The reproduction flag latch 204 has an S input for the output of the head touch detection circuit 201 and an R input for the timing generator 206.
The END signal which is the output of each of the above is input, and its Q output is input to the R input of the system counter 205. When the Q output of the reproduction flag latch 204 is H, the reproduction operation is in progress.

The system counter 205 has a playback flag latch 2 on the R input.
The Q output of 04 is input to the CK input of the basic clock f _M , and its outputs Q _{0 to} Q _X are input to the timing generator 206. The system counter 205 is for roughly indicating the position where each signal is recorded on the track.

The timing generator 206 outputs an ATF window set signal (via OR gate 218) to the output based on the Q ₁ -Q _X outputs from the system counter, after / Signal, window clear signal and END signal are generated, and ATF
Send the window set signal to the sync detection circuit 202 The signal is supplied to the ATF timing generator 203, the window clear signal is supplied to the OR gate 217, and the END signal is supplied to the R input of the reproduction flag latch 204. The timing generator 206 decodes the output of the system counter 205 and generates the timing required for each unit.

The 1/2 frequency divider 207 divides the HSWP (A /) signal applied to the CK input by 1/2 to generate a ▲ ▼ / EVEN signal at the Q output,
This is supplied to the ATF timing generator 203. The Q output of the ATF initial flag latch 208 is input to the R input of the 1/2 frequency divider.

In the ATF initial flag latch 208, the sampling signal SP2 from the ATF timing generator 203 is input to the S input, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is the R input of the 1/2 frequency divider 207. Is input to the ATF timing generator 203. The ATF initial flag latch 208 generates a flag indicating that the capstan servo by the ATF is being applied.

The power-on reset circuit 209 outputs H when the power is turned on.
Becomes

The latch 210 has its S input inputted with the erroneous detection signal from the ATF timing generator 203, its R input inputted with the sampling signal SP1 from the sync detection circuit 202, and its Q output inputted with the R input of the protection counter 211. When the latch 210 is erroneously detected, the Q output becomes H and is reset according to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain time from an erroneous detection, and counts the basic clock f _M applied to the CK input only when the R input is H, and is cleared by L of the R input. The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise flag latch 212 is for temporarily storing whether noise is being reproduced or not, and is composed of a D-type flip-flop. The latch 212 has a D input for the Q output of the latch 213 and a CK input for the sampling counter 2
The 15 CY outputs are respectively input, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

The latch 213 receives the CY output of the false detection counter 214 at the S input,
The CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise flag latch 212.

The false detection counter 214 uses the ATF timing generator 20 for the CK input.
False detection signal from 3 is input to sampling counter 2
Each of the 15 CY outputs is input, and the CY output is supplied to the S input of the latch 213. The erroneous detection counter 214 counts the number of times the sampling signal SP1 is erroneously detected in a certain period, and when it exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives the HSWP (A /) signal at the CK input, the CY output at the R input of the false detection counter 214,
The R input of the latch 213 and the noise flag latch 212
It is supplied to each CK input.

The OR gate 216 receives the erroneous detection signal and the ATFEND signal from the ATF timing generator 203 and the CY output of the protection counter 211, and sends an enable clear signal to the sync detection circuit 202 and the ATF timing generator 203 at its output.

The OR gate 217 is an output signal of the comparator 107, a window clear signal from the timing generator 206, an ATF
The ATFEND signal from the timing generator 203 and the CY output from the protection counter 211 are input, and the ATF window off signal to the sync detection circuit 202 is sent to the output.

The OR gate 218 is a comparator via an inverter 219.
The output of 107 and the output of the timing generator 206 are input, and the ATF window set signal is sent to the output.

In the above configuration, the RF signal is supplied to the head touch detection circuit 201 and the sync detection circuit 202 via the reproduction amplifier 15 and the BPF 101. RF supplied to BPF101
Only the 130 KHz component of the signal is passed. The amplitude level of the 130 KHz component is converted to a DC level by the envelope detector 102, and then applied to each input of the S / H circuits 103, 104, 105a and 105b, one input of the comparator 107 and + input of the differential amplifier 108.

The envelope detector 102 sequentially outputs the crosstalk of the pilot signal of one adjacent track and the DC level of the amplitude of the crosstalk of the pilot signal of the other adjacent track in order in time series. The DC level of the on-track pilot signal amplitude is output before or after the signal.

The S / H circuit 103 outputs the pilot signal of one adjacent track.
DC level is the sampling signal S from the sync detection circuit 202
Sample and hold at the timing of P1. The crosstalk level of the one adjacent track sampled and held is applied to the-input of the differential amplifier 108.

The S / H circuit 105a displays the DC level of the on-track pilot signal during playback of the + A azimuth A track,
-Samples and holds the DC level of the on-track pilot signal during reproduction of the azimuth B track. The output of the S / H circuit 105a, that is, the DC level of the on-track pilot signal is supplied to the control input of the level adjustment circuit 109 via the a contact of the switch SW1 of the toggle switch 106, and the resistors R ₁ and R ₂ are also supplied. The voltage is divided by 1/2 by the comparator 107 via the contact a of switch SW2.
Is supplied to one of the inputs. Similarly, the output of the S / H circuit 105b is supplied to the level adjusting circuit 109 via the b contact of the switch SW1.
Further, after being divided into ½ by the resistors R ₃ and R ₄ , the voltage is supplied to one input of the comparator 107 via the b contact of the switch SW2.

The output of the comparator 107 becomes L when 1/2 of the level input via the switch SW2 is larger than the input from the envelope detector 102. That is, it is determined that the output of the envelope detector 102 is the crosstalk of one adjacent track. In the opposite case, it is determined to be an on-track pilot signal. Therefore, when the output of the comparator 107 is H, the sync detection circuit 20 is connected via the OR gates 217 and 218 to prohibit the detection of the sync.
Supply ATF window off signal to 2. When the output of the comparator 107 changes from H to L, this is inverted by the inverter 219, and the output of the OR gate 218 is ATF.
The window set signal comes to be output.

In the differential amplifier 108, when the envelope detector 102 outputs the DC level of the crosstalk amplitude of the other adjacent track, the DC level of the crosstalk amplitude of the one adjacent track is input to the-input. Therefore, a difference in DC level of crosstalk between adjacent tracks, that is, a track shift amount is obtained at the output, and this is input to the level adjustment circuit 109.

The output of the S / H circuits 105a and 105b is applied as a control input to the level adjusting circuit 109. When the control input is large, the level of the input signal is lowered, and when the control input is small, the level is raised and output. In short, the level adjusting circuit 109 automatically corrects the variation in the outputs of the two rotary heads and inputs the corrected output to the next S / H circuit 104. The S / H circuit 104 samples and holds the deviation amount of both adjacent tracks after correction by the sampling signal SP2. The output of the S / H circuit 104 is supplied to the capstan servo 8.

FIGS. 3 (a) to 3 (i) are timing charts showing the signal waveforms generated in the respective parts by the above operation, corresponding to the reference numerals assigned to the respective parts.

The HSWP (A /) signal shown in FIG. 3 (b) becomes H when reproducing by the A head 1A of + azimuth, and becomes L when reproducing by the B head 1B. When the head is switched, the phase of the HSWP (A /) signal is inverted. When the phase is inverted, the Q output of the initial flag latch 11 (Fig. 1) becomes H, and the initial counter 12 (Fig. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is judged that the tape has passed the noisy portion, and the head touch window flag latch 14 (Fig. 1) is set to set the Q value.
Set the output to H. When the Q output of the head touch window flag latch 14 becomes H, the head touch detection circuit 201
Works.

When the head touch detection circuit 201 detects that the tape and the head are in contact with each other and the RF signal is reproduced, the output becomes H, and the reproduction flag latch 204 is set to set the Q output to H. When the Q output of the reproduction flag latch 204 becomes H, the system counter 205 starts counting operation. Based on this time point, the system counter 205 can make a rough judgment about the recorded position of each signal on the tape. Timing generator 206
Is ATF-1, A based on the Q _{0 to} Q _X outputs of system counter 205.
The ATF window set signal is supplied to the sync detection circuit 202 shortly before TF-2 is recorded.

The sync detection circuit 202 suspends the sync detection operation when the output of the comparator 107 becomes H after the ATF window set signal is applied, and the output of the comparator 107 becomes L.
When it becomes, the sync detection operation is restarted. According to this sync detection operation, after converting the RF signal into a digital signal, A
Each sync is detected based on the fact that the patterns of the sync 1 (= f ₂ ) in the case of reproduction by the head 1A and the sync 2 (= f ₃ ) in the case of the B head 1B have the relationships shown in the table below depending on the frame. .

Here, when the sync detection circuit 202 detects four syncs in the normal case or five syncs in the case of noisy, the sampling signal SP1 is output and the S / H circuit 103 crosses the pilot signal f1 of _one adjacent track. The talk level is sampled and held, and the enable signal is supplied to the ATF timing generator 203. Then, the detection pulse signal is supplied to the ATF timing generator 203 each time a continuous sync is detected.

The ATF timing generator 203 operates a sync detection counter and a timer according to H of the enable signal from the sync detection circuit 202. The ATF timing generator outputs 0 after the sampling signal SP1 is output from the sync detection circuit 202.
After 25 blocks, it is checked by the sampling signal SP1 whether the crosstalk of the adjacent track is sampled and held correctly. Next, after 1.25 blocks, it is judged whether or not the sync is detected more than the specified value. If it is more than the specified value, it is determined that the sync is correctly detected, and two blocks later, the sampling signal SP2 is supplied to the S / H circuit 104, and both adjacent tracks are detected. The crosstalk level difference is sampled and held, and its output is supplied to the capstan servo 8 as a track shift amount.

Further, when the on-track pilot signal f ₁ exists after the sync, the ATF-
2. Since it is the time of ATF-1 when reproducing the B head, in this case, the sampling signals SP3A and SP3B are output after four blocks, respectively, and are supplied to the S / H circuits 105a and S / H105b, respectively. The level of the on-track pilot signal being reproduced by is sample-held.

When the series of operations described above are correctly performed, the ATFEND signal is output, and this is supplied to the sync detection circuit 202 and the ATF timing generator 203 as an enable clear signal via the OR gate 216. ATFEND signal is also OR gate 2
Sync detection circuit 20 as a window-off signal via 17
2, the window for sync detection by the sync detection circuit 202 disappears accordingly, and the operation of detecting the pattern of the sync signal is stopped.

If the sync does not exceed the specified value, the false detection signal is set to H.
Then, the Q output of the latch 210 is set to H to cause the protection counter 211 to perform the counting operation and the erroneous detection counter 214 to perform the +1 operation. When the erroneous detection signal becomes H, the sync detection circuit 202 also passes through the OR gate 216.
And the enable clear signal to the ATF timing generator 203 becomes H. When the enable clear signal becomes H, the sync detection circuit 202 performs the operation of detecting the sync again from the beginning, and outputs the sampling signal SP1 again when the sync is detected. Meanwhile, the ATF timing generator 203 sets the sync detection counter and the timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal SP1
Is output, the latch 210 is reset and the Q output is
Therefore, the protection counter 211 is set to the initial state.

After the false detection signal is output once, C of the protection counter 211
After the Y output becomes H, that is, after a specified time (2.5 blocks), the sync detection circuit 202 is passed through the OR gate 216.
Also, the enable clear signal to the ATF timing generator 203 becomes H, and the operation is stopped.

Further, the sampling counter 215 becomes +1 at the rising edge of the HSWP (A /) signal, which means that the tape is managed for a certain length, and if the erroneous detection exceeds a certain level during that period, the erroneous detection counter 214 The CY output becomes H, whereby the Q output of the noise flag latch 213 is set to H and the sync detection circuit 202 is informed that the tape is noisy.

Also, the window clear signal from the timing generator 206 causes the ATF window off signal to the sync detection circuit 202 via the OR gate 217 to become H, which is for a large measure against dropout.

4 (a) to (c) and (A) to (G) are timing charts showing the outline of the signal waveform of each part of the digital system after the initial flag latch 11 is set at the time of reproduction, Corresponding numerals are given in FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific configuration example of the above-mentioned head touch detection circuit 201.

In the figure, the comparator 1-1 has an RF signal input to one input and a reference voltage + V input to the other input. The RF signal is input to one input of the comparator 1-2, and the reference voltage -V is input to the other input. The outputs of the comparators 1-1 and 1-2 are OR gates 1-
3, D-type flip-flop (FF) 1 via resistor 1-4
It is connected to the D input of -5, and is also a capacitor
Is connected to ground via.

The basic clock f _M is input to the CK input of the D type FF 1-5, the Q output thereof is connected to the input of the AND gate 1-7, and the output thereof is connected to the input of the AND gate 1-8.

The basic clock f _M is input to the inputs of the AND gates 1-7 and 1-8, and the respective outputs are connected to the UP input and the DOWN input of the up / down counter 1-9, respectively. Q _A to Q _D output of the up-down counter 1-9 to the input of the AND gate 1-8 through the OR gate 1-10, CY output is connected to the CK input of D-type FF1-11. D
The D input of the model FF1-11 is connected to _Vcc , and the Q output is the output of the touch detection circuit 201.

The head touch window flag latch 14 (first unit) is connected to the R input of the up / down counter 1-9 and the D type FF 1-11.
The Q output shown in the figure) is applied.

In the above configuration, the output of the comparator 1-1 becomes H when the level of the RF signal is higher than + V, and becomes L when the level of the RF signal is low. The output of the comparator 1-2 becomes H when the level of the RF signal is higher than -V to one side, and becomes L when the level is low. That is,
When the RF signal is not within the range of ± V, the output of the OR gate 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 form an integrator circuit, and the integrator circuit absorbs noise and the like in the output of the OR gate 1-3. The output of the OR gate 1-3 from which spike noise has been removed by the integrating circuit is a D-type FF1-
Applied to the D input of 5.

D-type FF1-5 is basic clock f _M applied to CK input
The state of the D input is sampled by and the state is output to the Q output. The output is an inverted output of the Q output.
When the Q output of the D type FF1-5 is applied to the other input of the AND gate 1-7 in which the basic clock f _M is applied to one input and the Q output of the D type FF1-5 is H, The basic clock f _M is input to the UP input of the up / down counter 1-9 via the AND gate 1-7. Therefore, the up / down counter 1-9 is the D type when the Q output of the head touch window flag latch 14 is H, the window is standing, and
When the Q output of FF1-5 is H, the basic clock f _M is up-counted.

When the Q output of D type FF1-5 is L, that is, when the level of the RF signal is within ± V and it is judged that there is no signal,
The output goes high. In this state, when any of Q _{A to} Q _D of the up / down counter 1-9 is H, that is, when the counter is not 0, the basic clock f _M is applied to the DOWN input through the AND gate 1-8, The up / down counter 1-9 performs a down count operation. When the contents of the counter are 0 and all the outputs of Q _{A to} Q _D are L by this down count or reset, the outputs of OR gates 1-10 are L and AND gate 1
Since −8 is closed, the basic clock f _M is not supplied to the DOWN input.

When a carry occurs due to the up-counting of the up-down counter 1-9 and the CY output becomes H, the D-type FF 1-11 stores the state of the D input by this rising. D input is H
Therefore, the Q output becomes H.

FIGS. 6 (a) to 6 (j) are timing charts showing waveforms of respective parts of the head touch detection circuit shown in FIG. 5 when the RF signal shown in FIG. 6 (a) is input.

The RF signal continuously has an amplitude larger than ± V in the signaled state, and almost no amplitude larger than ± V in the signalless state, that is, when the head is not in contact with the tape. In addition, ± V is set to a value that can clearly distinguish the signal and the noise.

In response to the RF signal input as shown in (a), the output of the comparator 1-1 has a waveform as shown in (b), and the output of the comparator 1-2 has a waveform as shown in (c). Appears. And in the output of OR gate 1-3,
A waveform as shown in (d) which is the logical sum of the waveforms of (b) and (c) appears. As is clear from the waveform of (d), there are gate leaks in the outputs of the gates 1-3. This gate leakage is removed by the integration circuit, and D type FF1-
A signal having a waveform as shown in (e) is input to the input of 5.

As a result, a waveform as shown in (f) appears in the Q output of the D-type FF1-5, and the AND gate 1-7 while the Q output is H.
When the basic clock f _M passes through, the signal shown in (g) appears at the output of the AND gates 1-7.
On the other hand, a signal as shown in (h) appears at the output of the AND gate 1-8.

It should be noted that noise components slightly exceeding ± V and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears in a single shot, it cannot be removed by the integrating circuit.

Signals (g) and (h) are up / down counters 1-9
Applied to the UP input and the DOWN input, respectively. When the up / down counter 1-9 counts a predetermined number (i)
The carry as shown in FIG. 11 is sent to the CY output, and in response to this, the D type FF 1-11 stores the D input, and the Q output rises as shown in (j).

As described above, the small noise and the gate leakage are integrated by the integrating circuit, and the large noise is up-down counter 1-
It is removed by the management of the time width by 9, and it is surely judged whether the signal is actually reproduced by the contact between the tape and the head or the signal is not reproduced by the non-contact. That is, the head touch is detected.

FIG. 7 shows a specific configuration example of the sync detection circuit 202.

An RF signal, HSWP (A /) signal, basic clock f _M , ATF window set signal, ATF window clear signal, noise signal and enable clear signal are input to the sync detection circuit 202.

ATF supplied with RF signal from playback amplifier 15 (Fig. 1)
Equalizer 2-1 is ATF sync signal band 400KHz ~ 900KH
It emphasizes z and outputs it to the limiter 2-2. Limiter 2-
2 is set to H when the amplitude of the signal is larger than the specified level, and is set to L when the amplitude is smaller than the specified level to convert the RF signal into a digital signal.

The output of the limiter 2-2 is supplied to the D input of the D-type FF2-3 in which the basic clock f _M is input to the CK input and also to one input of the exclusive (E) OR gate 2-4. . The Q output of the D-type FF2-3 is supplied to the other input of the EOR gate 2-4, and the EOR gate 2-4 and the D-type FF2-3 form a phase inversion detection circuit.

As for the ATF window set signal, the ATF window clear signal is input to the R input.
The ATF window signal is supplied from the Q output of the ATF window latch 2-5.

The output of the EOR gate 2-4 is the basic clock f _{M at} the CK input and the ATF from the ATF window latch 2-5 at the R input.
The window signal is supplied to the D input of the 11-stage shift register 2-6 to which each is input. 11-stage shift register 2
The Q ₁ output of −6 is sent to the AND gates 2-8 and 2-9 via the inverter 2-7, and the Q _{2 to} Q ₅ outputs are sent to the AND gates 2-8 and 2-9, and the Q _{6 to} Q ₈ outputs. Output is NOR gate 2-
The outputs of Q _{9 to} Q ₁₁ are supplied to the NOR gate and the outputs of the NOR gates 2-10 and 2-11 are supplied to the AND gates 2-8 and 2-9, respectively. The inputs of the AND gates 2-8 and 2-9 are supplied with the HSWP (A /) signal before and after being inverted by the inverter 2-12. The outputs of the AND gates 2-8 and 2-9 are supplied to the input of the OR gate 2-13.

The output of the OR gate 2-13 is supplied to the D input of the 29-stage shift register 2-14 whose basic clock f _M is input to the CK input. The Q ₁ output of the 29-stage shift register 2-14 is an AND gate
2-15 to 2-20 input, H when sync 2 Q _{6 to} Q ₈ outputs become OR gate 2-21 input, and sync 1 becomes H
Q _{9 to} Q ₁₁ outputs are to the input of OR gate 2-22, and become H at the time of sink 2. Q _{12 to} Q ₁₄ outputs are to the input of OR gate 2-23, and become to be H at both sink 1 and sink Q _18. ~ Q ₂₀ output goes to the input of OR gate 2-24 and goes high when sync 1
The Q _{27 to} Q ₂₉ outputs are supplied to the inputs of OR gate 2-25, respectively.

The output of OR gate 2-21 is the input of AND gates 2-16 and 2-18 and the input of OR gate 2-26, and the output of OR gate 2-22 is the input of AND gates 2-15 and 2-17 and OR gate 2-27. OR gate 2-23 output is AND gate
The inputs of 2-16 and 2-18 and the input of OR gate 2-26, the output of OR gate 2-24 to the inputs of AND gates 2-15 to 2-18 and the input of OR gate 2-27, and OR gate 2-25 The output of each is supplied to the input of AND gate 2-15. The output of OR gates 2-26 and 2-27 is AND gate 2-20.
And 2-19 inputs respectively.

The above-mentioned AND gates 2-15, 2-17 and 2-19 have HSWP (A /
) Signal is supplied to the AND gates 2-16, 2-18 and 2-20 by the HSWP (A /) signal inverted by the inverter 2-12. Further, the AND gates 2-15 and 2-16 are supplied with the noise signal, and the AND gates 2-17 and 2-18 are supplied with the noise signal inverted by the inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are OR gates 2-
28 ', and the output of OR gate-28 is AND gate
It is output as a detection pulse signal via 2-29. on the other hand,
The outputs of the AND gates 2-15 to 2-18 are supplied to the OR gate 2-30, the output of the OR gate 2-30 is output as the sampling signal SP1 via the AND gate 2-31, and R
It is supplied to the S input of the ATF enable latch 2-32 to which the enable clear signal is supplied. The Q output of the ATF enable latch 2-32 is output as an enable signal and is also supplied to the input of the AND gate 2-29. The output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control the opening and closing thereof.

With the above configuration, the sync detection circuit 202 operates as follows.

The limiter 2-2 outputs the digital signals corresponding to the sync 1 and sync 2 for the ATF in the RF signal, and the output of the EOR gate 2-4 becomes 1 in response to the phase inversion of the digital signal.
It becomes L for the clock. The output of this EOR gate 2-4 is D
The shift register 2-6 applied to the input responds to the rise of the basic clock f _M applied to the CK input when the window signal from the ATF window latch 2-5 applied to the R input is H. It takes in the D input, sends it to the Q ₁ output, and then sequentially shifts at each rising edge of the basic clock f _M ,
Send to Q _{2 to} Q ₁₁ outputs. That is, the shift register 2
-6 delays the output of the EOR gate 2-4 by 1 to 11 clocks and sends it to the Q _{1 to} Q ₁₁ outputs.

When the output of Q ₁ is L, that is, when there is a change, this is transmitted through the inverter 2-7 to the AND gates 2-8 and 2
When it is applied to −9 and any one of the outputs of Q _{6 to} Q ₈ becomes L, it becomes 1 of AND gate 2-8 via NAND gate 2-10.
Set two inputs to H. For Q ₂ to Q ₅ output is H when there is no change. At this time, when the HSWP (A /) signal is L, H is applied to the input of the AND gate 2-8 via the inverter 2-12.

In such a state, all inputs of the AND gate 2-8 become H and outputs become H. Therefore, when this condition is not satisfied, the output remains L, does not change in at least 4 clocks, changes in 5 to 7 clock periods, and HSWP (A /
) When the signal is L and the reproduction by the B head 1B is being performed, 1/2 cycle of the sync 2 signal is detected. Actually, since it is the sync 2 signal f ₃ (= 784 KHz, f _M / 12), the length that does not change is 6 clocks, but there is a margin of ± 1 clock due to clock timing, jitter, etc. It has.

1/2 of sync 2 signal from the output of AND gate 2-8
A pulse having a 1-clock period L in each cycle is output.
Also, from the output of the AND gate 2-9, the sync 1 signal f ₂ (= 520KHz, f _M / 18) is processed by the same process as the sync 2 and HSW.
The P (A /) signal is H, that is, detected when the A head 1A is reproducing, and is output from the AND gate 2-9. Note that the period without change is 7 clocks, and 8 to 10
Changes occur between clocks.

The sync 2 signal is output from the AND gate 2-8 when HSWP (A /) is L, and the sync 1 signal is output from the AND gate 2-9 when the HSWP (A /) signal is H via the OR gate 2-13. , The D input of the shift register 2-14.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock, sends it to the Q ₁ output, and thereafter shifts every time the clock is applied and sends it to the Q _{2 to} Q ₂₉ outputs. That is, Q
_{The 1 to} Q ₂₉ outputs are delayed by _{1 to 29} clocks and the state of the D input is output.

If there is a change in the Q ₁ output of the shift register 2-14, Q ₁
The output goes high. Sync 2 signal (f ₃ = 780KHz, 1 / 12f _M )
In the case of, the output of the OR gate 2-21 becomes H when there is a change 1/2 cycle before with reference to the Q ₁ output. Also, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H when there is a change in 1/2 and / or one cycle. The output of the OR gate 2-26 is applied to the input of the AND gate 2-20 together with the Q ₁ output of the shift register 2-14 and the HSWP (A /) signal. That is, in the case of the sink 2, the output appears on the Q ₁ output after one clock delay after the sink 2 is detected by the AND gate 2-8, and at this time, the change of 1/2 cycle before occurs in the OR gates 2-21 and 2
When -26 and the change one cycle before are simultaneously applied to the inputs of the AND gate 2-20 via the OR gates 2-23 and 2-26 respectively, the output of the AND gate 2-20 becomes H,
Along with this, the output of the OR gate 2-28 becomes H.

The outputs of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 become H when the sink 2 is set. Therefore, when the noise signal is L, the AND gate 2-18
Becomes H, which is output as the sampling signal SP1 through the OR gate 2-30 and the AND gate 2-31, and is applied to the S input of the ATF enable latch 2-32, and the Q of the ATF enable latch 2-32. Output is H, output is L
become. The Q output is output as an enable signal and is also applied to the AND gate 2-29 so that the detection pulse signal can be output thereafter through the AND gate 2-29.

In the case of the sink 2, when the noise signal is H, the output of the AND gate 2-16 becomes H, and the same operation is performed.

On the other hand, in the case of sink 1, OR gates 2-22, 2-24 and 2
When the output of -25 becomes H and the noise signal is L,
The output of AND gate 2-17 becomes H, and the noise signal is H.
At that time, the output of the AND gate 2-15 becomes H, and the same operation as described above is performed.

That is, the sync detection determination is switched between three points and four points according to the noise signal.

8 (a) to 8 (g) are timing charts showing the waveforms of the respective parts when the sink 2 is detected, and the corresponding reference numerals are given in FIG.

9 (A) to 9 (E) are timing charts showing the waveforms of the respective parts when the sink 1 is detected, and the corresponding reference numerals are given in the drawings.

FIG. 10 shows a specific configuration example of the ATF timing generator 203.

The ATF timing generator 203 has ▲ ▼ / EVEN signal, basic clock f _M , HSWP (A /) signal, enable signal, enable clear signal, rear / The signal, the initial signal, and the detection pulse signal are input.

Enable signal at E input, basic clock f _{M at} CK input,
Then, the 0.25 block counter 3-1 to which the enable clear signal is input to the R input respectively makes the CY output H when performing the count corresponding to 9.5 μs, which is the E input of the high counter 3-2 and the decoder 3 -3 is input to each C input.

In the high counter 3-2, the basic clock f _M is input to the CK input, and the enable clear signal is input to the R input.
Count up every 0.25 block. The counter 3-
2 ^{_{Q 0 ~Q 3 (2 0 ~2}} 3) output is input to the decoder 3-3.

The decoder 3-3 is for decoding each time, and outputs 0 to 8, 16 and 17 are active only when the C input is H, and 0.25 to 2.25 block signals are output from the 0 to 8 output every 0.25 block. In addition, 4 block signals and 4.25 block signals are output from the 16 and 17 outputs, respectively.

The output of the decoder 3-3 is the gates 3-4 to 3-7,3-
While being input to 9 to 3-11, the 0.5 block signal is supplied to the R input of the latch 3-12 and the CK input of the D-type FF3-13, and 1
The block signal is supplied to the CK input of the D-type FF3-14.

HSWP (A /) signal and after / The decoder 3-15 to which each signal is input is for decoding the position of the currently reproduced ATF signal,
B-ATF-1, A-ATF-1, B-ATF-2 and A-ATF-2 signals are output to 0 to 3 outputs, and these are output to the gate 3-in addition to the gates 3-4 and 3-7. Supply to 16 and 3-17.

Table 3-18, to which the HSWP (A /) signal and initial signal are input, holds the sync detection threshold value, and the threshold value that is held is switched by the HSWP (A /) signal and the initial signal to synchronize. Set it in the detection counter 3-19. The HSWP (A /) signal sets the respective values for sync 1 during A head reproduction and sync 2 during B head reproduction, and each value is 50% of the number of continuous sync patterns. However, when the initial signal is L, it is set to 60% of the number when the sync 2 is continuous. The sync detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 has a gate 3-20.
It has 3-15, 3-27 and inverters 3-28-3-30.

Then, the output of the gate 3-10 is the sample signal SP2, the output of the gate 3-26 is the false detection signal, the output of the gate 3-4 is the sample signal SP3A, the output of the gate 3-27 is the ATFEND signal, and the gate 3-7. The sample signal SP3B is output to each of the outputs.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SP1, the 0.25 block counter 3-1 starts counting in response to the enable signal which becomes H due to the fall of the sampling signal SP1, and the CY output thereof becomes H every 0.25 block. Becomes The decoder 3-3 decodes the state of the high counter 3-2, and the CY output of the 0.25 block counter 3-1 is H level.
The output becomes H only when.

When 1 output of the decoder 3-3 becomes H, 0.5
As post-block processing, this is applied to the L input of the sync detection counter 3-19 via the OR gate 3-11, and also to the R input of the latch 3-12 and the CK input of the D-type FF 3-13. .

Since the CY output of the sync detection counter 3-19 is input to the D input of the D type FF3-13 via the latch 3-12, 0.5
After the block, the D-type FF 3-13 samples whether or not there is a detection pulse signal whose value is equal to or larger than the specified value. At the same time, the latch 3-12 is reset and the threshold value from the table 3-18 is set again in the sync detection counter 3-19.

When the three outputs of the decoder 3-3 are H, the processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF3-14 which is applied to the D input via the latch 3-12. It is sampled whether or not there is a detection pulse having a specified value after one block.

The combination circuit of gates 3-20, 3-21, 3-23 and 3-30 is ▲
▼ Determine whether or not there is a specified detection pulse signal based on the / EVEN signal. In the case of ODD, D type FF3-13,3-
The Q outputs of 14 are both H, and in the case of EVEN, when the Q output of the D-type FF 3-13 is H, the output of the OR gate 3-25 becomes H even if there is a specified detection pulse signal.

In the same process, if the initial signal is H,
OR gate via inverter 3-29 and AND gate 3-22
The output of 3-25 becomes H.

When the sync detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore, when the four outputs of the decoder 3-3 are H, that is, after 1.25 blocks, when the specified number of detection pulse signals are not detected, an erroneous detection of being H through the inverter 3-28 and the AND gate 3-9. The signal is output.

When the 7 output of the decoder 3-3 is H, that is, after two blocks, the output of the AND gate 3-10 is used to sample other adjacent tracks due to the presence of the specified detection pulse signal and the OK signal. Outputs sampling signal SP2.

Further, when reproduced by the A head, 3 outputs of the decoder 3-15 are H and 16 outputs of the decoder 3-3 are H 4.
After the block, the sampling signal SP3A is outputted when the output of the decoder 3-15 is H and the output of 16 of the decoder is H during reproduction by the B head, and SP3B is outputted to sample the on-track level.

Furthermore, when 17 outputs of the decoder 3-3 are H, A head is ATF-2, and B head is ATF-1, gates 3-17, 3−
The ATFEND signal is output via 5 and 3-27. And
When 8 outputs of the decoder 3-3 become H when A head is ATF-1 or B head is ATF-2, gates 3-16, 3-6 and 3-27
The ATFEND signal is output via.

FIGS. 11 (a) to 11 (k) are timing charts showing the waveforms of the respective parts associated with the above operation, and the corresponding reference numerals are given to the respective parts.

It should be noted that in the above-described embodiment, only the operation of the ATF signal processing unit is controlled on the basis of the head portion of the reproduction signal.
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as PCM and SUB-2.

〔effect〕

As described above, according to the present invention, the detection of the sync signal is stopped when the level of the pilot signal frequency component in the output signal of each rotary head does not have a predetermined relationship with the level of the sampled on-track pilot signal. Therefore, the on-track pilot signal is erroneously detected by the remaining sync signal and the capstan servo is not controlled, and the capstan servo is prevented from being disturbed. In particular, due to the relationship of the level of the pilot signal frequency component in the output signal of each rotary head with respect to the level of the on-track pilot signal, that is, the mutual relationship of the signal levels recorded on the same recording medium, Since it is judged whether or not it is a thing, even if there is some variation in the recording level of the pilot signal, there is almost no erroneous judgment.

[Brief description of drawings]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, and FIG. 2 is a block diagram showing the essential parts of the present invention.
3 and 4 are timing charts showing signal waveforms of respective parts in FIG. 2, FIG. 5 is a circuit diagram showing a specific configuration of a part of FIG. 2, and FIG. 6 is FIG. 7 is a timing chart showing the signal waveform of each part of FIG. 7, FIG. 7 is a block diagram showing the concrete structure of the other part in FIG. 2, and FIGS. 8 and 9 are the signal waveforms of each part in FIG. FIG. 10 shows a timing chart, FIG. 10 is a circuit diagram showing a concrete structure of still another part of FIG. 2, FIG. 11 is a timing chart showing signal waveforms of respective parts in FIG. 10, and FIG. FIG. 13 shows the R-DAT track format and block format, FIG. 13 shows the R-DAT ATF track pattern, and FIG.
FIG. 14 is a diagram for explaining the principle of tracking control by the track pattern of FIG. 13. 1A, 1B ... rotary head, 103, 104, 105a, 105b ... sample and hold circuit, 107 ... comparator, 108 ... differential amplifier, 202 ... sink detection circuit, 217, 218 ... OR gate,
219 ... Inverter, 2-5 ... ATF window flag latch.

Claims (1)

(57) [Claims] 1. A plurality of signals including a tracking pilot signal composed of a digital signal and a frequency signal having a small azimuth effect and a sync signal are provided in each of a plurality of diagonal tracks with independent recording areas in the longitudinal direction of each track. On a recording medium, which is recorded in a predetermined format and in which the positions of the pilot signals recorded in three consecutive tracks are different from each other and a sync signal is recorded in a position corresponding to one adjacent track. Of at least two rotary heads for reproducing the plurality of signals, the width of each rotary head is made wider than the width of each track,
By reproducing each track, the crosstalk between the pilot signal of the on-track and the pilot signal of both adjacent tracks is obtained at the output of each rotary head, and the capstan servo is controlled by the level difference of the crosstalk between the pilot signals of both adjacent tracks. , Each rotary head scans each track, and a sync signal detecting means for detecting the sync signal, and a pilot signal from the output signals of the rotary head in response to the detection of the sync signal by the sync detecting means. First holding means for sampling and holding the level of the frequency component, and the output signal of each rotary head after a certain time has passed since the level held by the first holding means and the sync signal detected by the sync detecting means. Means for determining the level difference from the level of the frequency component of the pilot signal in the Second holding means for sampling the difference and holding it for control of the capstan servo, third holding means for sampling and holding the level of the on-track pilot signal, and level held by the third holding means And a determination means for determining whether or not the levels of the pilot signal frequency components in the output signals of the respective rotary heads have a predetermined relationship and are due to the pilot signals of both adjacent tracks. The digital signal reproducing device is characterized in that, when it is determined that the signal is not based on the pilot signals of both adjacent tracks because of no predetermined relationship, the detection of the sync signal by the signal detection circuit is prohibited.