JPS6325861A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To attain normally a tracking control by prohibiting the detecting of a sink signal when the level of the pilot signal frequency component in the output signal of respective rotating heads is not the prescribed relation to the level of the pilot signal of an on-track. CONSTITUTION:A sample holding S/H circuit 103 sample-holds the DC level of the pilot signal on one adjoining track by the timing of a sampling signal SP1 from a sink detecting circuit 202. An S/H circuit 105a supplies the DC level of an on track pilot signal during the reproduction of the A track of a +azimuth to the control input of a level adjusting circuit 109 and supplies it to one side input of a comparator 107. For the comparator 107, when the 1/2 of the level inputted through a switch SW2 is smaller than the input from an envelope detecting device 102, the output comes to be H, and an ATF window off signal is supplied through or gates 217 and 218 to the sink detecting circuit 202.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, and reproduces the digital signal recorded by a rotating head as one diagonal track on a recording medium for each unit of time. This invention relates to a digital signal reproducing device suitable for.

[Technical background of the invention and its problems]

A device that records audio signals on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotary head, and when reproducing the audio signals, converts the audio signals into PCM and records and reproduces them. There is a digital signal recording and reproducing device called DAT (rotating head digital audio tape recorder), which is considered as a digital audio tape recorder.

The format of the track actually recorded in R-DAT is the pattern shown in Fig. 12(a), and the frequency of each of MARGIN, PLL, and PO3 TAMBLE is 1/2 r, (fM = 9.4 MHz
), the frequency of I B G is 1/6 rH. S
The UB and PCM are composed of blocks as shown in FIG. 12(b). 5YNC is fixed at 9 bits, and the remaining bits have various patterns depending on the location, audio signal, etc. In the case of SUB, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 12 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas (ATF:
(8 automatic Track Finding)
The purpose of the present invention is to enable tracking control so that the rotary head correctly scans the recording track during reproduction using the output of the rotary head without providing a special head.

In other words, the PF A T F jJ area is the area where the beginning and end of each track is recorded when compressing the time axis of the PCM signal and forming tracks diagonally on a magnetic tape using two rotating heads without a guard band. A tracking pilot signal is recorded in a separate recording area from the PCM signal in the part, and during playback, the recording track is scanned by a rotating head whose scanning width is wider than the track width, and the rotating head tracks the track being scanned. The reproduced output of pilot signals from both adjacent tracks is used to control the tracking of the rotary head.

Then, the track pattern for this ATF is the first one.
As shown in Figure 3, the pattern shown is a drum diameter of 30 mm, a drum winding angle of 90°, and a rotation speed of 2.
The case of 000 rpm will be explained.

ATFl and A in the front and rear parts of each track
TF2 is a low frequency signal f with little azimuth effect as a pilot signal for tracking.

This is used to detect the level of crosstalk from both adjacent tracks during playback, and to obtain the level difference between the crosstalk components of both adjacent tracks as a tracking error signal. A low frequency signal of /72 (130 KHz) is used as the pilot signal f.

Furthermore, a sync signal for determining the position where the pilot signal f is recorded is recorded in ATFI and ATF2. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. Assuming that the head corresponding to +azimuth is A and the head corresponding to -azimuth is B, the sync signal is different from each other to distinguish between A head and B head, and the frequency for A head is different. r, /18 (=522KHz) sink 1 signal f2
However, for the B head, the frequency f, 4/12 (=7
The sync 2 signal f3 (84 KHz) is recorded at each predetermined position.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. Therefore, the frequency fs /6 (=1.56MHz) is set at a predetermined position to erase the pilot signal fl, sync 1 signal ft, and sync 2 signal f3 of the previous recording.
An erasure signal f, is recorded.

The positions of the ATF pilot signals are all different between the on-track and both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Five blocks are allocated to each ATF area of ATF 1 and ATF2, and the pilot signal f1 is recorded in two of the blocks. Sink signal f2, r,
is recorded using one block or 0.5 block from the vertical center where one adjacent track is recorded. The pilot signal f1 of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. A sync signal of 1 pro/ri is assigned to an odd numbered frame, and a sync signal of 0.5 block is assigned to an even numbered frame.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, when a magnetic tape recorded in the format shown in FIG. 12(a) is reproduced by a rotary head, an RF multiplied signal as shown in FIG. 14(al) is obtained from the rotary head.This RF multiplied signal For example, if the pilot signal f is obtained by reproducing the odd-numbered frame track (A) in FIG. 13, the pilot signal f as shown in (bl) is
, is obtained.

Section T is due to on-track pilot signals, and sections ■ and ■ are due to crosstalk between pilot signals of (B) odd frame tracks and (B) even frame tracks. When the rotating head is correctly scanning on-track, the envelope levels of sections ■ and ■, that is, ■■ and ■■ of (C1) should be equal, but if there is a track deviation, ■■≠■■ Then,
The amount and direction of deviation of the rotary head from on-track can be determined by its magnitude and polarity. Therefore, depending on the difference between ■■ and ■■, the capstan servo is operated to adjust the tape speed to HfF.
By aligning the four positions, the rotary head can be run on-track.

In order to perform the above-described operation, it is necessary to accurately detect the sync signal at a predetermined position and sample the levels (1) and (2). However, as mentioned above, R-DAT does not have an erase head, and due to override,
Since recording is being performed for the third time, it may not be possible to accurately detect the sync signal, sample ■ and ■, and generate a correct error signal.

That is, in R-DAT, recording can be performed within ±22 blocks from the center of the PCM area. Further, the recording level of the pilot signal fl (=130 KHz) is to be slightly lower than the level of other signals. This is because low frequency signals are recorded at a deep level on the tape, and the previously recorded pilot signal f can be erased by the erase signal at the time of override. However, if the level of the pilot signal f is lowered in this way, the pilot signal r will appear at the previously recorded sync signal f2 or f.
When a new sync signal is recorded, the previous sync signal may not be completely erased and may remain.

Specifically, when a later recording is performed ahead of the previous recording, the sync signal of the later recording always precedes the unerased sync signal of the previous recording on the track. Although this is not a problem, if the later recording is shifted backward, the unerased sync signal will precede the sync signal of the later recording. An example of this is when there is a deviation of 1 to 2 blocks later, and the AT
For F-1, the sync signal f2f of the previous recording is added to the pilot signal f in (A) even frames and (A) odd frames, and for ATF-2, the pilot signal f is in (B) even frames and (B) odd frames. Part or all of it will remain.

When this happens, the level of the frequency component of the pilot signal in the reproduced RF signal at that time is sampled according to the sync signal of the previous recording. Although this pilot signal should originally be at the crosstalk level of the sampling signal of one adjacent track, the sampled frequency component is the on-track pilot signal itself, and the level obtained by this sampling is an extremely large value. becomes. After that, the frequency component of the pilot signal in the reproduced RF signal two blocks later is sampled, the difference between this sampling value and the sample value two blocks before is taken, and this level difference is used as the amount of track deviation to control the capstan servo. However, since what is sampled first is the on-track level, not the crosstalk level of the adjacent track, a very large level difference that is far from the actual track shift amount is obtained. If this happens, the capstan servo will be disturbed and the tape running will be adversely affected.

[Purpose of the invention]

The present invention solves the above-mentioned problems, and makes it possible to perform tracking control normally without malfunctioning even if the sync signal of the previous recording remains erased at a position preceding the sync signal of the subsequent recording due to override. It is an object of the present invention to provide a digital signal reproducing device that achieves the following.

[Summary of the invention]

The present invention has been made to achieve the above-mentioned object, and the level of the pilot signal frequency component in the output signal of each rotary head is in a predetermined relationship with the level of the on-track pilot signal sampled and held. By prohibiting the detection of the sync signal when there is no sync signal, and preventing erroneous capstan servo control from occurring due to the level difference between the on-track pilot signal level and the level after a certain period of time due to erroneous detection of the sync signal. Prevents disturbance of the capstan servo.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, 1 is a rotating drum with a diameter of 30φ, and the rotating drum 1 has two rotating heads, 180@ The A head IA is spaced apart from each other.
Two pulse generators (PG) PGA and PCB are arranged at intermediate positions between the 8 heads IB and 8 heads IB.

2 is a crystal oscillator that generates a basic clock fM of 9.4 MHz, and the basic clock f is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system, outputs a PB/REC switching signal, and performs switching control of the toggle switch 4 consisting of switches SW1 and SW2.

5 is a reference signal generator, which generates XHz (66Hz: 2PG
), YHz (depending on the number of FCs of the capstan motor) and ZHz reference signals are generated.

Reference numeral 6 denotes a drum servo, which servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on a reference signal ZHz under the control of the system controller 3. 8 is a capstan servo, which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when switch 4 is switched to the B contact side by the system controller 3, and switch 4 is switched to the A contact side. During playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is a HSWP (A/100) signal generator, and drum 1
HSWP switching between A head IA and 867118 based on pulses from the top two PGs (A/100)
A signal is generated, and the HSWP (A/100) signal becomes H at 1 o'clock for A and 1 o'clock for B hen, which are also supplied to each part of the system.

Reference numeral 10 denotes a phase reversal detection circuit, to which the basic clock f applied to the CK input and the HSWP (A/100) signal are input, and the output is supplied to the S input of the initial flag latch 11. The CY output of the initial counter 12 is input to the R input of the initial flag latch 11, and the Q
The output is supplied to the R input of the initial counter 12.

The initial counter 12 is set with a threshold value from a table 13 under the control of the PB/REC signal from the system controller 3, and the CY output becomes H by counting the set value. The CY output is applied via the inverter 13a.
It is input to the encode data processing unit 18 via the AND gate 13b which is opened and closed by the /REC signal, and is also supplied to the S input of the head touch window flag latch 14 via the AND gate 13c which is opened and closed by the PB/REC signal. There is.

The head touch window flange launch 14 is for generating a window that prohibits the head touch detection operation during the noise period when switching the head. A clear signal is input from the processing section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, HSWP (A/
100) Encode data processing unit 18 (described later) based on the signal
The data to be recorded is supplied to the rotary hoods IA and IB via the switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
Data is extracted from the F signal, subjected to 1078 conversion (demodulation), deinterleaving, error correction, etc., and then sent to the D/A converter. In addition, head touch detection, ATF sync detection, tracking error detection, etc. are performed to detect track deviation. An error signal is supplied from the signal generator 17a to the capstan servo 8.

The encoded data processing unit 18 performs interleaving, parity addition, 8/10 conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above configuration, P from the system controller 3
A recording operation is performed when the B/REC signal is L.

Since the PB/REC signal is L, switch 4 is set to b.
The capstan servo 8 is switched to the contact side, a reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied based on the reference signal YHz, and tracking is controlled.

The HSWP (A/B) signal output by the HSWP (A/B) generator 9 based on the pulses generated by PGA and PGB due to the rotation of drum I is H, B when head A is IA.
It becomes L when the head is IB. This HSWP (A/100) signal is input to the phase reversal detection circuit 1o, and the HSWP (A/100) signal is input to the phase inversion detection circuit 1o.
/B) When the signal level changes, that is, when it is detected that the head has switched, the phase reversal detection circuit 10
The output becomes H for one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial Fran latch 11 is set and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic crosshairs f in a fixed period corresponding to 3.75 ms according to the set value from the table 13, its CY output rises, and this causes the initial frang latch to start. 11
is reset, and the rising edge of the CY output is applied to the encode data processing section 18 as a recording start signal. Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined format.

Next, when the P B/REτ multiplied signal from the system controller 3 is be done.

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The amount of track deviation is an ATF error signal that corresponds to the level difference in the amplitude of crosstalk between pilot signals of both adjacent tracks, and the details will be described later.

H3WP (A/100) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 becomes a playback mode counter by direct access from the table 13), and the count value is, for example, 100 μs.
/ 1 m s, the CY output becomes H.
becomes. This prohibits the head touch operation, which will be described later, while noise occurs when the head is switched, and sets the head touch window flag latch 14 via the AND gate 13 after the above-mentioned certain period of time, and outputs its Q output. This is to set it to H and output an on signal for head touch detection. The on signal from the head touch window flag latch 14 is sent to 7 in the decode data processing section 17.
When a contact, that is, contact between the tape T and the head IA or IB to output an RF multiplied signal is detected, the head touch window flag graph 14 is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproducing amplifier 15, a band pass filter (BPF) 101, and an envelope detector 102.
, the first sample hold (S/H) circuit 103, the 23rd
/H circuit 104, third S/H circuits 105a and 105
b, toggle switch 106, comparator 107, differential amplifier 108, level correction circuit 109, and resistor R7
It consists of ~R4.

On the other hand, the digital system includes a crystal oscillator 2, a head touch detection circuit 201, a sync detection circuit 202, an ATF timing generator 203, a regeneration flag latch 204, a system counter 205, a timing generator 206, a 1/2 frequency divider 207, and an ATF initial flag. latch 208,
It consists of a power-on reset circuit 209, a launch circuit 210, a protection counter 211, a noise error flag latch 212, a latch 213, an erroneous detection counter 214, a sampling counter 215, OR gates 216 to 218, and an inverter 219.

First, to explain the analog system, an RF multiplied signal is input from the rotary heads IA and IB (Fig. 1) to the input of the reproduction amplifier 15, and its output is input to each of the BPF 101, the head touch detection circuit 215, and the sync detection circuit 216. is supplied to.

The BPF 101 passes only the 130 KHz component of the RF multiplied signal and inputs it to the envelope detector 102 . Envelope detector 102 performs envelope detection on the 130KHz component and sends it to S/H circuits 103, 105a, 10.
5b and the differential amplifier 108.

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SP1 applied to the C input from the sync detection circuit 202, and supplies this to one input of the comparator 107 and the output of the differential amplifier 108. Apply each. #'i S/H circuit 10
What is sampled and held by 3 is the DC level of the crosstalk of the pilot signal of one adjacent track.

The S/H circuit 104 receives a signal level-adjusted by the level adjustment circuit 109 at its input, samples and holds this signal using the sampling signal SP2 from the ATF timing generator 203, and outputs the ATF signal to the capstan servo 8 (Fig. 1). Supplied as an error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The S/H circuit 105a samples and holds the output from the envelope detector 102 using the sampling signal 5P3A from the ATF timing generator 203, and outputs this to one end of the resistor R3 and the a contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105a samples and holds is the D of the on-track pilot signal when A track is played back.
It is C level.

The S/H circuit 105b samples and holds the output from the envelope detector 102 using the sampling signal 5P3B from the ATF timing generator 203, and outputs this to one end of the resistor R3 and the b contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105b samples and holds is the D on-track pilot signal when B track is played back.
It is C level.

The resistors R1 to R4 have the same value, and the S/H circuits 105a and 105a are added to one end of the resistor R1 and R1, respectively.
This is for dividing the output of 5b. The interconnection points of the resistors R and R2 and the interconnection points of the resistors R1 and R4 are respectively connected to the a contact and the b contact of the switch SW2 of the toggle switch 106, and each interconnection point is connected to each S/H circuit. A level of 1/2 of the sample hold value is obtained.

The toggle switch 106 is controlled by the H3WP (A/100) signal, and when the H3WP (A/100) signal is H, the a
side, and when it is L, it is switched to the b side.

The comparator 107 has one input connected to the S/H circuit 105a.
and 1/2 level of the output of 105b is connected to resistors R3 to R4.
and is applied via the switch SW2, and the output of the envelope detector 102 is applied to the other input. When 1/2 of the sample and hold values of the S/H circuits 105a and 105b is smaller than the output level of the envelope detector 102, the output of the comparator 107 becomes H, which is supplied to the input of the OR gate 217 and also
19 to the input of OR gate 218.

The differential amplifier 108 separates the output of the envelope detector 102, which is applied to the input power, and the S/D output, which is applied to the input power.
The difference between the output of the H circuit 103 and the output of the H circuit 103 is taken and inputted to the level adjustment circuit 109. That is, envelope detector 1
The output of 02 is the DC of Kukostalk of the other adjacent track.
When outputting the level, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

The level adjustment circuit 109 is the S/H circuit 105a and 105
For example, the amplification degree is changed in inverse proportion to the output level of b,
By adjusting the signal level from the differential amplifier 108, variations in the outputs of the rotary heads LA and IB are corrected.

Next, to explain the digital system, the head touch detection circuit 201 is connected to the hand touch window flag latch 1.
4 (Figure 1) and the basic clock f, detects that the RF multiplied signal is input, and supplies the signal to the S input of the regeneration flag latch 204, details of which will be described later. .

The sink detection circuit 202 receives the RF multiplied signal H3WP (A/100) signal, the ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise-y signal from the noise-if flag latch 212, and the crystal oscillator 2. The basic clock f i and the enable clear signal from the OR gate 216 are input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to the output. The sampling signal SPI is connected to the C input of the S/H circuit 103 and the latch 210.
The enable signal and detection pulse signal are connected to the R input of the A
Each is input to the TF timing generation circuit 203.

The sync detection circuit 202 converts the RF multiplied signal into a digital signal, detects the beginning of the ATF sync patterns SYl and SY2 of the rotary heads IA and IB, outputs a sampling signal SPI, and then outputs a sampling signal SPI to the continuously detected sync patterns. It operates to output a detection pulse signal to the target, and the details will be described later.

The ATF timing circuit 203 receives an ODD/EVEN signal which is the Q output of the 1/2 frequency divider 207, an initial signal which is the Q output of the ATF initial flag latch 20B,
Enable signal and detection pulse signal from sync detection circuit 202, after/W from timing generator 206
signal, enable clear signal from OR gate 216;
and the basic clock f, 4 from the crystal oscillator 2 are input, and the sampling signal SP2.5P3A is output.

Sends a 5P3BS erroneous detection signal and an ATFEND signal. The sampling signal SP2 is connected to the C input of the S/H circuit 104 and the S input of the ATF initial flag latch 208, and the sampling signal 5P3A is connected to the C input of the S/H circuit 105a.
Input, sampling signal 5P3B is S/H circuit 105b
The false detection signal is sent to the C input of the latch 210, one input of the OR gate 216, and the C input of the false detection counter 214.
K large input, ATFEND signal is OR gate 216 and 2
170 Each person is powered by one person.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer counter (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and performs a specified If the detected pulse exceeds the specified value by the time, the sampling signal SP2
．． It outputs 5P3A and 5P3B, and operates to output an erroneous detection signal when it is below a specified value or at the L level of the OK multiplied signal which is the output of the comparator 107, and the details will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of channel bit data of the R-DAT, and outputs a basic clock fM. The basic clock f9 is applied to the CK large input of the head touch detection circuit 201, the sync detection circuit 202, the ATF timing generator 203, the system counter 205, and the protection counter 211, respectively.

The latches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes L in response to the rising edge of the S input and the Q output becomes L in response to the rising edge of the HSR input.

The output of the head touch detection circuit 201 is input to the S input of the playback flag latch 204, the END signal which is the output of the timing generator 206 is input to the R input, and the Q output thereof is input to the R input of the system counter 205. When the Q output of the regeneration flag latch 204 is H, the regeneration operation is in progress.

The system counter 205 receives the Q output of the regenerated frang latch 204 and the CK large input basic clock f at its R input, and outputs Q0 to Q thereof are input manually to the timing generator 206.

This system counter 205 is for roughly indicating the position on the track where each signal is recorded.

Timing generator 206 generates at its output an ATF window cent signal (via OR gate 218), an after/penalty signal, a window clear signal, and an END signal based on the QI"-Qx output from the system counter, and Window set signal sync detection circuit 2
02, the after/enable signal is supplied to the ATF timing generator 203, the window clear signal is supplied to the OR gate 217, and the END signal is supplied to the R input of the regeneration flag latch 204. This timing generator 206 decodes the output of the system counter 205 and generates the timing required for each part.

1/2 frequency divider 207 is H3WP applied to CK power.
(A/100) Divide the signal by 1/2 and send ODD/EV to Q output
Generates an EN signal and sends it to the ATF timing generator 20
Supply to 3. The Q output of the ATF initial flag latch 208 is input to the 8 inputs of the 1/2 frequency divider.

ATF initial flag latch 208 connects AT to S input.
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. The ATF initial flag launch 208 is ATF
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The latch 210 connects the ATF timing generator 203 to the S input.
The sampling signal SPI from the sync detection circuit 202 is input to the R input, and the Q output is input to the R input of the protection counter 211. When the launch 210 is erroneously detected, the Q output becomes H, and is reset in response to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain period of time from erroneous detection, and only when the R input is H, it counts the basic clock fPI to which the CK large input is applied.
Cleared by input.

The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise flag latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The latch 212 receives the Q output of the latch 213 and the CY output of the large CK input sampling counter 215 at its D input, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

In the latch 213, the CY output of the false detection counter 214 is input to the S input, the CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise error flag latch 212.

The false detection counter 214 receives the false detection signal from the large CK input ATF timing generator 203 and the CY output of the sampling counter 215 at its R input, and the CY output is supplied to the S input of the latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SPI is erroneously detected during a - period, and when the value exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives CK large input H3WP (
A/100) signal is input, and CY output is false detection counter 2.
14, the R input of the latch 213, and the CK large input of the noise error flag latch 212.

The OR gate 216 connects the false detection signal from the ATF timing generator 203 and the ATFEND signal to the protection counter 21.
CY output of 1 is input, and the sync detection circuit 2 is input to that output.
02 and an enable clear signal to the ATF timing generator 203.

The OR gate 217 receives the output signal of the comparator 107, the window clear signal from the timing generator 206, and the ATFEND from the ATF timing generator 203.
The signal and the CY output from the protection counter 211 are respectively input, and the ATF to the sink detection circuit 202 is input to the output.
Sends window off signal.

The output of the comparator 107 and the output of the timing generator 206 are input to the OR gate 218 via the inverter 219, and the ATF window set signal is sent to the output thereof.

In the above configuration, the head touch detection circuit 201 and the sync detection circuit 202 pass through the RF double signal regeneration amplifier 15.
and the BPF 101. B.P.
Only the 130 KHz component of the RF multiplied signal supplied to F 101 is passed. The amplitude level of the 130KHz component is converted to a DC level by the envelope detector 102, and then the S/H
Each input of circuit 103゜104.105a and 105b, one input of comparator 107 and differential amplifier 1
It is applied to 08's ten-man power.

The envelope detector 102 sequentially outputs the DC level of the amplitude of the crosstalk of the pilot signal of one adjacent track, the amplitude of the crosstalk of the pilot signal of the other adjacent track, and the amplitude of the pilot signal of both adjacent tracks. The DC level of the amplitude of the on-track pilot signal is output before or after the signal.

The S/H circuit 103 samples and holds the DC level of the pilot signal of one adjacent track at the timing of the sampling signal SPI from the sync detection circuit 202.

The sampled and held crosstalk level of one adjacent track is applied to the differential amplifier 108.

The S/H circuit 105a converts the DC level of the on-track pilot signal during playback of +azimuth A track to the S/H circuit 105a.
The circuit 105b samples and holds the DC level of the on-track pilot signal during the reproduction of the -azimuth B track. The output of the S/H circuit 105a, that is, the DC level of the on-track pilot signal is:
It is supplied to the control input of the level adjustment circuit 109 through the a contact of the switch SWI of the toggle switch 106, and the voltage is divided into 1/2 by the resistors R3 and Rt, and then the voltage of the comparator 107 is supplied through the a contact of the switch SW2. supplied to one input. Similarly, the output of the S/H circuit 105b is sent to the level adjustment circuit 10 through the b contact of the switch SWI.
9, and after being divided into 1/2 by resistors R3 and R4, the voltage is applied to comparator 107 via the b contact of switch SW2.
is fed to one input of

The output of the comparator 107 becomes L when 1/2 of the level input manually via the switch SW2 is greater than the input from the envelope detector 102. That is,
It is determined that the output of the envelope detector 102 is due to crosstalk of one adjacent track. In the opposite case, it is determined that the signal is an on-track pilot signal. Therefore, when the output of the comparator 107 is H, an ATF window off signal is supplied to the sync detection circuit 202 via OR gates 217 and 218 to inhibit sync detection. Then, when the output of the comparator 107 changes from H to L, this is inverted by the inverter 219, and the ATF window cent signal is outputted to the output of the OR gate 218.

When the envelope detector 102 is outputting the DC level of the Kuko talk amplitude of the other adjacent track, the differential amplifier 108 inputs the DC level of the Kuko talk amplitude of one adjacent track. The difference between the DC-levels of crosstalk between both adjacent tracks, that is, the amount of track deviation, is obtained as an output, and this is input to the level adjustment circuit 109.

The level adjustment circuit 109 is the S/H circuit 105a and 105
The output of b is applied as a control input, and when the control input is large, the level of the input signal is lowered, and when it is small, it is raised and output.

In short, the level adjustment circuit 109 automatically corrects variations in the outputs of the two rotary heads and inputs the result to the next S/H circuit 104. The S/H circuit 104 samples and holds the corrected deviation amount between both adjacent transistors using the sampling signal SP2. The output of this S/H circuit 104 is supplied to the capstan servo 8.

FIGS. 3(a) to (11) are timing charts showing signal waveforms generated in each part by the above operations in correspondence with the reference numerals assigned to each part.

The H3WP (A/100) signal shown in Figure 3 (bl) is
When reproduced by B, it becomes L. H3 when the head is switched
The phase of the WP (A/B) signal is reversed. When the phase is reversed, the Q output of the initial flag latch 11 (FIG. 1) becomes H, and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is determined that the tape has passed a noisy part, and the head touch window frang latch 1
4 (Fig. 1) to make its Q output H. When the Q output of the head touch window flag latch 14 becomes H, the head touch detection circuit 201 operates.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF multiplied signal is reproduced, its output becomes H.
, set the regeneration flag latch 204 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 outputs the ATF window cent signal to the sync detection circuit 2 based on the Q0 to Q outputs of the system counter 205 and outputs the ATF window cent signal slightly before the recorded ATF-1 and ATF-2.
Supply to 02.

The sync detection circuit 202 temporarily suspends the sync detection operation when the output of the comparator 107 becomes H after the ATF window set signal is applied, and resumes the sync detection operation when the output of the comparator 107 becomes L. In response to this sync detection operation, after converting the RF multiplied signal into a digital signal, the sync 1 (=
Each sync is detected based on the fact that the patterns of sync 2 (=fz) and sync 2 (=f3) in the case of B head IB have the relationships shown in the table below depending on the frame.

Here, when the sync detection circuit 202 detects 4 syncs in a row in the normal case or 5 syncs in the noise case, it outputs the sampling signal SP1, and sends the cross of the pilot signal f of one adjacent track to the S/H circuit 103. The talk level is sampled and held, and an enable signal is supplied to the ATF timing generator 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SPI is output from the sync detection circuit 202.
Check whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI. Next 1.2
After 5 blocks, it is determined whether the sync is detected at a specified value or more, and if it is above the specified value, it is assumed that the sync has been detected correctly and the sampling signal SP2 is sent to S/H after 2 blocks.
The signal is supplied to a circuit 104 to sample and hold the crosstalk level difference between both adjacent tracks, and its output is supplied to the capstan servo 8 as the amount of track deviation.

In addition, if the on-track pilot signal fI exists after the sync, when playing back with the A head IA, the A
Since TF-2 and B heads are being played back at ATF-1, in this case, the sampling signals 5P3A and 5P3B are output after 4 blocks, and these are supplied to the S/H circuits 105a and S/H 105b, respectively. Sample and hold the level of the on-track pilot signal being played by each head.

If the above series of operations are performed correctly, ATFEND
A signal is output, which is passed through the OR gate 216 as an enable clear signal to the sink detection circuit 202 and the AT.
It is supplied to the F timing generator 203. ATFEND
The signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. .

If the sink does not exceed the specified value, the false detection signal is set to H, the Q output of the latch 210 is set to H, and the protection counter 21
1 count operation, and false detection counter 2
14 performs +1 action.

When the false detection signal becomes H, the enable clear signal to the sink detection circuit 202 and ATF timing generator 203 via the OR gate 216 also becomes H. When the enable clear signal becomes H, the sync detection circuit 202 performs the operation of detecting the sync from the beginning again.
When the sink is detected, the sampling signal SPI is output again. - On the other hand, the ATF timing generator 203 sets the sync detection counter and timer to the initial state.

As described above, when the sync detection circuit 202 outputs the sampling signal SPI again, the touch 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the CY output of the protection counter 211 becomes H after the erroneous detection signal is output once, that is, after a specified time (2.5 blocks), the sync detection circuit 202 and the ATF timing generator are connected via the OR game 216. The enable clear signal to 203 becomes H, and the operation stops.

In addition, the sampling counter 215 is H5WP (A/B
) The rising edge of the signal increases +1, but this is managed by the length of the tape, and if the number of false detections exceeds a certain level during that period, the CY output of the false detection counter 214 becomes H, and this causes the noise flag to rise. The Q output of the latch 213 is set to H to notify the sync detection circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent large dropouts.

In addition, FIGS. 4A to 4C are timing charts showing the outline of signal waveforms of each part of the digital system after the initial French launch 11 is set during playback. Corresponding symbols are attached to FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific example of the configuration of the head touch detection circuit 201 described above.

In the figure, the comparator 1-1 has an RF multiplied signal inputted to one input, and a reference voltage element 2 inputted to the other input. Comparator 1-2 has an RF multiplied signal on one input,
The reference voltage -■ is input to the other input.

The output of comparators 1-1 and 1-2 is OR gate 1-
3. D-type flip-flop (FF) via resistors 1-4
1-5 and is further connected to the D input of capacitor 1-5.
6 to ground.

The D-type FF1-5 receives the CK large input basic clock f8, its Q output is connected to the input of the AND gate 1-7, and its 0 output is connected to the input of the AND gate 1-8.

The basic clock r8 is input to the inputs of the AND gates 1-7 and 1-8, and the outputs of each are connected to the UP large input and DOWN input of the up/down counter 1-9, respectively. QA-Q of up/down counter 1-9
ゎOutput is sent to AND gate I- via OR gate 1-10.
The CY output is connected to the CK input of the D-type FF1-11, respectively. The D input of the D type FF1-11 is connected to VCC, and the Q output is the output of the touch detection circuit 201.

R of up/down counter 1-9 and D type FF1-11
For input, head touch window flag latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, if the level of the comparator 1-1 is higher than the RF multiplied signal +■, the output becomes H1, and if it is lower, the output becomes L. For example, if the level of the comparator 1-2 is higher than that of the RF multiplied signal 1, the output becomes H1, and if it is lower, the output becomes L. That is,
When the RF multiplied signal is not within the range of ±V, the output of the OR gates 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise leaking from the output of the OR gate 1-3. The output of the OR gate 1-3 from which spike noise has been removed by the integration circuit is a D-type FFl.
-5 is applied to the D input.

The D-type FF1-5 samples the state of the D input using the basic clock fM applied to the CK large input, and outputs the state to the Q output. The 0 output is the inverted output of the Q output. The Q output of the D-type FF1-5 is applied to the other input of the AND gate 1-7, which has the basic tally fM applied to one input, and when the Q output of the D-type FF1-5 is H, the AND gate is applied. The UP large input basic clock fM of the up/down counter 1-9 is inputted through the gate 1-7.

Therefore, the up/down counter 1-9 increases the basic clock f, 4 when the Q output of the window flag 14 is H and the window is set and the Q output of the D-type FF 1-5 is H. Count.

When the Q output of the D-type FF1-5 is L, that is, when the RF multiplied signal level is within ±V and it is determined that there is no signal, the 0 output becomes H. In this state, Qa'''Q of the up/down counter 1-9.

When any one of is H, that is, when the counter is not G, the basic clock f4 is D through AND gates 1-8.
It is applied to the OWN input, and the up/down counters 1-9 perform a down-count operation. In addition, due to this down count or reset, the contents of the counter become 0 and Q
When all of the outputs of A-Q are L, the output of OR gate 1-10 is L, and AND gates 1-8 are closed, so that basic clock fH is not supplied to the DOWN input.

When the up/down counter 1-9 counts up, a carry occurs and the CY output becomes H, and this rise causes the D-type FF1-11 to memorize the state of the D input. Since the D input is H, the Q output becomes H.

FIG. 6 (fat to U) is a timing chart showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in (a) is input.

In a state where the RF multiplied signal is present, the amplitude is continuously greater than ±■, and in a state where there is no signal, that is, where the head is not in contact with the tape, there is almost no amplitude greater than ±■.

Note that ±V is set to a value that allows a signal and noise to be clearly distinguished.

(In response to the RF multiplied signal input as shown in al, a waveform as shown in fb) appears in the output of the comparator 1-1, and a waveform as shown in (C) appears in the output of the comparator 1-2. And the output of OR gate 1-3 has (b
A waveform as shown in (d) appears, which is the logical sum of the waveforms 1 and (C). As is clear from the waveform of +dl, there is gate leakage etc. in the output of gates 1-3. This gate leakage is removed by the integrating circuit, and the D-type FF1-5
A signal having a waveform as shown in (e) is input to the input.

As a result, a waveform as shown in (f) appears in the Q output of D-type FF1-5, and the period when the Q output is H is AND gate 1-5.
When the basic clock f passes through 7, a signal as shown in (frame) appears at the output of AND gates 1-7. On the other hand, a signal as shown in fh appears at the output of AND gates 1-8. appear.

Incidentally, noise components slightly exceeding ±V and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears singly, the integrating circuit cannot completely remove it.

Signals (g) and fh) are applied to the UP large input and DOWN input of the up/down counter 1-9, respectively.

When the up/down counter 1-9 counts a predetermined number, it sends out a carry as shown in (i) to the CY output, and in response, the D-type FF1-11 stores the D input, and the Q output changes to U). Stand up as shown.

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down counters 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 7 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H5WP (A
/100) signal, basic clock f, 4, ATF window set signal, ATF window clear signal, noise signal, and enable clear signal are input.

The ATF equalizer 2-1, to which the RF multiplied signal is supplied from the reproduction amplifier 15 (Fig. 1), has a band 40 of the ATF sync signal.
0KH2 to 900KH2 are emphasized and output to the limiter 2-2. The limiter 2-2 converts the signal into an RF multiplied digital signal by setting H when the amplitude of the signal is larger than a specified level and setting it to L when it is smaller.

The output of limiter 2-2 is CK large input basic clock f,
is supplied to the D input of the D-type FF 2-3, and also to one input of the exclusive (E) OR gate 2-4.

The other input of the EOR gate 2-4 is supplied with the Q output of the D-type FF 2-3, and the EOR gate 2-4 and the D
The type FF2-3 constitutes a phase reversal detection circuit.

The ATF window set signal is sent to the ATF window latch 2- to which the ATF window clear signal is input to the R input.
5 and the ATF window latch 2-
The ATF window signal is output from the Q output of 5.

The output of the EOR gate 2-4 is supplied with the GK large input basic clock fM to the D input of an 11-stage shift register 2-6 whose R input receives the ATF window signal from the ATF window latch 2-5. Ru. The Q1 output of the 11-stage shift register 2-6 is passed through the inverter 2-7 to the AND gate 2-8 and the AND gate 2-9.
2~Q.

Outputs are sent to AND gates 2-8 and 2-9, Q, ~Qa outputs are sent to NOR gate 2-10 and AND gate 2-9, and Q
, ~Q, the outputs are respectively supplied to the NOR gates, and the outputs of the NOR gates) 2-10 and 2-11 are fed to the AND gates 2-8
and 2-9, respectively. and gate 2
The inputs of -8 and 2-9 are supplied with the inverted and previous H3WP (A/100) signals by the inverter 2-12, respectively. The outputs of AND gates 2-8 and 2-9 are supplied to the input of OR game 2-13.

The output of OR gate 2-13 is CK large input basic tarok f
, 4 is supplied to the D input of the 29-stage shift register 2-14. The QI output of the 29-stage shift register 2-14 is input to the AND gates 2-15 to 2-20.
Q, ~Q8 output that becomes H when sink 2 is OR gate 2
-21 input, Q that becomes H when sink 1, ~Q++
The output is H when sink 2 is input to 2-22 (or game)
The Q1□~QI4 outputs are input to the OR gate 2-23, and the Q18~Q outputs are H at both sink 1 and sink 2.
The 2° output is input to OR gate 2-24, and the Q27 to Q29 outputs, which become H when sink 1 is input, are input to OR gate 2-24.
25 inputs, respectively.

The output of OR gate 2-21 is connected to the input of AND gates 2-16 and 2-18 and the input of OR gate 2-26, and the output of OR gate 2-22 is connected to AND gates 2-15 and 2-18.
-17 and the input of OR gate 2-27, the output of OR gate 2-23 is connected to AND gate 2-16 and 2-
18 and the input of OR gate 2-26, the output of OR gate 2-24 is connected to AND gates 2-15 to 2-18.
and the input of OR gate 2-27, and the output of OR gate 2-25 is supplied to the input of AND gate 2-15, respectively. Also, or gate 2-26 and 2-
The output of 27 is supplied to the AND gates 2-20 and 2-19, respectively.

The H3WP (A/100) signal is applied to the AND gates 2-15, 2-17 and 2-19, and the AND gate 2-16
, 2-18 and 2-20 are supplied with the H3WP (A/100) signal inverted by the inverter 2-12, respectively. Further, the AND gates 2-15 and 2-16 are supplied with a noise-like signal, and the AND gates 2-17 and 2-18 are supplied with a noise-like signal inverted by an inverter 2-28.

The outputs of the above-mentioned anti-games 2-19 and 2-20 are supplied to the OR gate 2-28', and the output of the OR gate 28 is output as a detection pulse signal via the anti-games 2-29. On the other hand, the above AND gates 2-15 to 2-18
The output of is supplied to OR gate 2-30,
The output of -30 is outputted as a sampling signal SP1 via an AND gate 2-31, and an enable clear signal is supplied to the R input of the ATF enable latch 2.
-32 S input. The Q output of the ATF enable latch 2-32 is output as an enable signal and is also supplied to the input of the AND gate 2-29. The Q output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

A digital signal corresponding to ATF sync 1 and sync 2 in the RF signal is output to the limiter 2-2, and the output of the EOR gate 2-4 corresponds to one clock in accordance with the phase inversion of the digital signal.

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK high input when the window signal from the ATF window latch 2-5 applied to the R input is H. In response to the rising edge of the basic clock f, 4, the D input is taken in and sent to the Q output, and thereafter the basic clock r is input.

It is sequentially shifted every time the signal rises and is sent to the Q2 to Qll outputs. That is, shift register 2-6 is EOR gate 2
-4 output is delayed by 1 to 11 clocks to Q, ~Q+,
Send to output.

Q. When the output is L, that is, when there is a change, this is passed through the inverter 2-7 to the AND gates 2-8 and 2.
-9 and when any one of the Q6 to Q8 outputs becomes negative, it is applied to the AND gate 2 through the Nant gate 2-10.
- Make one human power of 8 H. Q z ” Q s output is H when there is no change. At this time, H3W
If P (A/B) signal is present, inverter 2-1
H is applied to the input of the AND gate 2-8 via the gate 2-8.

In this state, all inputs of the AND gate 2-8 become H, and the output becomes H. Therefore, when this condition is not met, the output remains at L, does not change for at least 4 clocks, changes for 5 to 7 clocks, and H3WP
(A/100) signal is detected and the 1/2 cycle of the sync 2 signal is detected when the B head IB is reproducing the signal.

In addition, in reality, the sink 2 signal f3 (=784KHz
, f, 4/12), so there is a length of 6 clocks that does not change, but a margin of ±11 clocks is allowed due to clock timing, jitter, etc.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

Furthermore, from the output of the AND gate 2-9, the sink 1 signal f2 (=520KHzSf, 4
/18) is detected when the H3WP (A/100) signal is being reproduced in H2, that is, the A head IA, and is output from the AND gate 2-9. It should be noted that the period with no change is the macro shift, and a change occurs between 8 and 10 clocks.

The sink 2 signal is sent from the AND gate 2-8 when the H5WP (A/100) signal is L, and the sink 1 signal is sent from the AND gate 2-9 via the OR gate 2-13 when the H3WP (A/100) signal is H. output and shift register 2-
14 D input.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock and sends it to the Q output, and thereafter is shifted every time the clock is applied and sent to the Q z -Q zq output. That is, the state of the D input is output to the Q,'-wq, output after being delayed by 1 to 29 clocks.

When there is a change in the Q output of the shift register 2-14, the Q output becomes H. Sink 2 signal (f3=780K
Hz, 1/12 f, ), if there is a change 1/2 period before the Q1 output, OR gate 2-21
The output becomes H. Further, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. The output of the OR gate 2-26 is the Ql output of the shift register 2-14 and H3WP (A
/100) signal is applied to the input of the AND gate 2-20. That is, for sink 2, AND gate 2
Q after one clock delay after detecting sink 2 by -8
, the output appears at the output, and at this time, the change from 1/2 period ago is transmitted through ORG) 2-21 and 2-26, and the change from one cycle ago is transmitted through ORG) 2-23 and 2-26, respectively. When simultaneously applied to the inputs of the AND gate 2-20, the output of the AND gate 2-20 becomes H, and accordingly the output of the OR gate 2-28 becomes H.

The output of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink is 2, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SP1 via the OR gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable latch 2-32, causing the ATF enable rough The Q output of chip 2-32 becomes H and the Q output becomes L. The Q output is output as an enable signal and is applied to the AND gate 2-29.
After that, the detection pulse signal can be outputted.

In the case of sink 2, when the noise signal is H,
The output of the AND gate 2-16 becomes H, and a similar operation is performed.

On the other hand, when sink 1, or gate 2-22°2-2
When the outputs of 4 and 2-25 become H, and the noise signal is L, the output of AND gate 2-17 becomes H, and when the noise signal is H, the output of AND gate 2-15 becomes H, and as described above. A similar thing is done.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

FIGS. 8(a) to 8(gl) are timing charts showing waveforms of various parts during detection of the sink 2, and corresponding symbols are given in FIG. 7.

Further, FIGS. 9A to 9E are timing charts showing waveforms of various parts when detecting the sync 1, and corresponding symbols are given in the figures.

FIG. 10 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
A signal, a basic clock f, , HSWP (A/100) signal, an enable signal, an enable clear signal, a rear/degree front borrow signal, an initial signal, and a detection pulse signal are input.

Enable signal to E input, CK large input basic clock fM
, and the 0 and 25 block counters 3-1 each having an enable clear signal input to their R inputs have a value of 9.5.
When a count corresponding to μs is performed, the CY output becomes H, which is input to the E input of the high counter 3-2 and the decoder 3.
-3 are respectively input to the C input.

High counter 3-2 is CK large input basic clock fH,R
An enable clear signal is input to each input, and counts up every 0.25 block. The Q, ~Q, (2°~23) output of the counter 3-2 is sent to the decoder 3.
-3 is input.

Decoder 3-3 is for decoding each time,
Only when the C input is H, the 0 to 8.16 and 17 outputs become active, and the 0 to 8 outputs send 0.25 to 2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is connected to the gates 3-4 to 3-7.3-
9 to 3-11, and the 0.5 block signal is supplied to the R input of the edge 3-12 and the CK large input of the D-type FF 3-13, and the 1 block signal is supplied to the CK of the D-type FF 3-14. Large input supplied.

The decoder 3-15, which receives the HSWP (A/100) signal and the rear/previous signal, respectively, outputs the A that is currently being played.
This is for decoding the position of the TF signal, and B-ATF-1, A-ATF-1, B-ATF-2 is used for 0 to 3 outputs.
and A-ATF-2 signal as output, which is sent to the gate 3 above.
-4 and 3-7 as well as gates 3-16 and 3-17.

Table 3-18 to which the HSWP (A/100) signal and the initial signal are input holds the sink detection threshold value, and the held threshold value is switched by the HSWP (A/B) signal and the initial signal. and sets it in the sync detection counter 3-19.

The HSWP (A/100) signal sets each section for sync 1 when playing A head and for sync 2 when playing B head, and each section sets 50% of the number of consecutive sync patterns.
It becomes. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-15, 3-27 and inverters 3-28 to 3-27.
3-30.

Then, the sample signal SP2 is output from the gate 3-10.
Error detection signal is output to the output of gate 3-26, sample signal S P 3 A is output to the output of gate 3-4, ATFEND signal is output to the output of gate 3-27, and sample signal 5P3B is output to the output of gate 3-7. do.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SP1, the 0.25 block counter 3
-1 starts counting, and every 0°25 block its C
Y output becomes H. The decoder 3-3 is a high counter 3
-2 state is decoded and 0.25 block count 3
The output becomes H only when the -1 CY output is H.

When 1 output of decoder 3-3 becomes H, 0, 5
As processing after blocking, this is applied to the input of the sink detection counter 3-19 via the OR gate 3-11, and is also applied to the R input of the latch 3-12 and the D-type FF 3-1.
It is also applied to CK man power of 3.

Since the CY output of the sync detection counter 3-19 is input to the D input of the D-type FF 3-13 via the latch 3-12, it is determined whether there is a detected pulse signal greater than the specified value after 0.5 blocks. This will be sampled by the D-type FF3-13. At the same time, the latch 3-12 is reset and the sync detection counter 3-12 is reset.
19, set the threshold value again from Table 3-18.

When the 3 outputs of the decoder 3-3 are H, processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF 3-14 applied to the D input via the latch 3-12. After one block, sampling is performed to determine whether there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and 3-30 determines whether or not a prescribed detection pulse signal is present based on the ODD/EVEN signal. O
In the case of DD, it is D type FF3-13.

Q outputs of 3-14 are both HS]? , D in case of VEN
When the Q output of the type FF 3-13 is H, the output of the OR gate 3-25 becomes H if there is a specified detection pulse signal.

In similar processing, when the initial signal is H, the output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR game 3-25 becomes L. Therefore,
When the 4 outputs of decoder 3-3 are H, that is, 1.25
After blocking, when a specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-9
An erroneous detection signal of H is outputted via the .

When the 7 output of decoder 3-3 is H, that is, the 2 pro
After linking, there is a specified detection pulse signal and it is OK.
A sampling signal S for sampling other adjacent tracks is sent to the output of the AND gate 3-10.
Output P2.

Also, after 4 blocks when the 3 outputs of the decoder 3-15 are H during playback by the A head and the 16 outputs of the decoder 3-3 are H, the sampling signal 5P3A is transferred to the B
When the 1st output of decoder 3-15 is H during playback by the head and the 16th output of decoder is H, 5P
Output 3B and sample the on-track level.

Furthermore, when the 17 output of the decoder 3-3 is H, and the A head is ATF-2 and the B head is ATF-1, ATFEN is output through the gates 3-17, 3-5 and 3-27.
A D signal is output. Then, when the 8 outputs of the decoder 3-3 become H when the A-head is ATF-1 or the B-head is ATF-2, the ATFEND signal is output via the gates 3-16, 3-6 and 3-27. .

FIGS. 11(a) to 11(g)) are timing charts showing waveforms of each part associated with the above operation, and corresponding symbols are assigned to each part.

Note that in the above embodiment, only the operation of the ATF signal processing section is controlled based on the beginning part of the reproduced signal, but the SU
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as B 1 , PCM, and 5UB-2.

〔effect〕

As explained above, according to the present invention, the detection of the sync signal is stopped when the level of the pilot signal frequency component in the output signal of each rotary head does not have a predetermined relationship with the level of the sampled on-track pilot signal. This prevents the on-track pilot signal from being erroneously detected by the unerased sync signal and controlling the capstan servo, thereby preventing capstan servo disturbance.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing main parts of the present invention,
Figures 3 and 4 are timing charts showing signal waveforms of each part in Figure 2, Figure 5 is a circuit diagram showing the specific configuration of a part of Figure 2, and Figure 6 is in Figure 5. FIG. 7 is a block diagram showing the specific configuration of other parts in FIG. 2. FIGS. 8 and 9 are timing chart diagrams showing signal waveforms of each part in FIG. FIG. 10 is a circuit diagram showing a specific configuration of another part in FIG. 2, FIG. 11 is a timing chart showing signal waveforms of each part in FIG. 10, and FIG. R-DA
FIG. 13 is a diagram showing the track format and block format of T, FIG. 13 is a diagram showing the ATF rack pattern of R-DAT, and FIG. 14 is a diagram for explaining the principle of tracking control using the track pattern of FIG. . IA, IB... Rotating head, 103, 104, 105
a, 105b...sample hold circuit, 107...
・Comparator, 108...Differential amplifier, 202...
・Sink detection circuit, 217, 218...OR gate,
219...Inverter, 2-5...ATF window flag launch.

Claims (1)

[Scope of Claims] A plurality of signals including a tracking pilot signal and a sync signal consisting of a digital signal and a frequency signal with little azimuth effect are recorded in each of a plurality of diagonal tracks in independent recording areas in the longitudinal direction of each track. A recording in which the pilot signals are recorded in three consecutive tracks in a predetermined format, and the pilot signals are recorded in different positions, and the sync signal is recorded in a position corresponding to one adjacent track. at least two rotary heads for reproducing the plurality of signals on the medium, each rotary head having a width greater than the width of each track, and reproducing each track providing an on-track pilot signal and an on-track pilot signal to the output of each rotary head. Crosstalk between pilot signals of both adjacent tracks is obtained, and a capstan servo is controlled based on a level difference in the crosstalk of pilot signals of both adjacent tracks, so that each rotary head scans over each track, sync detection means for detecting the sync signal; first holding means for sampling and holding the level of the pilot signal frequency component from the output signal of each rotary head in response to the detection of the sync signal by the sync detection means; means for determining the level difference between the level held in the first holding means and the level of the frequency component of the pilot signal in the output signal of each rotary head after a certain period of time from the detection of the sync signal by the sync detection means; a second holding means for sampling and holding the level difference; a third holding means for sampling and holding the level of the on-track pilot signal; and determining means for determining whether or not the levels of the pilot signal frequency components in the output signals of the respective rotary heads are in a predetermined relationship, and when the determining means determines that the predetermined relationship does not exist, a sync detection circuit is provided. A digital signal reproducing device characterized by: prohibiting the detection of a sync signal by the sync signal.