JPS6318501A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To obtain a reproducing signal not including noise at the switching of a rotary head by providing a count means generating the post-recording start signal of a predetermined 1st time and a control means generating a reproduction start signal to the count means after the count of a predetermined 2nd time. CONSTITUTION:A waveform (d) appears at an output of an OR gate 1-3 in response to an input of an RF signal from a reproducing amplifier, a gate leakage or the like is eliminated by an integration circuit and a signal (e) shown in waveform is inputted to an input of a D flip-flop 1-5. As a result, a waveform (f) appears at a Q output of a D FF1-5, a signal (g) appears at an output of an AND gate 1-7 by a basic clock fM passing through the gate while a Q output is logical H and a signal (h) appears at the output of an AND gate 1-8. The signals (g), (h) are fed to an up-down counter 1-9 and a carry (i) is sent to a CY output after a prescribed count and a Q output (j) of the D FF1-11 rises.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, records this as one diagonal track on a recording medium by a rotating head for each unit time, and reproduces this. This invention relates to a digital signal recording and reproducing device that has been used for a variety of applications.

[Technical background of the invention and its problems]

A device that records audio signals on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotary head, and when reproducing the audio signals, converts the audio signals into PCM and records and reproduces them. There is a digital signal recording and reproducing device called R-DAT (rotating head digital audio tape recorder), which is considered as a rotary head type digital audio tape recorder.

The format of the track actually recorded on R-DAT is the pattern shown in Figure 12 (al), and the frequencies of MARGIN, PLL, and PO3 TAMBLE are 1/2f, 4 (fs=9.4MHz).
, IBG frequency is 1/6fK. SUB and PCM
is composed of blocks as shown in FIG. 12(b). 5YNC is fixed at 9 bits, and the rest are as follows:
There are various patterns depending on the location, audio signal, etc. In the case of SUB, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 12 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas located between 5UB-1 and PCM and between PCM and 5UB-2 (A T
F: Automatic Track Findi
ng) is intended to enable tracking control so that the rotary head correctly scans the recording track during reproduction using the output of the rotary head without providing a special head.

That is, the ATF area is located at the beginning and end of each track when the PCM signal is compressed in the time axis and recorded by two rotating heads diagonally forming tracks on a magnetic tape without a guard band. A PCM signal is a tracking pilot signal recorded in separate recording areas, and during playback, the recording trunk is scanned by a rotating head whose scanning width is wider than the track width, and the rotating head scans both adjacent tracks of the track being scanned. The reproduction output of the pilot signal from the rotary head is used to control the tracking of the rotating head.

Then, the track pattern for this ATF is the first one.
As shown in Figure 3, the pattern shown is a drum diameter of 30mm, a drum winding angle of 90'', and a rotation speed of 20mm.
The case of 00 rpm will be explained.

ATF1 and ATF2 located in the front and rear parts of each trunk are low frequency signals f with little azimuth effect as pilot signals for tracking.

This is used to detect the level of crosstalk from both adjacent trunks during playback, and to obtain the level difference between the crosstalk components of both adjacent tracks as a tracking error signal. A low frequency signal of 7f, 4/72 (130 KHz) is used as the piezo signal r1.

Further, in ATF1 and ATF2, a sync signal for determining the position where the viroft signal f is recorded is recorded. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. Assuming that the head corresponding to +azimuth is A and the head corresponding to -azimuth is B, the sync signal is different from each other to distinguish between A head and B head, and the frequency for A head is different. Sync l signal f2 of fM/18 (-522KHz)
However, for the B head, the frequency fs /12 (=78
4KH2) sink 2 signal f.

are recorded at respective predetermined positions.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. For this reason, a frequency fM/6 (=1.5'6MHz) is placed at a predetermined position to erase the pilot signal f of the previous recording, the sync 1 signal f2, and the sync 2 signal f3.
An erasure signal f4 is recorded.

The positions of the ATF pilot signals are all different between the on-track and both adjacent trunks, and the level of the on-track pilot signal and the level of the pilot signal of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Five blocks are allocated to each of the ATF areas ATF 1 and ATF 2, and pilot signals f are recorded in two of the blocks. The sync signals f, , f3 are 1 from the center of the position where one adjacent track is recorded.
It is recorded using blocks or 0.5 blocks.

The pilot signal f1 of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. 1 block of sync signals are assigned to odd frames, and 0.5 blocks of sync signals are assigned to even frames.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish between them. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, in order to perform recording in the format shown in FIG. 12(a) on a magnetic tape using two rotary heads, it is necessary to control the servo of the drum motor that rotates the drum on which the two rotary heads are installed, and to use the rotary heads. All you have to do is measure the time based on the signal from the pulse generator (PG>) installed on the drum to generate signals used for switching, etc., and specify the recording start position. This is because the positional relationship between the rotary head and the PG in the recording apparatus is determined in advance.

On the other hand, when a magnetic tape recorded in the formant shown in FIG. 12(a) is reproduced by a rotary head, an RF multiplied signal as shown in FIG. 14(a) is obtained from the rotary head. For example, if this RF multiplied signal is obtained by reproducing the odd-numbered frame track (A) in FIG.
By passing through a 30 KHz band pass filter (BPF), a biloft signal f1 as shown in (b) is obtained.

Section I is due to on-track pilot signals, and sections ■ and ■ are due to crosstalk between pilot signals of (B) odd frame track and (B) even frame trunk. When the rotating head is correctly scanning on the track, the envelope levels of sections ■ and ■, that is, V■ and v■ of (C1) should be equal, but if there is trunk deviation, ■■≠■■ Then,
The amount and direction of deviation of the rotary head from on-track can be determined by its magnitude and polarity. Therefore, by operating the capstan servo and finely adjusting the tape speed based on the difference between V■ and V■, the rotary head can be run on track.

In order to perform the above-described operation, it is necessary to detect the sync signal at a predetermined position and accurately sample the levels of ■■ and ■■. However, the PCM signals in the SUB and PCM areas before and after the ATF area have the same frequency components as the pilot signal fI and the sync signals f2 and f. Therefore, it is necessary to accurately set the window so that the signal processing section that should operate in connection with the ATF area does not operate when it is in the SUB or PCM area.

Similar statements can be made regarding the SUB and PCM areas.

Therefore, it has been considered to set the window based on the signal from the pulse generator (PC).

However, with this method, there is no compatibility between devices having different positional relationships between the rotary head and the PG.

Even if the model or equipment is the same, the position of the window relative to each rotary head may not be constant due to manufacturing variations or changes over time. Of course, it is possible to set a narrow window to some extent by adjusting the window creation for each drum and head, but the adjustment work is troublesome and costly, and it is difficult to connect with other equipment. There are still issues with compatibility.

To eliminate such problems, always use a constant oma,
It is possible to control the processing time of each No. 13 based on the playback signal that is at the top, but in order to do this, it is necessary to detect the beginning of the playback signal from the output signal of the rotary head after switching to rotation. be.

However, since noise is included in the output signal of the rotary head when the rotary head is switched, there is a risk that a so-called malfunction may occur, in which noise is detected as the leading portion of the reproduced signal.

〔the purpose〕

In view of the above-mentioned problems, the present invention provides a digital signal recording and reproducing apparatus which detects a reproduced signal without malfunction and can detect the reproduced signal with a simple configuration by using a timing means that determines the recording start point during recording. is intended to provide.

[Summary of the invention]

A digital signal recording and reproducing apparatus according to the present invention, which has been made to achieve the above object, forms a plurality of diagonal tracks on a recording medium, and each track contains a plurality of digital signals obtained by converting an audio signal into a PCM signal and compressing the time axis. at least two recording/reproducing rotary heads for recording the signals in a predetermined former in independent recording areas in the longitudinal direction of each track and reproducing the plurality of signals on the recording medium; at least one pulse generating means provided in a predetermined positional relationship with respect to the two recording/reproducing rotary heads and rotating together with the rotary heads to generate a pulse every rotation; The two rotary heads are alternately switched in response to the pulses, each rotary head records a plurality of signals on each track during recording, and each rotary head reproduces a plurality of signals from each track during reproduction, During recording, time measurement is started in response to a pulse from the pulse generating means, and a predetermined first
a timer for generating a recording start signal after measuring a second time; and a timer for starting timekeeping by the timer in response to a pulse from the pulse generating means during playback, and for causing the timer to start measuring time after measuring a second predetermined time. and control means for generating a reproduction start signal.

This makes it possible to obtain a reproduced signal that does not include noise when switching the rotary head with a simple configuration.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, reference numeral 1 denotes a rotating drum with a diameter of 30φ, and the rotating drum l has two rotating heads, an A head IA for recording and reproducing +azimuth and a B head IB for recording and reproducing one azimuth. The A head IA is spaced apart from each other.
Two pulse generators (PG) PGA and PCB are arranged at an intermediate position between the B head IB and the B head IB.

2 is a crystal oscillator that generates a basic clock r8 of 9.4 MHz, and the basic clock fM is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system, outputs a P B/REC switching signal, and performs switching control of the toggle switch 4 consisting of switches SWI and SW2.

5 is a reference signal generator, which generates reference signals of XH2 (66Hz: in the case of 2PG), YHz (depending on the number of FG of the capstan motor) and ZHz based on the basic clock f, 4 applied to the CK large input. do.

Reference numeral 6 denotes a drum servo, which servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. 7 is a reel servo, which servo-controls the rotation of the reel motor based on the reference signal ZHz under the control of the system controller 3. 8 is a capstan servo, which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when switch 4 is switched to the B contact side by the system controller 3, and switch 4 is switched to the A contact side. During playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is an ISWP (A/100) signal generator, and drum 1
The ISWP (A/100) signal is generated to switch between A head IA and B head IB based on the pulses from the two PCs above.
, 8671, which are also supplied to each part of the system.

Reference numeral 10 denotes a phase reversal detection circuit, to which the basic clock f and the ISWP (A/B) signal applied to the CK large input are input, and the output is supplied to the S input of the initial flag latch 1). Initial hula knob latch 1) is R
The CY output of the initial counter 12 is input to the input,
The Q output is supplied to the R input of the initial counter I2.

The initial counter 12 is set with a threshold value from a table 13 under the control of the P B/RE C signal from the system controller 3, and the CY output becomes H by counting the set value. The CY output is applied via the inverter 13a.
AND gate 13 opened and closed by B/RE C signal
The signal is input to the encode data processing section 18 via the PB/REC signal, and is also supplied to the S input of the head touch window flag latch 14 via the AND gate 13c, which is opened and closed by the PB/REC signal.

The head touch window flag latch 14 is used to generate a window that prohibits the head touch detection operation during the noise period when switching the head.The Q output is input as an on signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, ISWP (A/
100) Encode data processing unit 18 (described later) based on the signal
The recording data is received and supplied to the rotary heads IA and IB via the switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
After extracting data from the F signal, performing 10/8 conversion (demodulation), deinterleaving, error correction, etc., it is sent to the D/A converter, and also performs head touch detection, ATF sync detection, tracking error detection, etc. An error signal is supplied to the capstan servo 8 from the track deviation signal generating section 17a.

The encoded data processing unit 18 performs interleaving, parity addition, 8/1O conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above configuration, P from the system controller 3
A recording operation is performed when the B/REC signal is L.

The switch 4 is switched to the b contact side by the PB and /REC signals, the reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, and the capstan is activated based on the reference signal YHz. The servo is activated and tracking is controlled.

The ISWP (A/100) signal output by the ISWP (A/100) generator 9 based on the pulses generated by PGA and PGB due to the rotation of the drum 1 is H, 86 when the A head is IA.
71) It becomes L at 8 o'clock. This ISWP (A/100) signal is input to the phase inversion detection circuit 10,
/100) When the signal level changes, that is, when it is detected that the head has switched, the phase reversal detection circuit 10
The output becomes H for only one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial flag latch 1) is set and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic clocks fM corresponding to a certain period of time corresponding to 3.75 ms based on the cent value from the table 13, its CY output rises, thereby causing the initial flag latch 1 )
is reset, and the rising edge of the CY output is applied to the encode data processing section 18 as a recording start signal. Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined format.

Next, when the P B/RE signal from the system controller 3 is H, the switch 4 is set to the a side, and the rotating head I
A and IB are connected to the reproduction amplifier 15 and supplied to the RF multiplied signal decode data processing section 17 .

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The track deviation amount is an ATF error signal corresponding to the level difference in the crosstalk amplitude of the pilot signals of both adjacent tracks, and the details will be described later.

H3WP (A/100) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 becomes a playback mode counter based on the set value from table 13, and the count value is, for example, 100 μs/1.
When the value corresponds to m s, the CY output becomes H. This prohibits the head touch operation, which will be described later, while noise occurs when the head is switched, and sets the head touch window flag latch 14 via the AND gate 13 after the above-mentioned certain period of time, and outputs its Q output. This is to set it to H and output an on signal for head touch detection. When the decode data processing unit 17 detects a head touch, that is, a contact between the tape T and the head IA or IB, and outputs an RF multiplied signal, the on signal from the head touch window flag latch 14 is turned on. Sochi 14 is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproducing amplifier 15, a band pass filter (BPF) 101, and an envelope detector 102.
, the first sample hold (S/H) circuit 103, the 23rd
/H circuit 104, third S/H circuit 105a and 1osb
, toggle switch 106, comparator 107, differential amplifier 108, level correction circuit 109, and resistor R, ~
It consists of R4.

On the other hand, the digital system includes a crystal oscillator 2, a head touch detection circuit 201, a sync detection circuit 202, an ATF timing generator 203, a regeneration flag latch 204, a system counter 205, a timing generator 206, a 1/2 frequency divider 207, and an ATF initial flag. Lunch 208,
It consists of a power-on reset circuit 209, a latch circuit 210, a protection counter 21), a noise error latch 212, a latch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, to explain from the analog system, the RF multiplied signal is input from the rotary heads IA and IB (Fig. 1) to the input of the reproduction amplifier 15, and its output is input to each input of the BPF IOL, the head touch detection circuit 215, and the sync detection circuit 216. Supplied.

BPF 101 passes only the 130 KHz component in the RF signal and inputs it to envelope detector 102 . The envelope detector 102 envelope-detects the 130 KHz component, and sends it to the S/H circuits 103, 105a, 10.
5b and the differential amplifier 108.

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SPI applied from the sync detection circuit 202 to the C input, and outputs this to one input of the comparator 107 and the output of the differential amplifier 108. Apply each. What is sampled and held by the S/H circuit 103 is the DC level of the crosstalk of the pilot signal of one adjacent track.

The S/H circuit 104 receives a signal whose level has been adjusted by the level adjustment circuit 109 at its input, samples and holds this signal using the sampling signal SP2 from the ATF timing generator 203, and outputs the signal to the capstan servo 8 (Fig. 1).
is supplied as an ATF error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The S/H circuit 105a samples and holds the output from the envelope detection H102 using the sampling signal 5P3A from the ATF timing generator 203, and outputs it to one end of the resistor R and the a contact of the switch SWI of the toggle switch 106.

The S/H circuit 105a samples and holds the D on-track pilot signal during A trunk playback.
It is C level.

The S/H circuit 105b samples and holds the output from the envelope detector 102 using the sampling signal 5P3B from the ATF timing generator 203, and outputs this to one end of the resistor R and the b contact of the switch SW1 of the toggle switch 106.

What the S/H circuit 105b samples and holds is the D on-track pilot signal when B track is played back.
It is C level.

Resistors R3-R4 have the same value, and S/H circuits 105a and 105a are added to one end of resistors R1 and R3, respectively.
This is for dividing the output of 5b. The interconnection point of resistors R5 and R2 and the interconnection point of resistors R3 and R4 are respectively connected to the a contact and b contact of switch S W 2 of toggle switch 106, and each interconnection point is connected to each S A level of 1/2 of the sample and hold value of the /H circuit is obtained.

The toggle switch 106 is controlled by the HS'i'/P (A/100) signal, and is switched to the a side when the H3WP (A/100) signal is H, and to the b side when it is L.

The comparator 107 has one input connected to the S/H circuit 105a.
and the level of 172 of the output of 105b is connected to the resistors R3 to R4.
and is applied via the switch SW2, and the output of the S/H circuit 103 is applied to the other input. Comparator 1
07, when 1/2 of the sample and hold values of the S/H circuits 105a and 105b is larger than the output level of the S/H circuit 103, the output becomes H, and this is sent as an OK double signal to the input of the ATF timing generator 203. supply

The differential amplifier 108 separates the output of the envelope detector 102, which is applied to the input power, and the S/D output, which is applied to the input power.
The difference between the output of the H circuit 103 and the output of the H circuit 103 is taken and inputted to the level adjustment circuit 109. That is, envelope detector 1
The output of 02 is the DC of the crosstalk of the other adjacent trunk.
When outputting the level, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

The level adjustment circuit 109 is the S/H circuit 105a and 105
For example, the amplification degree is changed in inverse proportion to the output level of b,
By adjusting the signal level from the differential amplifier 108, variations in the outputs of the rotary heads LA and IB are corrected.

Next, to explain the digital system, the head touch detection circuit 201 is connected to the head touch window flag latch 1.
4 (FIG. 1) and the basic clock fH, it detects that the RF multiplied signal is input, and supplies the signal to the S input of the reproduction flag latch 204, the details of which will be described later.

The sink detection circuit 202 detects the RF multiplied signal HSWP(A
/100) signal, AT from timing generator 206
F window cent signal, AT from OR gate 217
F window off signal, noise error graph 212
, the basic clock "4" from the crystal oscillator 2, and the enable clear signal from the OR gate 216 are input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to the output.The sampling signal SPI is the S/ C input of H circuit 103 and latch 2
The enable signal and the detection pulse signal are input to the ATF timing generation circuit 203 through the R input of 10, respectively. The sync detection circuit 202 converts the RF multiplied signal into a digital signal, detects the beginning of the ATF sync patterns SYl and SY2 of the rotary heads IA and IB, outputs a sampling signal SPI, and then outputs a sampling signal SPI to the continuously detected sync patterns. It operates to output a detection pulse signal against the
Details will be described later.

The ATF timing circuit 203 receives an OK double signal which is the output of the comparator 107, an ODD/EVEN signal which is the Q output of the 1/2 frequency divider 207, an initial signal which is the Q output of the ATF initial flag latch 20th, and a sink detection circuit 202. an enable signal and a detection pulse signal from
After/before” signal from timing generator 206;
The enable clear signal from the OR gate 216 and the basic clock from the crystal oscillator 232 are input, and the sampling signals SP2.5P3A, 5P3B,
Sends an erroneous detection signal and an ATFEND signal. The sampling signal SP2 is connected to the C input of the S/H circuit 104 and the ATF.
The sampling signal 5P3A is connected to the S input of the initial flag latch 208, the sampling signal 5P3B is connected to the C input of the S/H circuit 105b, and the false detection signal is connected to the S input of the latch 210 and the OR gate 21.
6 and the CK large input of the false detection counter 214,
The ATFEND signal is input to one input of OR gates 216 and 217, respectively.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer counter (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and performs a specified If the detected pulse exceeds the specified value by the time, the sampling signal SP2
．． It outputs 5P3A and 5P3B, and operates to output an erroneous detection signal when it is below a specified value or at the L level of the OK multiplied signal which is the output of the comparator 107, and the details will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of channel bit data of the R-DAT, and outputs a basic clock f8. The basic clock fPl is used by the head touch detection circuit 201, the sync detection circuit 202, and the ATF.
The CK large inputs of the timing generator 203, system counter 205, and protection counter 21) are respectively applied.

The latches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes H in response to a rising edge of the S input, and whose Q output becomes L in response to a rising edge of the R input.

The reproduction flag latch 204 receives the output of the head touch detection circuit 201 at the S input, the END signal which is the output of the timing generator 206 at the R input, and its Q output is input at the R input of the system counter 205. . When the Q output of the regeneration flag latch 204 is H, the regeneration operation is in progress.

The system counter 205 receives the Q output of the reproduction flag latch 204 and the CK large input basic clock r at its R input, and the outputs Q0 to Q and I are input to the timing generator 206.

This system counter 205 is intended to roughly indicate where each signal is recorded on the trunk.

The timing generator 206 generates an STF window set signal, a rear/■ double signal window clear signal, and an END signal at its output based on the Q, ~Q, outputs from the system counter, and sends the ATF window set signal to the sync detection circuit 202. , the after/“before” signal to the ATF timing generator 203, the window clear signal to the OR gate 217, and the END signal to the regeneration flag launch 2.
04 R input respectively. This timing generator 206 decodes the output of the system counter 205 and generates the timing required for each part.

1/2 frequency divider 207 is H3WP to which CK large input is applied.
(A/100) Divide the signal by 1/2 and send ODD/EV to Q output
Generates an EN signal and sends it to the ATF timing generator 20
Supply to 3. The Q output of the ATF initial flag latch 208 is input to the R input of the 1/2 frequency divider.

ATF initial flag launch 208 is AT to S input
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. The ATF Initial Rufurano Gratchi 208 is ATF
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The launch 210 has an ATF timing generator 203 on the S input.
The erroneous detection signal from the sync detection circuit 202 and the sampling signal SPI from the sink detection circuit 202 are input manually, respectively, and the Q output is input to the R input of the protection counter 21). When the launch 210 is erroneously detected, the Q output becomes H and is reset in response to the output of the sampling signal SP1.

The protection counter 21) is for counting a certain period of time from erroneous detection, and only when the R input is H, it counts the basic clock f, 4 to which the CK high input is applied, and the R
Cleared by input.

The Q output of the latch 210 is input to the two-way input, and the CY output is input to the OR gate 217.

The noise flag latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The latch 212 is manually powered by the Q output of the latch 213 and the CY output of the large CK input sampling counter 215, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

The latch 213 receives the CY output of the erroneous detection counter 214 at its S input, the CY output of the sampling counter 215 at its R input, and is supplied to the D input of the °Q small output noise error latch 212.

The false detection counter 214 receives the false detection signal from the large CK input ATF timing generator 203 and the CY output of the sampling counter 215 at its R input, and the CY output is supplied to the S input of the latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SPI is erroneously detected during a - period, and when the value exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives CK large input H3WP (
A/100) signal is input, and CY output is false detection counter 2.
14, the R input of the touch 213, and the CK large input of the noise error flag 212 are respectively supplied.

The OR gate 216 connects the false detection signal from the ATF timing generator 203 and the ATFEND signal to the protection counter 21.
) is input, and the sync detection circuit 2 is input to that output.
02 and an enable clear signal to the ATF timing generator 203.

OR gate 217 is a window clear signal from timing generator 206, ATF timing generator 20
3 and the CY output from the protection counter 21) are respectively input, and the ATF window off signal to the sync detection circuit 202 is sent to the output thereof.

In the above configuration, the head touch detection circuit 201 and the sync detection circuit 202 pass through the RF double signal regeneration amplifier 15.
and the BPF 101. B.P.
Only the 130 KHz component of the RF multiplied signal supplied to F 101 is treated. The amplitude level of the 130KHz component is converted to a DC level by the envelope detector 102, and then the S
/H circuits 103, 104, 105a and 105b, and the differential amplifier 108.

The envelope detector 102 sequentially outputs the DC level of the amplitude of the crosstalk of the pilot signal of one adjacent trunk, the crosstalk of the biloft signal of the other adjacent track, and the pilot signal of both adjacent tracks in chronological order. The DC level of the amplitude of the on-track biloft signal is output before or after the signal.

The S/H circuit 103 samples and holds the pilot signal of one adjacent trunk at the timing of the sampling signal SPI from the DCC level sync detection circuit 202. is applied to

The S/H circuit 105a converts the DC level of the on-trunk pilot signal during playback of +azimuth A track to the S/H circuit 105a.
The circuit 105b samples and holds the DC level of the on-track pilot signal while the azimuth B track is being reproduced. The output of the S/H circuit 105a, that is, the DC level of the on-track biloft signal is:
It is supplied to the control input of the level adjustment circuit 1090 through the a contact of the switch SWI of the toggle switch 106, and after being divided in half by the resistors R and R2, it is supplied to the comparator 107 through the a contact of the switch SW2. supplied to one input. Similarly, the output of the S/H circuit 1osb is sent to the level adjustment circuit 10 via the b contact of the switch SWI.
9, and after being divided into 1/2 by resistors R3 and R4, the voltage is applied to comparator 107 via the b contact of switch SW2.
is fed to one input of

The comparator 107 becomes an OK multiplied signal H when the level input via the switch SW2 is higher than the input from the S/H circuit 103. In other words, it is determined that the crosstalk level of one adjacent track has been correctly sampled. In the opposite case, it is determined that the on-track level has been sampled. Therefore, when the OK double signal is L, it is determined that the sync has been erroneously detected. This OK double signal is supplied to the ATF timing generator 203.

The differential amplifier 108 receives the DC level of the crosstalk amplitude of one adjacent track when the envelope detector lO2 is outputting the DC level of the crosstalk amplitude of the other adjacent track. Therefore, the output includes the difference in DC level of crosstalk between both adjacent tracks,
That is, the amount of track deviation is obtained, and this is input to the level adjustment circuit 109.

The level adjustment circuit 109 is the S/H circuit 105a and 105
The output of b is applied as a control input, and when the control input is large, the level of the input signal is lowered, and when it is small, it is raised and output.

In short, the level adjustment circuit 109 automatically corrects variations in the outputs of the two rotary heads and inputs the result to the next S/H circuit 104. The S/H circuit 104 samples and holds the corrected deviation amount of both adjacent tracks using the sampling signal SP2. The output of this S/H circuit 104 is supplied to the capstan servo 8.

FIGS. 3(a) to 3(1) are timing charts showing the signal waveforms generated in each part by the above operation, with the remainder corresponding to the reference numerals attached to each part.

The H3WP (A/B) signal shown in Figure 3(b) is
When reproduced by B, it becomes L. H3 when the head does not switch
The phase of the WP (A/100) signal is inverted. When the phase is reversed, the Q output of the initial flag latch 1)' (FIG. 1) becomes H, and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is determined that the tape has passed a noisy part, and the head touch window flag latch 1
4 (Figure 1) to set its Q output to H. Q output of head touch window flange latch 14 is H
Then, the head touch detection circuit 201 operates.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF multiplied signal is reproduced, its output becomes H.
, set the regeneration flag latch 204 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 outputs the ATF window set signal to the sync detection circuit 2 based on the Q0 to Q8 outputs of the system counter 205 and outputs the ATF window set signal a little before the recording of ATF-1 and ATF-2.
Supply to 02.

After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects sync 1 (""
Each sink is detected based on the fact that the patterns of fz) and sink 2 (=f3) in the case of B head IB have the relationships shown in the table below depending on the frame.

When the sync detection circuit 202 detects 4 syncs in the normal case or 5 syncs in the noisy case, it outputs a sampling signal SPI, and sends a cross of the pilot signal r of one adjacent trunk to the S/H circuit 103. The talk level is sampled and held, and an enable signal is supplied to the ATF timing generator 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SPI is output from the sync detection circuit 202.
It is checked whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI. Next 1゜2
After 5 blocks, it is determined whether the sync has been detected at a specified value or higher, and if it is at or above the specified value, it is assumed that the sync has been detected correctly and after 2 blocks, the sampling signal SP2 is
The signal is supplied to the H circuit 104 to sample and hold the level difference of the Kuko talk between both adjacent tracks, and the output thereof is supplied to the capstan servo 8 as the amount of track deviation.

In addition, if the on-track pilot signal f exists after the sync, when playing back by the A head IA,
When playing TF-2 and B heads, it is ATF-1, so in this case, sampling signals 5P3A and 5P3B are output after 4 blocks, respectively, and these are converted to S/T (
The level of the on-trunk biloft signal supplied to the circuit 105a and S/H 105b and reproduced by each head is sampled and held.

If the above series of operations are performed correctly, ATFEND
A signal is output, which is passed through the OR gate 216 as an enable clear signal to the sink detection circuit 202 and the AT.
It is supplied to the F timing generator 203. ATFEND
The signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. .

Missampling, that is, the output of the comparator 107 changes the level of the on-track pilot signal to S/H.
If it is determined that the circuit 103 has sampled and held,
If the sink is not equal to or greater than the specified value, the erroneous detection signal is set to H, the Q output of the launch 210 is set to H, and the protection counter 21) performs a counting operation, and the erroneous detection counter 214 performs a +1 operation. When the false detection signal becomes H, the enable clear signal to the sink detection circuit 202 and ATF timing generator 203 via the OR gate 216 also becomes H.

When the enable clear signal becomes H, the sink detection circuit 2
02 performs the operation of detecting the sync again from the beginning, and once the sync is detected, outputs the sampling signal SPl again. On the other hand, the ATF timing generator 203 sets the sync detection counter and timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal S.
When PI is output, the latch 210 is reset, the Q output becomes L, and the protection counter 21) is set to the initial state.

After the CY output of the protection counter 21) becomes H after the false detection signal is output once, that is, after a specified period of time (2.5 blocks), the sync detection circuit 202 and the ATF timing generator are connected via the OR gate 216. The enable clear signal to 203 becomes H, and the operation stops.

In addition, the sampling counter 215 is HS W P (A
/B) The rising edge of the signal becomes 〒1, but this is managed by the length of the tape, and if the number of false detections exceeds a certain level during that period, the CY output of the false detection counter 214 becomes H,
As a result, the Q output of the noise flag latch 213 is set to H to notify the sync detection circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent large dropouts.

Note that FIGS. 4(a) to (C) and (A) to (H) are timing charts showing the outline of signal waveforms of each part of the digital system after the initial flag latch 1) is set during playback. , corresponding symbols are attached to FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific example of the configuration of the head touch detection circuit 9201 described above.

In the figure, the comparator 1-1 has an RF multiplied signal inputted to one input, and a reference voltage +V inputted to the other input. Comparator 1-2 has an RF multiplied signal on one input,
A reference voltage -V is input to the other input.

The output of comparators 1-1 and 1-2 is OR gate 1-
3. D-type flip-flop (FF) via resistors 1-4
It is connected to the D input of 1-5 and further connected to the capacitor l-
6 to ground.

The D-type FF1-5 receives the CK large input basic clock f,4, and its Q output is connected to the input of the AND gate 1-7, and its 0 output is connected to the input of the AND gate 1-8.

The basic clocks f and 4 are input to the inputs of the AND gates 1-7 and 1-8, and their outputs are respectively connected to the UP large input and the DOWN input of the up/down counter 1-9. QA-Q of up/down counter 1-9
, the output is passed through OR gate 1-10 to AND gate 1-
8, the CY output is connected to the CK large input of the D-type FF1-1). The D input of the D-type FF1-1) is connected to VCC, and the Q output is the output of the touch detection circuit 201.

R of up/down counter 1-9 and D type FFl-1)
For input, head touch window flag latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, if the level of the comparator 1-1 is higher than the RF multiplied signal +■, the output becomes H1, and if it is lower, the output becomes L. If the level of the comparator 1-2 is higher than the RF multiplied signal -V on one side, the output becomes L if H1 is lower. That is,
When the RF multiplied signal is not within the range of ±V, the output of the OR gates 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise leaking from the output of the OR gate 1-3. The output of OR gates 1-3 from which spike-like noise has been removed by the integration circuit is a D-type FF.
Applied to the D inputs of 1-5.

The D-type FF1-5 samples the state of the D input using the basic clock applied to the CK large input and outputs the state to the Q output.The 0 output is the inverted output of the Q output.D-type FF1 The Q output of -5 is applied to the other input of AND gate l-7, which has the basic clock f, 4 applied to one input, and the Q output of D-type FF l-5 is high.
At this time, the UP large input basic clock f8 of the up/down counter 1-9 is inputted via the AND gate 1-7. Therefore, the up/down counter 1-9 counts up the basic clock fM when the Q output of the head touch window flag latch 14 is H, the window is standing, and the Q output of the D-type FF 1-5 is H.

When the Q output of the D-type FF1-5 is L, that is, when the RF multiplied signal level is within ±V and it is determined that there is no signal, the 0 output becomes H. In this state, QA-Q of up/down counter 1-9.

When any one of is H, that is, when the counter is not O, the basic clock f is D through AND gates 1-8.
1 applied to the OWN input. Up/down counter 1-9
works by counting down. Note that when the contents of the counter become 0 due to this down count or reset, and all outputs of QA-Q are L, the output of OR gate 1-10 becomes L, and AND gate 1-8
is closed, so the basic clock fM is not supplied to the DOWN power.

When the up/down counter 1-9 up-counts, a carry occurs and the CY output becomes H. This rise causes the D-type FF1-1) to memorize the state of the D input. Since the D input is H, the Q output becomes H.

6(a) to 6(J) are timing charts showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in FIG. 6(a) is input.

In a state where the RF multiplied signal is present, the amplitude is continuously greater than ±■, and in a state where there is no signal, that is, where the head is not in contact with the tape, there is almost no amplitude greater than ±■.

Note that ±■ is set to a value that makes it possible to clearly distinguish between a signal and noise.

In response to the RF multiplied signal input as shown in (a), a waveform as shown in (bl) appears in the output of the comparator l-1, and a waveform as shown in (C1) appears in the output of the comparator 1-2, respectively. And the output of OR gate 1-3 has (b
) and (c) are logically summed, and a waveform as shown in Idl appears. As is clear from the waveform in (d), there is gate leakage etc. in the output of gates 1-3. This gate leakage is removed by the integrating circuit, and the D-type FF 1-
A signal having a waveform as shown in (81) is input to the input of 5.

As a result, a waveform as shown in ff) appears in the Q output of the D-type FFl-5, and during the period when the Q output is H, the AND gate 1-
By treating 7 with the basic clock f and 4, a signal as shown in (g) appears at the output of the AND gate 1-7. On the other hand, the output of AND gates 1-8 is (hl
A signal like the one shown appears.

Incidentally, noise components slightly exceeding ±■ and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears singly, it cannot be completely removed by the integrating circuit.

The signals (gl and lh) are applied to the UP large input and DOWN input of the up/down counter 1-9, respectively.

When the up/down counter 1-9 counts a predetermined number, it sends out a carry as shown in (i) to the CY output, and in response, the D-type FF1-1) stores the D input, and the Q output becomes 0. ).

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down counters 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 7 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H3WP (A
/100) signal, basic clock f, , ATF window set signal, ATF window clear signal, noise signal, and enable clear signal are input.

A, which is supplied with the RF multiplied signal from the reproduction amplifier 15 (Fig. 1)
The TF equalizer 2-1 has a band of 400 for the ATF sync signal.
KHz to 9QOKHz is emphasized and output to the limiter 2-2. The limiter 2-2 converts the signal into an RF multiplied digital signal by setting H when the amplitude of the signal is larger than a specified level and setting it to L when it is smaller.

The output of the limiter 2-2 is supplied to the D input of the D-type FF 2-3 to which the CK large input basic clock f is input, and also to one input of the exclusive (E) OR gate 2-4. has been done.

The Q output of the D-type FF 2-3 is supplied to the other input of the EOR gate 2-4, and the EOR gate 2-4 and the D
The type FF2-3 constitutes a phase reversal detection circuit.

The ATF window set signal is sent to the ATF window latch 2- to which the ATF window clear signal is input to the R input.
5 and the ATF window latch 2-
The ATF window signal is output from the Q output of 5.

The output of the EOR gate 2-4 is the CK large input basic clock f, and the D of the 1) stage shift register 2-6 to which the ATF window signal from the ATF window latch 2-5 is input to the R input. supplied to the input. 1) The Q output of the stage shift register 2-6 is sent to the AND gate 2-8 and the AND gate 2-9 via the inverter 2-7.
2~Q.

Outputs are sent to AND gates 2-8 and 2-9, Q6 to Q8 outputs are sent to NOR gate 2-10 and AND gate 2-9, and Q
, ~Q, the outputs are respectively supplied to the NOR gates, and the outputs of the NOR gates 2-10 and 2-1) are connected to the AND gate 2-8.
and 2-9, respectively. and gate 2
The inputs of -8 and 2-9 are supplied with the inverted and previous H3WP (A/B) signals by the inverter 2-12, respectively. The outputs of AND gates 2-8 and 2-9 are supplied to the input of OR gate 2-13.

The output of OR gate 2-13 is CK large input basic clock f
D of 29-stage shift register 2-14 where M is manually operated
supplied to the input. Q of 29-stage shift register 2-14
l output is input to AND gates 2-15 to 2-20, Q, ~Q, which becomes H when sink 2, output is OR gate 2-
21 input, Q that becomes H when sink 1, ~Qll output is OR gate) 2-22 input, QIZ ~ QI4 output that becomes H when sink 2 is input to OR gate 2-23, sink 1 Q18~Qt which becomes H at both sink 2 and sink 2
.

The output is input to the OR gate 2-24, and Qz? becomes H when the sink is 1. ~Q t q output is OR gate 2-
25 inputs, respectively.

The output of OR gate 2-21 is connected to the input of AND gates 2-16 and 2-18 and the input of OR gate 2-26, and the output of OR gate 2-22 is connected to AND gates 2-15 and 2-18.
-17 input and OR gate) 2-27 input, OR gate 2-23 output is AND gate 2-16 and 2-
18 and the input of OR gate 2-26, the output of OR gate 2-24 is connected to AND gates 2-15 to 2-18.
The input of AND gate 2-27 and the output of OR gate 2-25 are respectively supplied to the input of AND gate 2-15. Also, or gate 2-26 and 2-
The output of 27 is supplied to the inputs of AND gates 2-20 and 2-19, respectively.

The H3WP (A/100) signal is applied to the AND gates 2-15, 2-17 and 2-19, and the AND gates 2-16
, 2-18 and 2-20 are supplied with the H3WP (A/100) signal inverted by the inverter 2-12, respectively. Further, the AND gates 2-15 and 2-16 are supplied with a noise-like signal, and the AND gates 2-17 and 2-18 are supplied with a noise-like signal inverted by an inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28, and the output of the OR gate 28 is output as a detection pulse signal via the AND gate 2-29. On the other hand, the outputs of the AND gates 2-15 to 2-18 are supplied to the OR gate 2-30.
The output of 30 is outputted as a sampling signal SP1 via AND gate 2-31, and the ATF enable latch 2-30 is supplied with an enable clear signal to the R input.
32 S input. ATF enable latch 2
The Q output of -32 is output as an enable signal and is also supplied to the input of ant game)2-29. The Q output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

A digital signal corresponding to sink 1 and sink 2 for ATF in the RF signal is output to the limiter 2-2, and the output of the EOR gate 2-4 becomes equal to one clock in accordance with the phase inversion of the digital signal. .

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK high input when the window signal from the ATF window latch 2-5 applied to the R input is H. In response to the rising edge of the basic clock fM, the D input is taken in and sent to the Q1 output, and after that, it is sequentially shifted every time the basic clock f, 4 rises, and Q2 to
QI, send to output. That is, shift register 2-
6 delays the output of the EOR gate 2-4 by 1 to 1) clocks and sends it to the Q, to Qll outputs.

Q. When the output is L, that is, when there is a change, this is passed through the inverter 2-7 to the AND gates 2-8 and 2.
-9 and when any one of the Q6 to Q8 outputs becomes negative, it is applied to the AND gate 2 through the Nant gate 2-10.
Set one input of -8 to H. Q2 to Q, the output is H when there is no change. At this time, H3WP (A
/100) When the signal is L, H is applied to the input of AND gate 2-8 via inverter 2-12.

In this state, all inputs of the AND gate 2-8 become H, and the output becomes H. Therefore, when this condition is not satisfied, the output remains L, does not change for at least 4 clocks, changes in 5 to 7 clocks, and H5WP
(A/100) When the signal is L and reproduction is being performed by the B head IB, 1/2 cycle of the sync 2 signal is detected.

In addition, in reality, the sink 2 signal fs (=784KH
2S fM/12), so the length that does not change is 6 clocks, but due to clock timing, jitter, etc., a margin of ±1) is allowed.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

Furthermore, from the output of the AND gate 2-9, the sink 1 signal f2 (=520KHz, f, 4
/18) is detected when the H5WP (A/B) signal is being reproduced by Hl, that is, the A head IA, and is output from the AND gate 2-9. Note that the period with no change is 7 clocks, and a change occurs between 8 and 10 clocks.

The sink 2 signal is sent from the AND gate 2-8 when the H3WP (A/100) signal is L, and the sink 1 signal is sent from the AND gate 2-9 via the OR gate 2-13 when the H3WP (A/100) signal is H. output and shift register 2-
14 D input.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock, sends it to the Q1 output, and thereafter is shifted every time the clock is applied to the state of Q2 to Q2. Sent to output.

That is, Q1 to Q2. The state of the D input is output after being delayed by 1 to 29 clocks.

When there is a change in the Q1 output of the shift register 2-14, the Q1 output becomes H. Sink 2 signal (fz = 780
KHz! /12 r, ), then Q.

If there is a change 1/2 cycle before the output, the output of the OR gate 2-21 becomes H. Further, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. or gate 2
-26 output is output from AND gate 2-20 along with Q1 output of shift register 2-14 and H3WP (A/100) signal.
is applied to the input of That is, in the case of sink 2,
After one clock delay after detecting sink 2 by AND gate 2-8, output appears at Q, and at this time 1/2
Changes before the cycle are made via or gates 1-2-21 and 2-26, and changes one cycle before are made via or gates 2-23 and 2.
-26 to the inputs of AND gates 2-20, respectively, the outputs of AND gates 2-20 go high.
Accordingly, the output of the OR gate 2-28 becomes H.

The output of the OR gates 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink is 2, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SPl via the OR gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable latch 2-32. The Q output of 2-32 becomes the H, CL ratio output L. The Q output is output as an enable signal, and
Applied to AND gate 2-29, AND gate 2-2
9, the detection pulse signal can then be output.

In the case of sink 2, when the noise signal is H,
The output of the AND gate 2-16 becomes H, and a similar operation is performed.

On the other hand, when sink 1, or gate 2-22°2-2
4 and 2-25 become H, and when the noise signal is L, the output of AND gate 2-17 becomes H, and when the noise signal is H, the output of AND gate 2-15 becomes H, and as described above. The same thing is done.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

Figures 8(a) to 8(a) are timing charts showing the waveforms of various parts during detection of sync 2, and the corresponding symbols are shown in 7th
It is attached in the figure.

Further, FIGS. 9A to 9E are timing charts showing waveforms of various parts when detecting the sync 1, and corresponding symbols are given in the figures.

FIG. 10 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
Signal, basic clock fM, H3WP (A/100) signal, enable signal, enable clear Shingetsu, back/front”
A signal, an OK double signal, an initial signal, and a detection pulse signal are input.

Enable signal to E input, CK large input basic clock f,
1, and the 0 and 25 block counters 3-1 to which enable clear signals are input to the R inputs are 9.
When a count corresponding to 5 μs is performed, the CY output becomes H, which is input to the E input of the high counter 3-2 and the C input of the decoder 3-3, respectively.

The high counter 3-2 has a CK large input basic clock f, 4,
An enable clear signal is input to each R input, and counts up every 0.25 block. The Q, .about.Q, (2.degree..about.23) outputs of the counter 3-2 are input to the decoder 3-3.

Decoder 3-3 is for decoding each time,
Only when the C input is H, the 0 to 8.16 and 17 outputs become active, and the 0 to 8 outputs send 0.25 to 2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is input to the gates 3-4 to 3-1), and the 0.5 block signal is input to the latch 3-12.
The R input of the D-type FF 313 is supplied to the CK large input, and one block signal is supplied to the CK large input of the D-type FF 3-14.

The decoder 3-15 to which the H, SWP (A/100) signal and rear/N signal are respectively input is the AT currently being reproduced.
This is for decoding the position of the F signal, and outputs the B-ATF-1, A-ATF-1, B-ATF-2 and A-ATF-2 signals to the 0 to 3 outputs, and sends this to the gate 3. −
In addition to gates 4 and 3-7, it is also supplied to gates 3-16 and 3-17.

Table 3-18, into which the H3WP (A/100) signal and the initial signal are input, has a sink-generated threshold value, and the held threshold value can be changed by the H3WP (A/B) signal and the initial signal. It is switched and set in the sync detection counter 3-19.

The H3WP (A/100) signal sets each section for sync 1 when playing A head and for sync 2 when playing B head, and each section sets 50% of the number of consecutive sync patterns.
It becomes. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-27 and inverters 3-28 to 3-30.

Then, the sample signal SP2 is output from the gate 3-10.
Erroneous detection signal at the output of gate 3-26, sample signal 5P3A at the output of gate 13-4, A at the output of gate 3-27.
The sample signal 5P3B is output to the TFEND signal and the output of the gates 3-7, respectively.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SPI, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK multiplication signal, which become H at the falling edge of the sampling signal SPI. The CY output becomes H every time. The decoder 3-3 decodes the state of the high counter 3-2, and its output becomes H only when the CY output of the 0.25 block counter 3-1 is H.

When the O output of the decoder 3-3 appears, that is, 0.25 blocks after the generation of the sampling signal SPI,
If the crosstalk sample value of one adjacent track is less than 1/2 of the on-track level, OK double signal L
Therefore, the D output of the decoder 3-3 does not appear at the output of the AND gate 3-8 which is input via the OK multiplication signal inverter 3-9. However, if there is no OK double signal, the output of AND gate 3-8 becomes H,
This is output as an erroneous detection signal from the OR game) 3-26.

When 1 output of decoder 3-3 becomes H, 0.5
As a post-blocking process, this is applied to the input of the sync detection counter 3-19 via the OR gate 3-1), and is also applied to the R input of the latch 3-12 and the D-type FF 3-1.
3 CK large input is also applied.

Since the CY output of the sync detection counter 3-19 is input to the zero input of the D-type FF 3-13 via the latch 3-12, there was a detection pulse signal greater than the specified value after 0.5 blocks. Both signals are sampled by the D-type FF 3-13. At the same time, the latch 3-12 is reset and the sync detection counter 3-12 is reset.
19, set the threshold value again from Table 3-18.

When the 3 outputs of the decoder 3-3 are H, processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF 3-14 applied to the D input via the latch 3-12. After one block, sampling is performed to determine whether there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and 3-30 determines whether a prescribed detection pulse signal is present or not based on the ODD/EVEN signal. In case of ODD, D type FF3-13.

Q outputs of 3-14 are both H, D type F in case of EVEN
When the Q output of F3-13 is H, the output of OR gate 3-25 becomes H if there is a specified detection pulse signal.

In a similar process, if the initial signal is I (
The output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore,
When the 4 outputs of decoder 3-3 are H, that is, 1.25
After blocking, when a specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-9
An erroneous detection signal of H is outputted from the output of the OR gate 3-26 via.

When the 7 output of the decoder 3-3 is H, that is, after 2 blocks, the presence of the specified detection pulse signal and the OK double signal cause the output of the AND gate 3-10 to be used for sampling other adjacent tracks. sampling signal SP
Outputs 2.

Also, with the A head, 3 of decoder 3-15 during □ playback.
After 4 blocks when the output is H and the 16 outputs of the decoder 3-3 are H, the sampling signal 5P3A is
During playback by B head, 1 output of decoder 3-15 is H.
and when the 16 outputs of the decoder are H, 5
Output P3B and sample the on-track level.

Furthermore, when the 17 output of the decoder 3-3 is H and the A head is ATF-2 and the B head is ATF-1, the ATFEND signal is output via the gates 3-17, 3-5 and 3-27.
A signal is output. Then, when the 8 outputs of the decoder 3-3 become H when the A-head is ATF-1 or the B-head is ATF-2, the ATF E N D signal is sent through the gates 3-16, 3-6 and 3-27. Output.

1) Figures (a) to (1) are timing charts showing waveforms of each part associated with the above operation, and corresponding symbols are assigned to each part.

Note that in the above-mentioned embodiment 0, only the operation of the ATF signal processing section is controlled based on the beginning part of the reproduced signal, but the S
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as OB 1 , PCM, and 5OB-2.

〔effect〕

As explained above, according to the present invention, time measurement is started in response to the pulse from the pulse generation means during recording, and
The clocking means for generating a recording start signal after measuring a second period of time is started in response to a pulse from the pulse generating means during playback, and the reproduction start signal is generated after a predetermined second period of time has been measured by the timing means. As a result, it is possible to obtain a signal that excludes the output signal that includes noise when switching the rotating head, and as a means for this purpose, the timer used to specify the recording start position during recording can be used. The configuration is simple because it uses a method.

[Brief explanation of drawings]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing main parts of the present invention,
3 and 4 are timing charts showing the signal waveforms of each part in FIG. 2, FIG. 5 is a circuit diagram showing a specific configuration of a part of FIG. 2, and FIGS. Figure 7 is a block diagram showing the specific configuration of other parts in Figure 2, Figures 8 and 9 are signal waveforms of each part in Figure 7. FIG. 10 is a circuit diagram showing the specific configuration of another part in FIG. 2, FIG. 1) is a timing chart showing the signal waveforms of each part in FIG. The diagram is R-D
FIG. 13 is a diagram showing the trunk format and block format of AT, FIG. 13 is a diagram showing the ATF track pattern of R-DAT, and FIG. 14 is a diagram for explaining the principle of tracking control using the track pattern of FIG. 13. IA, IB...rotating head, PGA, PCB...
Pulse generator, 3... system controller,
12...Initial counter, 13...Table,
13b, 13c...AND gate, 17...Decode data processing section, 18...Encode data processing section.

Claims (2)

[Claims] (1) A plurality of diagonal tracks are formed on a recording medium, and a plurality of signals, including a digital signal that has been converted into a PCM signal from an audio signal and time-axis compressed, is recorded in advance in each track by making the recording area independent in the longitudinal direction of each track. at least two recording/reproducing rotary heads for recording in a predetermined format and reproducing the plurality of signals on the recording medium, and provided in a predetermined positional relationship with respect to the two recording/reproducing rotary heads. , at least one pulse generating means that rotates together with the rotary head and generates a pulse every rotation, and alternately switches between the two rotary heads according to the pulse from the pulse generating means, so that each rotary head is activated during recording. In a device in which a plurality of signals are recorded on each track by a plurality of signals, and a plurality of signals are reproduced from each track by each rotary head during reproduction, timing is started in accordance with a pulse from the pulse generating means during recording, and a predetermined time is started during recording. a timer for generating a recording start signal after measuring a first time; and a timer for causing the timer to start measuring time in response to a pulse from the pulse generating means during playback, and for generating a recording start signal after measuring a predetermined second time. 1. A digital signal recording and reproducing device, comprising: a control means for generating a reproduction start signal to a timekeeping means; (2) Claim (1) characterized in that the second time is longer than the period during which noise occurs due to switching of the rotary head, and is sufficiently shorter than the first time.
The digital signal recording and reproducing device described in .