JPS6318503A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To prevent a noise signal from mis-detecting as a reproducing signal by providing a means detecting that a rotary head reproduces the tip part of plural signals on a track in response to a signal from a comparison means consecutive for a prescribed time. CONSTITUTION:In case of the mis-sampling, that is, an output of a comparator 107 is at L and it is discriminated that a level of a pilot signal of an ON-track is sampled and held by a S/H circuit 103 and if a prescribed value or over of a synchronizing signal does not exist, a mis-detection signal goes to H, a Q output of a latch 210 goes to H to allow a protection counter 211 to apply counting and to allow a mis-detection counter 214 to apply increment by '1'. With the level of the mis-detection signal going to H, an enable clear signal to a SYNC detection circuit 202 and to an ATF timing generator 203 goes to H, the SYNC detection circuit 202 operates the detection of a SYNC again from the start, and when a SYNC is detected, a sampling signal SP1 is outputted again. On the other hand, the ATF timing generator 203 sets a SYNC detection counter and a timer to the initial.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, and reproduces a digital signal recorded by a rotating head as diagonal tracks on a recording medium one unit at a time. The present invention relates to a digital signal reproducing device suitable for.

[Technical background of the invention and its problems]

A device that records audio signals on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotary head, and when reproducing the audio signals, converts the audio signals into PCM and records and reproduces them. There is a digital signal recording and reproducing device called R-DAT (rotating head digital audio tape recorder), which is considered as a rotary head type digital audio tape recorder.

The track format 7 actually recorded on the R-DAT has a pattern as shown in FIG. ),
The frequency of IBG is 1/6f, 4. SUB and PCM
is composed of blocks as shown in FIG. 12). 5YNC is fixed at 9 bits, and the remaining bits have various patterns depending on the location, audio signal, etc. In the case of SUB, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 12 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas located between 5UB-1 and PCM and between PCM and 5UB-2 (A T
F: Automatic Track Findi
ng) is intended to enable tracking control so that the rotary head correctly scans the recording track during reproduction using the output of the rotary head without providing a special head.

That is, the ATF area is located at the beginning and end of each track when the PCM signal is compressed in the time axis and recorded by two rotating heads diagonally forming tracks on a magnetic tape without a guard band. A PCM signal is a system in which tracking pilot signals are recorded in independent recording areas, and during playback, the recording track is scanned by a rotating head whose scanning width is wider than the width of the track, and the rotating head is scanning both adjacent tracks of the track being scanned. The reproduction output of the pilot signal from the rotary head is used to control the tracking of the rotating head.

Then, the track pattern for this ATF is the first one.
As shown in Figure 3, the pattern shown is a drum diameter of 3On+, a drum winding angle of 90@, and a rotation speed of 2.
The case of 00Orpm will be explained.

ATFl and A in the front and rear parts of each track
TF2 has a low frequency signal f1 with little azimuth effect as a pilot signal for tracking, and this detects the level of crosstalk from both adjacent tracks during playback, and detects the level of crosstalk components of both adjacent tracks. The difference is used to obtain a tracking error signal. As the pilot signal f, f, /72(13
A low frequency signal of 0 KHz) is used.

Furthermore, a sync signal for determining the position where the pilot signal f is recorded is recorded in ATFI and ATF2. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. The sync signals are different from each other in order to distinguish between the A head and the B head, with the head corresponding to +azimuth being A1 and the head corresponding to -azimuth being B, and the frequency f + for the A head. /18 (=522K) (z) sync l signal f2 has a frequency of IN/12 (=
784KHz) sink 2 signal f.

are recorded at respective predetermined positions.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. Therefore, the frequency fx /6 (-1,56MHz>
An erasure signal f, is recorded.

The positions of the ATF pilot signals are all different between the on-track and both adjacent tracks, and the level of the on-track pilot signal and the level of the biloft signals of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Each ATF area of ATF 1 and ATF 2 is 5)
The pilot signal "1" is recorded in two blocks of the block.The sync signal f!, f
, is recorded using one block or 0.5 block from the center of the position where one adjacent track is recorded. The pilot signal f of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. 1
Block sync signals are assigned to odd frames, and 0.5 block sync signals are assigned to even frames.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, when a magnetic tape recorded in the format shown in FIG. 12 (al) is reproduced with a rotary head, an RF multiplied signal as shown in FIG. 14(a) is obtained from the rotary head. If it is obtained by playing back the odd frame track (A) in Figure 13,
By passing a 130KH2 bandpass filter (BPF), a biloft signal f as shown in (bl) is obtained.
is obtained.

Section (2) is due to the on-track biloft signal, and sections (2) and (2) are due to crosstalk between the pilot signals of (B) the odd frame track and (B) the even frame track. When the rotating head is correctly scanning on-track, the envelope levels of sections ■ and ■, that is, ■■ and ■■ of IcI, should be equal, but if there is a track deviation, V■≠VI[l The amount and direction of deviation of the rotary head from on-track can be determined from the magnitude and polarity. Therefore, ■■ and VI[I
By operating the capstan servo and finely adjusting the tape speed based on the difference in the tape speed, the rotary head can be moved on-track.

In order to perform the above operation, it is necessary to detect the sync signal at a predetermined position and accurately sample the levels of v■ and ■■. However, the PCM signals in the SUB and PCM areas before and after the ATF area have the same frequency components as the pilot signal f3 and the sync signals r2 and f3. Therefore, it is necessary to accurately set the window so that the signal processing section that should operate in connection with the ATF area does not operate when it is in the SUB or PCM area.

The same can be said for the SUB and P CM areas.

Therefore, a signal from a pulse generator (PC) installed in the drum is used to generate signals for switching between the two rotating heads and for servo control of the drum motor that rotates the drum on which the rotating head is installed. It is considered that the above window can be set based on the following.

However, with this method, there is no compatibility between devices having different positional relationships between the rotary head and the PC.

Even if the machine is of the same model or the same type of equipment, the position of the window relative to each rotary head will not be constant due to manufacturing variations or changes over time, so the window must be set wide depending on the tolerance. If this is done, malfunctions are likely to occur. Of course, it is possible to set a somewhat narrow window by adjusting the window creation for each drum and head, but the adjustment work is troublesome and costly, and there are still problems in terms of compatibility with other equipment. remain.

To solve this problem, it is possible to control the processing time of each signal based on the reproduced signal, which is always in a fixed format. There was no means to detect the reproduced signal.

[Purpose of the invention]

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, an object of the present invention is to provide a digital signal reproducing device that can detect the beginning of the reproduced signal of each track based on the output signal of the rotary head after switching the rotary head. There is.

[Summary of the invention]

In order to achieve the above object, the digital playback device according to the present invention transmits a plurality of signals including a digital signal obtained by converting an audio signal into a PCM signal and compressing the time axis to each of a plurality of diagonal tracks. It has at least two rotary heads for reproducing the plurality of signals on a recording medium recorded in a predetermined format with recording areas independent in the longitudinal direction, and the two rotary heads are alternately switched and each In a device that reproduces a digital signal by processing a plurality of signals from each track reproduced by a rotary head, the level of the output signal of the rotary head after switching the rotary head is compared with a reference level of a predetermined width, and a reference level is determined. Comparing means outputs a signal when the level exceeds the level, and detecting that the rotary head is reproducing the leading end portions of the plurality of signals on the track according to the signal from the comparing means that continues for a predetermined time. and means.

This prevents signals such as noise output from being mistakenly detected as playback signals until the rotary head contacts the tape and reproduces the actual recorded signal after switching the rotary head.
, the leading part of the reproduced signal can be detected accurately.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, 1 is a rotating drum with a diameter of 30φ, and the rotating drum 1 has two rotating heads, 180@ The A head IA is spaced apart from each other.
Two pulse generators (PG) PGA and PGB are arranged at an intermediate position between the B head IB and the B head IB.

2 is a crystal oscillator that generates a 9.4MH2 basic clock "9," and the basic tarokk f8 is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system, outputs a P B/REC switching signal, and performs switching control of the toggle switch 4 consisting of switches SWI and SW2.

A reference signal generator 5 generates reference signals of XHz (66Hz: in case of 2PG), YH2 (depending on the number of FG of the capstan motor) and ZHz based on the basic clock fH applied to the CK large input.

A drum servo 6 servo-controls the rotation of the drum motor based on the reference signal XH2 under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on a reference signal ZHz under the control of the system controller 3. 8 is a capstan servo, which servo-controls the rotation of the capstan motor based on the reference signal YHz during recording when switch 4 is switched to the B contact side by the system controller 3, and switch 4 is switched to the A contact side. During playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is a HSWP (A/100) signal generator,
HSWP that switches between A head IA and B head IB based on pulses from the two PGs above (A/100)
A signal is generated, and the HSWP (A/100) signal is H and B when the head is a human head, and this is also supplied to each part of the system.

Reference numeral 10 denotes a phase reversal detection circuit, into which the basic clock f, 4, and SWP (A/B) signal applied to the CK large input are input, and the output is supplied to the S input of the initial flag latch 11. In the initial flag latch 11, the C1Y output of the initial counter 12 is input to the R input, and the Q output is supplied to the R input of the initial counter 12.

The initial counter 12 is under the control of the system controller 3, and the Q output of the initial flag latch 11 and the CK large input basic clock f8 are input to the R input, respectively, and the CY output is supplied to the R input of the initial flag latch 11. It is also supplied to the S input of the head touch window flag latch 14 via an AND gate 13 that is opened and closed under the control of the system controller 3. Further, the CY output is input to an encode data processing section 18, which will be described later.

The head touch window flag latch 14 is used to generate a window that prohibits the head touch detection operation during the noise period when switching the head.The Q output is input as an on signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, ) ISWP (A
/100) Based on the signal, encode data processing section 1 described below
Record data is received from 8 and supplied to rotary heads IA and IB via switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
2'Jt D/2'Jt D /
In addition to sending data to the A converter, head touch detection and AT
F sync detection, tracking error detection, etc. are performed, and the capstan servo 8 is output from the track deviation signal generator 17a.
An error signal is supplied to the

The encoded data processing unit 18 performs interleaving, parity addition, 8/10 conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above configuration, P from the system controller 3
A recording operation is performed when the B/REC signal is L.

Since the PB/REC signal is L, switch 4 is set to b.
The capstan servo 8 is switched to the contact side, a reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied based on the reference signal YHz, and tracking is controlled.

The H3WP (A/B) signal output by the H3WP (A/100) generator 9 based on the pulses generated by PGA and PGB due to the rotation of the drum 1 becomes H when the A head is IA and becomes L when the B spatula 11B is active. This H3WP (A/100) signal is input to the phase reversal detection circuit 10,
B) When the signal level changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H for one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial flag latch 11 is set and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic clocks f9 corresponding to a fixed period of 3.75 ms, its CY output rises, which resets the initial flag latch 11 and The rising edge of the output is applied to the encode data processing section 18 as a recording start signal. Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined format.

Next, when the P B/RE signal from the system controller 3 is H, the switch 4 is set to the a side, and the rotation
A and IB are connected to the reproduction amplifier 15 and supplied to the RF multiplied signal decode data processing section 17 .

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The amount of track deviation is an ATF error signal corresponding to the level difference of the crosstalk amplitude of pilot No. 48 on both adjacent tracks, and the details will be described later.

H5WP (A/100) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 is a reproduction mode counter, and when the count value reaches a value corresponding to, for example, 100 μs/1 ms, the CY output becomes H. This is what happens when the head is switched.
Head touch detection, which will be described later, is prohibited while an error occurs, and after the predetermined period of time, the head touch window flag latch 14 is set via the AND gate 13 to set its Q output to H, and the head touch detection is disabled. This is to output an on signal. The on signal from the head touch window flag latch 14 is sent to the decode data processing unit 1.
In 7, hendotasochi, i.e. tape T and head I
When it is detected that A or IB is in contact and the RF multiplied signal is output, the head touch window flag latch 14 is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproduction amplifier 15, a bandpass filter (BPF) 101, an envelope detector 102,
1st sample hold (S/H) circuit 103, 23rd/
H circuit 104, third S/H circuits 105a and 105b,
Toggle switch 106, comparator 107, differential amplifier 108, level correction circuit 109, and resistors R, ~R
It consists of 4.

On the other hand, the digital system includes a crystal oscillator 2, head touch detection circuit 201, sync detection circuit 202, ATF timing generator 203, playback flag latch 204, system counter 205, timing generator 206.172 frequency divider 207, ATF initial flag latch 208 ,
It consists of a power-on reset circuit 209, a latch circuit 210, a protection counter 211, a noise error latch 212, a latch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, to explain from the analog system, RF signals are input from the rotary heads IA and IB (Fig. 1) to the input of the reproduction amplifier 15, and the output is input to each input of the BPFIOl, the head touch detection circuit 215, and the sync detection circuit 216. Supplied.

BPF 101 passes only the 130 KHz component in the RF signal and inputs it to envelope detector 102 . The envelope detector 102 envelope-detects the 130 KHz component, and sends it to the S/H circuits 103, 105a, 10.
5b and the differential amplifier 108.

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SPI applied from the sync detection circuit 202 to the C input, and outputs this to one input of the comparator 107 and the output of the differential amplifier 108. Apply each. What is sampled and held by the S/H circuit 103 is the DC level of the crosstalk of the pilot signal of one adjacent track.

The S/H circuit 104 receives a signal whose level has been adjusted by the level adjustment circuit 109 at its input, samples and holds this signal using the sampling signal SP2 from the ATF timing generator 203, and outputs the signal to the capstan servo 8 (Fig. 1).
as an ATF error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The S/H circuit 105a samples and holds the output from the envelope detector 102 using the sampling signal 5P3A from the ATF timing generator 203, and outputs it to one end of the resistor R1 and the a contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105a samples and holds is the D of the on-track pilot signal when A track is played back.
It is C level.

The S/H circuit 105b samples and holds the output from the envelope detector 102 using the sampling signal 5P3B from the ATF timing generator 203, and outputs this to one end of the resistor R1 and the b contact of the switch SWI of the toggle switch 106.

What the S/H circuit 105b samples and holds is the D on-track pilot signal when B track is played back.
It is C level.

The resistors RI-Ra have the same value, and the S/H circuits 105a and 10 are added to one end of the resistors R and R1, respectively.
This is for dividing the output of 5b. The mutual connection point of the resistors R1 and R2 and the mutual connection point of the resistors R1 and R4 are respectively connected to the a contact and the b contact of the switch SW2 of the toggle switch 106. 172 levels of sample and hold values are obtained.

The toggle switch 106 is controlled by the H3WP (A/100) signal, and is switched to the a side when the H3WP (A/100) signal is H, and to the b side when it is L.

The comparator 107 has one input connected to the S/H circuit 105a.
and 1/2 level of the output of 105b is connected to resistors R7 to R4.
and is applied via the switch SW2, and the output of the S/H circuit 103 is applied to the other human power. Comparator 1
07, when 1/2 of the sample and hold values of the S/H circuits 105a and 105b is larger than the output level of the S/H circuit 103, the output becomes H, and this is sent as an OK double signal to the input of the ATF timing generator 203. supply

The differential amplifier 108 separates the output of the envelope detector 102, which is applied to the input power, and the S/D output, which is applied to the input power.
The difference between the output of the H circuit 103 and the output of the H circuit 103 is taken and inputted to the level adjustment circuit 109. That is, envelope detector 1
The output of 02 is the DC of the crosstalk of the other adjacent track.
When outputting the level, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

The level adjustment circuit 109 is the S/H circuit 105a and 105
For example, the amplification degree is changed in inverse proportion to the output level of b,
By adjusting the signal level from the differential amplifier 108, variations in the outputs of the rotary heads IA and IB are corrected.

Next, to explain the digital system, the head touch window flag latch 1 is connected to the head touch window flag latch 1.
4 (FIG. 1) and the basic clock f8, it detects that the RF multiplied signal has been input, and supplies the signal to the S input of the reproduction flag latch 204, the details of which will be described later.

The sink detection circuit 202 receives the RF multiplied signal H5WP (A/B
) signal, the ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise flag latch 212, the basic clock fM from the crystal oscillator 2
, and ORG) 216 is input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to its output. The sampling signal SPI is connected to the C input of the S/H circuit 103 and the latch 210.
The enable signal and detection pulse signal are connected to the R input of the A
Each is input to the TF timing generation circuit 203.

After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects the beginning of the ATF sync patterns SYl and SY2 of the rotating inputs IA and IB, outputs the sampling signal SPI, and then continuously outputs the negative output. The detection pulse signal is output to the sink that has been detected, and the details will be described later.

The ATF timing circuit 203 includes an OK multiplied signal which is the output of the comparator 107, an ODD/EVEN signal which is the Q output of the 1/2 frequency divider 207 (7), an initial signal which is the Q output of the ATF initial flag latch 208, and a sink detection circuit. The enable signal and detection pulse signal from 202, the after/"before" signal from timing generator 206, the enable clear signal from OR gate 216, and the basic clock f, 4 from crystal oscillator 2 are input,
Sampling signals SP2.5P3A, 5P3 are output to that output.
B, send out an erroneous detection signal and an ATFEND signal. The sampling signal SP2 is connected to the C input and A of the S/H circuit 104.
The sampling signal 5P3A is connected to the S input of the TF initial flag latch 208, and the sampling signal 5P3A is connected to the C input of the S/H circuit 105a.
The sampling signal 5P3B is connected to the C input of the S/H circuit 105b, the false detection signal is connected to the S input of the latch 210, one input of the OR gate 216, and the CK large input of the false detection counter 214, and the ATFEND signal is connected to one of the OR gates 216 and 217. Each input is done manually.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer counter (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and performs a specified If the detected pulse exceeds the specified value by the time, the sampling signal SP2
．． It outputs 5P3A and 5P3B, and operates to output an erroneous detection signal when it is below a specified value or at the L level of the OK multiplied signal which is the output of the comparator 107, and the details will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of channel bit data of the R-DAT, and outputs a basic clock f8. The basic clock f9 is applied to the CK large input of the head touch detection circuit 201, the sync detection circuit 202, the ATF timing generator 203, the system counter 205, and the protection counter 211, respectively.

The latches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes H in response to a rising edge of the S input, and whose Q output becomes L in response to a rising edge of the R input.

The output of the head touch detection circuit 201 is input to the S input of the playback flag latch 204, and the END signal which is the output of the timing generator 206 is input to the R input, and the Q output thereof is input to the R input of the system counter 205. When the Q output of the regeneration flag latch 204 is H, the regeneration operation is in progress.

The system counter 205 receives the Q output of the reproduction flag latch 204 and the CK large input basic clock fM at its R input, and its outputs Q0 to Q are input to the timing generator 206.

This system counter 205 is for roughly indicating the position on the track where each signal is recorded.

The timing generator 206 generates an STF window set signal, a rear /N signal, a window clear signal, and an END signal at its output based on the Q, -Q, and outputs from the system counter, and sends the ATF window set signal to the sync detection circuit 202. , the rear /N signal to the ATF timing generator 203, and the window clear signal to the OR gate 2.
17, and play the END signal flag latch 204
are supplied to the R inputs of This timing generator 206 decodes the output of the system counter 205 and generates the timing required for each part.

1/2 frequency divider 207 is H5WP to which CK large input is applied.
(A/100) Divide the signal by 1/2 and output OD D/E to Q output.
It generates a V E N signal and supplies it to the ATF timing generator 203 . The R input of the 1/2 frequency divider has A.
The Q output of the TF initial flag latch 208 is input.

ATF initial flag latch 208 connects AT to S input.
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. The ATF initial flag latch 208 is ATF
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The latch 210 connects the ATF timing generator 203 to the S input.
The sampling signal SPI from the sync detection circuit 202 is input to the R input, and the Q output is input to the R input of the protection counter 211. When the latch 210 detects an error, the Q output becomes H and is reset in response to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain period of time from erroneous detection, and only when the R input is H, counts the basic clock fM applied to the CK high input, and is cleared by the R input.

The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise flag latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The latch 212 receives the Q output of the latch 213 and the CY output of the large CK input sampling counter 215 at its D input, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

In the latch 213, the CY output of the false detection counter 214 is input to the S input, the CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise error flag latch 212.

The false detection counter 214 receives the false detection signal from the large CK input ATF timing generator 203 and the CY output of the sampling counter 215 at its R input, and the CY output is supplied to the S input of the latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SPI is erroneously detected during a - period, and when the value exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives CK large input H5WP (
A/B) signal is input, CY output is false detection counter 2
14, the R input of the latch 213, and the CK large input of the noise error graph 212 are respectively supplied.

The OR gate 216 connects the false detection signal from the ATF timing generator 203 and the ATFEND signal to the protection counter 21.
CY output of 1 is input, and the sync detection circuit 2 is input to that output.
02 and an enable clear signal to the ATF timing generator 203.

OR gate 217 is a window clear signal from timing generator 206, ATF timing generator 20
The ATFEND signal from the protection counter 202 and the CY output from the protection counter 211 are respectively input, and an ATF window off signal is sent to the sync detection circuit 202 at its output.

In the above configuration, the signal is passed through the RF double signal regeneration amplifier 15 to the hendotasochi detection circuit 201 and the sync detection circuit 202.
and the BPFIOI. BPF
Only the 130 KHz component of the RF multiplied signal supplied to 101 is passed. The amplitude level of the 130 KHz component is converted to a DC level by the envelope detector 102, and then applied to the inputs of each of the S/H circuits 103, 104, 105a and 105b, and the differential amplifier 108.

The envelope detector 102 sequentially outputs the DC level of the amplitude of the crosstalk of the pilot signal of one adjacent track, the amplitude of the crosstalk of the pilot signal of the other adjacent track, and the amplitude of the pilot signal of both adjacent tracks. The DC level of the amplitude of the on-track biloft signal is output before or after the signal.

The S/H circuit 103 samples and holds the DC level of the pilot signal of one adjacent track at the timing of the sampling signal SPI from the sync detection circuit 202.

The crosstalk level of one adjacent track sampled and held is determined by the comparator 107 and the differential amplifier 10.
It is applied to B's single power.

The S/H circuit 105a converts the DC level of the on-track pilot signal during playback of +azimuth A track to the S/H circuit 105a.
The circuit 105b samples and holds the DC level of the on-track pilot signal during the reproduction of the -azimuth B track. The output of the S/H circuit 105a, that is, the DC level of the on-track pilot signal is:
It is supplied to the control input of the level adjustment circuit 109 through the a contact of the switch SWI of the toggle switch 106, and after being divided into 1/2 by the resistors R1 and R2, it is supplied to the comparator through the a contact of the switch SW2. 107. Similarly, the output of the S/H circuit 105b is sent to the level adjustment circuit 109 via the b contact of the switch SWI, and after being divided into 1/2 by resistors R3 and R4, the output is sent to the level adjustment circuit 109 via the b contact of the switch S W 2. It is supplied to one input of comparator 107.

The comparator 107 becomes an OK multiplied signal H when the level input via the switch SW2 is higher than the input from the S/H circuit 103. In other words, it is determined that the crosstalk level of one adjacent track has been correctly sampled. In the opposite case, it is determined that the on-track level has been sampled. Therefore, when the OK double signal is L, it is determined that the sync has been erroneously detected. This OK double signal is supplied to the ATF timing generator 203.

When the envelope detector 102 is outputting the DC level of the crosstalk amplitude of the other adjacent track, the differential amplifier 108 inputs the DC level of the crosstalk amplitude of one adjacent track. , the output is the difference in the DC level of the Kukostalk of both adjacent tracks,
That is, the amount of track deviation is obtained, and this is input to the level adjustment circuit 109.

The level adjustment circuit 109 is the S/H circuit 105a and 105
The output of b is applied as a control input, and when the control input is large, the level of the input signal is lowered, and when it is small, it is raised and output.

In short, the level adjustment circuit 109 automatically corrects variations in the outputs of the two rotary heads, and the output of the S/H circuit 104 that is input to the next S/H circuit IQ4 is corrected by the sampling signal SP2. Sample and hold the amount of track deviation. The output of this S/H circuit 104 is supplied to the capstan servo 8.

FIGS. 3(a) to 3(1) are timing charts showing signal waveforms generated in each part by the above operations, corresponding to the reference numerals given to each part.

The H5WP (A/100) signal shown in Figure 3 ('b) is +
The signal becomes H when the azimuth is reproduced by the A head IA, and becomes L when the azimuth is reproduced by the B head IB. H when the head does not switch
The phase of the 3WP (A/B) signal is inverted. When the phase is reversed, the Q of the initial flag latch 11 (Fig. 1)
The output becomes H and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is judged that the tape has passed a noisy portion, and the head touch window flag latch 14 (FIG. 1) is set to set its Q output to H. Q output of head touch window flag latch 14 is H
Then, the head touch detection circuit 201 operates.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF multiplied signal is reproduced, its output becomes H.
, set the regeneration flag latch 204 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 outputs the ATF window set signal to the sync detection circuit 2 based on the Q0 to Q outputs of the system counter 205 and outputs the ATF window set signal slightly before the recordings of ATF-1 and ATF-2.
Supply to 02.

After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects sync 1 (= f
Each sync is detected based on the fact that the patterns of sync 2 (fz) and sync 2 (fz) in the case of B head IB have the relationships shown in the table below depending on the frame.

Here, when the sync detection circuit 202 detects 4 syncs in the normal case or 5 syncs in the noisy case, it outputs the sampling signal SPI, and sends the S/H circuit 103 to the crosstalk of the pilot signal r1 of one adjacent track. The level of the ATF timing orderer 203 is sampled and held, and an enable signal is supplied to the ATF timing orderer 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SPI is output from the sync detection circuit 202.
Check whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI. Next 1.2
After 5 blocks, it is determined whether the sync is detected at a specified value or more, and if it is above the specified value, it is assumed that the sync has been detected correctly and the sampling signal SP2 is sent to S/H after 2 blocks.
The signal is supplied to a circuit 104 to sample and hold the crosstalk level difference between both adjacent tracks, and its output is supplied to the capstan servo 8 as the amount of track deviation.

In addition, if the on-track pilot signal f exists after the sync, when playing back by A to Rad IA, A
Since TF-2 and B heads are being played back at ATF-1, in this case, the sampling signals 5P3A and 5P3B are output after 4 blocks, and these are supplied to the S/H circuits 105a and S/H 105b, respectively. Sample and hold the level of the on-track pilot signal being played by each head.

If the above series of operations are performed correctly, ATFEND
A signal is output, which is passed through the OR gate 216 as an enable clear signal to the sink detection circuit 202 and the AT.
It is supplied to the F timing generator 203. ATFEND
The signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. .

Missampling, that is, the output of the comparator 107 is L, and the level of the on-track pilot signal is S/H.
If it is determined that the circuit 103 has sampled and held,
If the sink is not equal to or greater than the specified value, the erroneous detection signal is set to H, the Q output of the latch 210 is set to H, and the protection counter 211 is caused to perform a counting operation, and the erroneous detection counter 214 is caused to perform a +1 operation. When the false detection signal becomes H, the enable clear signal to the sink detection circuit 202 and ATF timing generator 203 via the OR gate 216 also becomes H.

When the enable clear signal becomes H, the sink detection circuit 2
02 performs the operation of detecting the sync again from the beginning, and once the sync is detected, outputs the sampling signal SP1 again. On the other hand, the ATF timing generator 203 sets the sync detection counter and timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal S.
When PI is output, the latch 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the CY output of the protection counter 211 becomes H after the erroneous detection signal is output once, that is, after a specified time (2.5 blocks), the sync detection circuit 202 and the ATF timing generator 203 are connected via the OR gate 216. The enable clear signal to becomes H, and the operation stops.

The sampling counter 215 increases by 1 at the rising edge of the HSWP (A/100) signal, but this is because the tape is managed by length, and if the number of false detections exceeds a certain level during that period, the false detection counter 214 increases. The CY output becomes H, which causes the Q output of the noise error flag graph 213 to become H, thereby informing the sink noise output circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent large dropouts.

In addition, FIG. 4 (al to (C1) and (A) to (H) are timing charts showing the outline of the signal waveforms of each part of the digital system after the initial flap flap 11 is set during playback. The reference numerals are given in FIGS. 1 and 2.

FIG. 5 is a block diagram showing a specific example of the configuration of the head touch detection circuit 201 described above.

In the figure, the comparator 1-1 has an RF multiplied signal inputted to one input, and a reference voltage +■ to the other input. Comparator 1-2 is -4 human power and RF multiplied signal,
The reference voltage -■ is input to the other input.

The output of comparators 1-1 and 1-2 is OR gate 1-
3. D-type flip-flop (FF) via resistors 1-4
1-5 and is further connected to the D input of capacitor 1-5.
6 to ground.

The D-type FF 1-5 receives the CK large input basic clock fM, and its Q output is connected to the input of the AND gate 1-7, and its 0 output is connected to the input of the AND gate 1-8.

The basic clocks f and 4 are input to the inputs of the AND gates 1-7 and 1-8, and their outputs are respectively connected to the UP large input and the DOWN input of the up/down counter 1-9. QA of up/down counter 1-9 = Q
n output is passed through OR gate 1-10 to AND gate 1-
The CY output is connected to the CK input of the D-type FF1-11, respectively. The D input of the D type FF1-11 is connected to VCC, and the Q output is the output of the touch detection circuit 20'1.

R of up/down counter 1-9 and D type FF1-11
For input, head touch window flag latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, if the level of the comparator 1-1 is higher than the RF multiplied signal +V, the output becomes H1, and if it is lower, the output becomes L. If the level of the comparator 1-2 is higher on one side than the RF multiplied signal 1, the output becomes L if H1 is lower. That is,
When the RF multiplied signal is not within the range of ±V, the output of the OR gates 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise leaking from the output of the OR gate 1-3. The output of the OR gate 1-3 from which spike noise has been removed by the integration circuit is a D-type FFl.
-5 is applied to the D input.

The D-type FF1-5 samples the state of the D input using the basic clock f,4 applied to the CK large input, and outputs the state to the Q output. The output is the inverted output of the Q output. The Q output of D-type FFl-5 is the basic clock r1
4 is applied to one input of the AND gate 1-7, and when the Q output of the D-type FF1-5 is H, the up/down counter 1 is applied to one input of the AND gate 1-7. -9 UP large input basic clock fM is input. Therefore, the up/down counter 1-9 indicates that the Q output of the head touch window flag latch 14 is H and the window is standing, and the Q output of the D-type FF 1-5 is H.
At this time, the basic clock f8 is counted up.

When the Q output of the D-type FF1-5 is L, that is, when the RF multiplied signal level is within ±V and it is determined that there is no signal, the output becomes H. In this state, QA to Q of the up/down counter 1-9.

When any one of is H, that is, when the counter is not 0, the basic clock f8 is input to
It is applied to the OWN input, and the up/down counters 1-9 perform a down-count operation. In addition, due to this down count or reset, the contents of the counter become 0 and Q
When all of the outputs of A-Q are low, the output of OR gate 1-10 is low and AND gate 1-8 is closed, so that basic clock fH is not supplied to the DOWN input.

When the up/down counter 1-9 counts up, a carry occurs and the CY output becomes H, and this rise causes the D-type FF1-11 to memorize the state of the D input. Since the D input is H, the Q output becomes H.

FIGS. 6(al) to (j) are timing charts showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in (al) is input.

Continuously stops when the RF double signal is present.V
The amplitude is larger, and in the absence of a signal, that is, when the head is not in contact with the tape, the
Larger amplitudes are almost non-zero. Note that ±■ is set to a value that allows the signal and noise to be clearly distinguished.

In response to the RF multiplied signal input as shown in (8), the output of comparator 1-1 has the waveform shown in (b), and the output of comparator 1-2 has the waveform shown in (C). appear. And the output of OR gate l-3 has fb
) and (C), a waveform as shown in (dl) appears.As is clear from the waveform (d), there is gate leakage etc. in the output of gates 1-3. Gate leakage etc. are removed by the integration circuit, and the D-type FF1-5
A signal having a waveform as shown in Te) is inputted to the input of .

As a result, a waveform as shown in (f) appears in the Q output of D-type FF1-5, and the period when the Q output is H is AND gate 1-5.
When the basic clock f, 4 passes through 7, a signal as shown in (h) appears at the output of AND gates 1-7.On the other hand, a signal as shown in (h) appears at the output of AND gates 1-8. A signal appears.

Incidentally, noise components slightly exceeding ±■ and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears in bursts, the integrating circuit cannot completely remove it.

Signals (gl and fhi are applied to the UP large input and DOW N input of the up/down counter 1-9, respectively.

When the up/down counter 1-9 counts a predetermined number, it sends out a carry as shown in (1) to the CY output, and in response, the D-type FF1-11 stores the D input, and the Q output becomes ('' ).

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down counters 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 7 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H3WP (A
/100) signal, basic clock f, ATF window set signal, ATF window clear signal, noise signal, and enable clear signal are input.

A, which is supplied with the RF multiplied signal from the reproduction amplifier 15 (Fig. 1)
The TF equalizer 2-1 has a band of 400 for the ATF sync signal.
KHz to 900 KHz is emphasized and output to the limiter 2-2. The limiter 2-2 converts the signal into an RF multiplied digital signal by setting H when the amplitude of the signal is larger than a specified level and setting it to L when it is smaller.

The output of limiter 2-2 is CK large input basic clock f,
4 is supplied to the D input of the D-type FF 2-3, and also to one input of the exclusive (E) OR gate 2-4.

The other input of the EOR gate 2-4 is supplied with the Q output of the D-type FF 2-3, and the EOR gate 2-4 and the D
The type FF2-3 constitutes a phase reversal detection circuit.

The ATF window set signal is sent to the ATF window latch 2- to which the ATF window clear signal is input to the R input.
5 S human power is supplied, the ATF window luff 2-
The ATF window signal is output from the Q output of 5.

The output of the EOR gate 2-4 is supplied with the CK large input basic clock fH to the D input of an 11-stage shift register 2-6 whose R input receives the ATF window signal from the ATF window latch 2-5, respectively. Ru. The Q1 output of the 11-stage shift register 2-6 is passed through the inverter 2-7 to the AND gate 2-8 and the AND gate 2-9.
2~Q.

The outputs are output to AND gates 2-8 and 2-9, Q, ~QI!
The output is to NOR gate 2-10 and AND gate 2-9,
The Q, ~Ql+ outputs are respectively supplied to the NOR gates, and the outputs of the NOR gates 2-10 and 2-11 are fed to the AND gate 2.
-8 and 2-9, respectively. The inputs of the AND gates 2-8 and 2-9 are supplied with the inverted and previous H3WP (A/100) signals by the inverter 2-12, respectively. The outputs of AND gates 2-8 and 2-9 are supplied to the input of OR gate 2-13.

The output of OR gate 2-13 is CK large input basic clock r
D of the 29-stage shift register 2-14 to which H is input
supplied to the input. Q of 29-stage shift register 2-14
1 output is input to AND gates 2-15 to 2-20, Q, ~Q, which becomes H when sink 2, output is OR gate 2-
21 input, the Q, ~Ql+ output that becomes H when sink 1 is input to the input of OR gate 2-22, and the Q1□~Q14 output that becomes H when sink 2 is input to the input of OR gate 2-23. Q111 to Q that are H on both sinks 2
2゜output is ORGATE) 2-24 human power, and Qz7~Q29 output that becomes H when sink 1 is ORGATE 2-
25 inputs, respectively.

The output of OR gate 2-21 is the human power of AND gates 2-16 and 2-18, and the human power of OR gate 2-26, and the output of OR gate 2-22 is the human power of AND gates 2-16 and 2-18, and the output of OR gate 2-22 is
-17 and the input of OR gate 2-27, the output of OR gate 2-23 is connected to AND gate 2-16 and 2-
18 and the input of OR gate 2-26, the output of OR gate 2-24 is connected to AND gates 2-15 to 2-18.
and the input of OR gate 2-27, and the output of OR gate 2-25 is supplied to the input of AND gate 2-15, respectively. Also, or game) 2-26 and 2-
The output of 27 is supplied to the inputs of AND gates 2-20 and 2-19, respectively.

The above AND gates 2-15, 2-17 and 2-19 have the H3WP (A/100) signal, and the AND gates 2-16
, 2-18 and 2-20 are supplied with the H3WP (A/100) signal inverted by the inverter 2-12, respectively. Further, a noisey signal is supplied to AND gates 2-15 and 2-16, and a noisey signal inverted by an inverter 2-28 is supplied to AND gates 2-17 and 2-18, respectively.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28, and the output of the OR gate 28 is output as a detection pulse signal via the AND gate 2-29. On the other hand, the outputs of the AND gates 2-15 to 2-18 are supplied to the OR gate 2-30.
The output of 30 is outputted as a sampling signal SP1 via AND gate 2-31, and the ATF enable latch 2-30 is supplied with an enable clear signal to the R input.
32 S input. ATF enable latch 2
The Q output of -32 is output as an enable signal and is also supplied to the input of AND gate 2-29. The 0 output is supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

A digital signal corresponding to ATF sync 1 and sync 2 in the RF signal is output to the limiter 2-2, and the output of the EOR gate 2-4 corresponds to one clock in accordance with the phase inversion of the digital signal.

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK high input when the window signal from the ATF window latch 2-5 applied to the R input is H. In response to the rising edge of the basic clock f, l, the D input is taken in and sent to the Q, output, and thereafter it is shifted sequentially at each rising edge of the basic clock f, 4.
~ Send to Qll output. That is, shift register 2
-6 delays the output of the EOR gate 2-4 by 1 to 11 clocks and sends it to the Ql-QII output.

Q. When the output is L, that is, when there is a change, this is passed through the inverter 2-7 to the AND gates 2-8 and 2.
-9, and when any one of the Q h "" Q * outputs becomes low, one input of the AND gate 2-8 becomes H via the Nandt gate 2-10. Q2 to Q, the output is H when there is no change. At this time, H5
If WP (A/B) signal is present, inverter 2-
H is applied to the input of AND gate 2-8 via 12.

In such a state, all inputs of the AND gate 2-8 become H, and the output power becomes <H. Therefore, when this condition is not satisfied, the output remains L, does not change for at least 4 clocks, changes for 5 to 7 clocks, and H5WP
(A/100) When the signal is L and reproduction is being performed by the B head IB, 1/2 cycle of the sync 2 signal is detected. In addition, in reality, the sink 2 signal fx (=784K
Hz-fH/12), so there is a length of 6 clocks that does not change, but there is a margin of ±11 clocks due to the clock timing, shifter, etc.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

In addition, from the output of AND gate 2-9, the sink 1 signal “2 (=520KHz, fx
/18) is detected when the H3WP (A/100) signal is being reproduced by Hl, that is, the A head IA, and is output from the AND gate 2-9. Note that the period with no change is 7 clocks, and a change occurs between 8 and 10 clocks.

The sink 2 signal is sent from the AND gate 2-8 when the H3WP (A/100) signal is L, and the sink 1 signal is sent from the AND gate 2-9 via the OR gate 2-13 when the H3WP (A/100) signal is H. output and shift register 2-
14 D input.

The 29-stage shift register 2-14 stores the state of the D input at the rising edge of the clock, sends it to the Q1 output, and thereafter is shifted every time the clock is applied to the state of Q2 to Q2. Sent to output.

That is, Ql x Q, the state of the D input is output with a delay of 1 to 29 clocks.

When there is a change in the Q1 output of the shift register 2-14, the Q output becomes H. Sink 2 signal (fs = 780
KHz, 1/12 rs), if there is a change 1/2 period before the Q1 output, the or game 1
-2-21 output becomes H. Further, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. or gate 2-2
The output of 6 is the Q1 output of shift register 2-14 and H3
It is applied to the input of the AND gate 2-20 together with the WP (A/B) signal. In other words, in the case of sink 2, the output appears at Q after one clock delay after detecting sink 2 by AND gate 2-8, and at this time, the change 1/2 period before is detected by OR gates 2-21 and 2-26. Via
Also, the changes one cycle ago are OR gates 2-23 and 2-26.
When applied simultaneously to the inputs of the AND gates 2-20 through the respective AND gates, the output of the AND gates 2-20 becomes H, and accordingly, the output of the OR gates 2-28 becomes H.

The output of 2-21, 2-23 and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink 2 is set, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SP1 via the AND gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable latch 2-32. The Q output of enable latch 2-32 becomes H and the Q output becomes L. The Q output is output as an enable signal and is applied to the AND gate 2-29.
After that, the detection pulse signal can be outputted.

In the case of sink 2, when the noise signal is H,
The output of the AND gate 2-16 becomes H, and a similar operation is performed.

On the other hand, when sink l, or gate 2-22.

When the outputs of 2-24 and 2-25 become H, and the noise signal is L, the output of AND gate 2-17 becomes H, and when the noise signal is H, the output of AND gate 2-15 becomes H, The same thing as described above is done.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

FIG. 8 (al to (gl) is a timing chart diagram showing waveforms of various parts during detection of the sink 2, and corresponding symbols are given in FIG. 7.

Further, FIGS. 9A to 9E are timing charts showing waveforms of various parts when detecting the sync 1, and corresponding symbols are given in the figures.

FIG. 10 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
Signals, basic ratio f, 4, H3WP (A/100) signal, enable signal, enable clear signal, rear/"front" signal, OK signal, initial signal, and detection pulse signal are input.

Enable signal to E input, CK large input basic clock f,
4, and the 0 and 25 block counters 3-1 to which the enable clear signal is input to the R inputs are 9.
When a count corresponding to 5 μs is performed, the CY output becomes H, which is input to the E input of the high counter 3-2 and the C input of the decoder 3-3, respectively.

High counter 3-2 is clocked by CK, basic clock f, R
An enable clear signal is input to each input, and count amplification is performed every 0.25 blocks. Q of the counter 3-2. -Qyu (2' to 23) The output is input to the decoder 3-3.

Decoder 3-3 is for decoding each time,
The 0-8.16 and 17 outputs are active only when the C input is H, and the 0-8 outputs send 0.25-2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is input to the gates 3-4 to 3-11, and the 0.5 block signal is input to the latch 3-12.
R input, D type FF3-130) CK large input is supplied,
(2) The block signal is supplied to the CK large input of the D-type FF3-14.

The decoder 3-15 to which the H3WP (A/100) signal and the rear/both signals are respectively input is the ATF currently being reproduced.
This is for decoding the position of the signal, and outputs the B-ATF-1, A-ATF-1, B-ATF-2 and A-ATF-2 signals to the 0 to 3 outputs, and sends this to the gate 3-3. 4
and 3-7 as well as gates 3-16 and 3-17.

Table 3-18, in which the H3WP (A/100) signal and the initial signal are input, holds the sink detection threshold value, and the held threshold value is switched by the H3WP (A/100) signal and the initial signal. and sets it in the sync detection counter 3-19.

The H3WP (A/100) signal sets each section for sync 1 when playing A head and for sync 2 when playing B head, and each section sets 50% of the number of consecutive sync patterns.
It becomes. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-27 and inverters 3-28 to 3-30.

Then, the sample signal SP2 is output from the gate 3-10.
Erroneous detection signal at the output of gate 3-26, sample signal S P 3 A at the output of gate 3-4, ATFEND signal at the output of gate 3-27, and sample signal 5P3B at the output of gate 3-7. Output each.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SPI, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK multiplication signal, which become H at the falling edge of the sampling signal SPI. The CY output becomes H every time. The decoder 3-3 decodes the state of the high counter 3-2, and its output becomes H only when the CY output of the 0.25 block counter 3-1 is H.

When the 0 output of the decoder 3-3 appears, that is, 0.25 blocks after the generation of the sampling signal SPI,
If the crosstalk sample value of one adjacent track is less than 1/2 of the on-track level, OK double signal L
Therefore, the D output of the decoder 3-3 does not appear at the output of the AND gate 3-8 which is input via the OK multiplication signal inverter 3-9. However, if there is no OK double signal, the output of AND gate 3-8 becomes H,
This is output from the OR gate 3-26 as an erroneous detection signal.

When 1 output of decoder 3-3 becomes H, 0, 5
As processing after blocking, this is applied to the L input of the sink detection counter 3-19 via the OR gate 3-11, and is also applied to the R input of the latch 3-12 and the D-type FF 3-1.
3 CK large input is also applied.

Since the CY output of the sync detection counter 3-19 is input to the D input of the D-type FF 3-13 via the latch 3-12, it is determined whether there is a detected pulse signal greater than the specified value after 0.5 blocks. This will be sampled by the D-type FF3-13. At the same time, the latch 3-12 is reset and the sync detection counter 3-12 is reset.
19, set the threshold value again from Table 3-18.

When the 3 outputs of the decoder 3-3 are H, processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF 3-14 applied to the D input via the latch 3-12. After one block, sampling is performed to determine whether there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and 3-30 determines whether or not a prescribed detection pulse signal is present based on the ODD/EVEN signal. In the case of ODD, the Q outputs of D type FF3-13゜3-14 are both H,
In the case of EVEN, when the Q output of the D-type FF 3-13 is H, the output of the OR gate 3-25 becomes H if there is a specified detection pulse (No. 8).

In similar processing, when the initial signal is H, the output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore,
When the 4 outputs of decoder 3-3 are H, that is, 1.25
After blocking, when a specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-9
An erroneous detection signal of H is output from the output of the OR gates 3 and -26.

When the 7 output of the decoder 3-3 is H, that is, after 2 blocks, it means that the specified key output pulse signal is present and OK.
Sampling signal S for sampling other adjacent tracks to the output of 3-10
Output P2.

Also, after 4 blocks when the 3rd output of the decoder 3-15 is H during playback by the head and the 16th output of the decoder 3-3 is H, the sampling signal 5P3A is changed to B
When the 1st output of decoder 3-15 is H during playback by the head and the 16th output of decoder is H, 5P
Output 3B and sample the on-track level.

Furthermore, when the 17 output of the decoder 3-3 is H and the A head is ATF-2 and the B head is ATF-1, the ATFEND signal is output via the gates 3-17, 3-5 and 3-27.
A signal is output. Then, when the 8 outputs of the decoder 3-3 become H when the A-head is ATF-1 or the B-head is ATF-2, the ATFEND signal is output via the gates 3-16, 3-6 and 3-27. .

FIG. 11 (al~(11 is a timing chart showing waveforms of each part associated with the above operation, and corresponding symbols are assigned to each part.

Note that in the above embodiment, only the operation of the ATF signal processing section is controlled based on the beginning part of the reproduced signal, but the SU
Similar control can be applied to the operation of the signal processing unit that processes PCM data such as B 1 , PCM, and 5UB-2.

〔effect〕

As explained above, according to the present invention, the level of the output signal of the rotary head after switching of the rotary head is compared with a reference level of a predetermined width, and whether the duration of the signal exceeding the reference level is longer than a predetermined time? Since the leading portion of the reproduced signal is detected from the output signal depending on whether the output signal is present or not, the leading portion of the reproduced signal can be accurately detected without erroneous detection due to noise or the like.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing main parts of the present invention,
3 and 4 are timing charts showing the signal waveforms of each part in FIG. 2, FIG. 5 is a circuit M showing a specific configuration of a part of FIG. 2, and FIG. FIG. 7 is a block diagram showing the specific configuration of other parts in FIG. 2. FIGS. 8 and 9 are timing chart diagrams showing signal waveforms of each part in FIG. FIG. 10 is a circuit diagram showing a specific configuration of another part in FIG. 2, FIG. 11 is a timing chart showing signal waveforms of each part in FIG. 10, and FIG. R-DA
FIG. 13 is a diagram showing the ATF rank pattern of R-DAT, and FIG. 14 is a diagram for explaining the principle of tracking control using the track pattern of FIG. 13. . IA, IB...rotating belly button)', 201... head touch detection circuit, I-1, 1-2... comparator, 1
-4.1-6...Integrator circuit, 1-9...Up/down counter, ±■...Reference voltage.

Claims (1)

[Claims] Audio signals are transmitted to each of a plurality of diagonal tracks by a PC.
At least a method for reproducing the plurality of signals on a recording medium in which a plurality of signals including digital signals converted into M signals and time axis compressed are recorded in a predetermined format with independent recording areas in the longitudinal direction of each track. In a device that has two rotating heads and alternately switches between the two rotating heads and processes a plurality of signals from each track reproduced by each rotating head to reproduce a digital signal, after switching the rotating heads. comparing means for comparing the level of the output signal of the rotating head with a reference level of a predetermined width and outputting a signal when the level exceeds the reference level; A digital signal reproducing apparatus comprising: means for detecting that leading portions of a plurality of signals on the track are being reproduced.