JPS6364660A - Digital signal reproducing device - Google Patents

Abstract

PURPOSE:To prevent the disturbance of a capstan servo by deciding whether a sampled level is appropriate or not and insuring a capstan servo control due to the level difference of an unappropriate cross talk against being executed. CONSTITUTION:A signal RF from a rotating head is inputted to an envelope detector 102 through a reproduction amplifier 15, and a BPF 101. A sample holding circuit 103 sample-holds the output of the detector 102 and impresses it on the one out of differential amplifiers 108. The amplifier 108 outputs the difference between the outputs of the detector 102 and the circuit 103, that is, a track drift amount, and outputs it to a sample holding circuit 104. It sample-holds the output with the aid of a sampling signal SP2 from an ATF timing generator 203, and outputs it as an ATF error signal to the capstan servo. If the output of the detector 102 is larger than a prescribed level, a comparator 107 stops outputting a signal OK to the generator 203. Consequently the generator 203 stops supplying the signal SP2 to the circuit 104.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention converts an audio signal into a PCM signal, and reproduces the digital signal recorded by a rotating head as one diagonal track on a recording medium for each unit of time. This invention relates to a digital signal reproducing device suitable for.

[Technical background of the invention and its problems]

A device that records audio signals on a magnetic tape by forming one diagonal track every unit time using a helical scan type rotary head, and when reproducing the audio signals, converts the audio signals into PCM and records and reproduces them. There is a digital signal recording and reproducing device called DAT (rotating head digital audio tape recorder), which is considered as a digital audio tape recorder.

The track formant actually recorded in R-DAT has a pattern as shown in FIG.
MHz), the frequency of the IBG is 1/6 f14. The SUB and PCM are composed of blocks as shown in FIG. 14('b). 5YNC is 10 focus (
(fixed at 9 bits), and the remaining patterns vary depending on the location, audio signal, etc. In the case of SUB, this block is repeated 8 times, and in the case of PCM, this block is repeated 128 times. Note that in FIG. 14 (the numbers in al represent the number of blocks occupied by each area).

The ATFI and ATF2 areas located between 5UB-1 and PCM and between PCM and 5UB-2 (A T
F: Automatic Track Findi
ng) is intended to enable tracking control so that the rotary head correctly scans the recording track during reproduction using the output of the rotary head without providing a special head.

That is, the ATF area is located at the beginning and end of each track when the PCM signal is compressed in the time axis and recorded by two rotating heads diagonally forming tracks on a magnetic tape without a guard band. A PCM signal is a system in which tracking pilot signals are recorded in independent recording areas, and during playback, the recording track is scanned by a rotating head whose scanning width is wider than the width of the track, and the rotating head is scanning both adjacent tracks of the track being scanned. The reproduction output of the pilot signal from the rotary head is used to control the tracking of the rotating head.

Then, the track pattern for this ATF is the first one.
The pattern shown is as shown in Figure 5, with a drum diameter of 30 liters, a drum winding angle of 90'', and a rotation speed of 2.
The case of 000 rpm will be explained.

ATFl and A in the front and rear parts of each track
TF2 has a low frequency signal f1 with little azimuth effect as a pilot signal for tracking; 1. This is used to detect the level of crosstalk from both adjacent tracks during playback, and to obtain the level difference between the crosstalk components of both adjacent tracks as a tracking error signal. fM/72 as the above pilot signal f1
A low frequency signal of (130 KHz) is used.

Further, in ATF1 and ATF2, a sync signal for determining the position where the pilot signal f is recorded is recorded. Since it is difficult to distinguish between on-track and adjacent tracks when there is crosstalk in the sync signal, a sync signal is selected that has a frequency with an azimuth effect and a pattern that does not exist in the PCM signal. Assuming that the head corresponding to +azimuth is A and the head corresponding to -azimuth is B, the sync signal is different from each other to distinguish between A head and B head, and the frequency for A head is different. Sink 1 signal f2 of fM/18 (=522KHz)
However, for the B head, the frequency is f+ /12 (=78
4KH2) sink 2 signal f.

are recorded at respective predetermined positions.

The R-DAT is not provided with an erasing head, and signals are rewritten by overwriting the previous recording, so-called override. For this reason, the pilot signal fl− of the previous recording,
Frequency f, 4/6 (= 1.56
MHz) erasure signal r4 is recorded.

The positions of the ATF pilot signals are all different between the on-track and both adjacent tracks, and the level of the on-track pilot signal and the level of the pilot signal of both adjacent tracks are different in time, and three types of levels are sampled. It is arranged so that you can

Five blocks are allocated to each of the ATF areas ATF 1 and ATF2, and the pilot signal f1 is recorded in two of the blocks. Sink signals ft, f
, are recorded using one block or 0.5 block from the center of the position where one adjacent track is recorded. The pilot signal f of the other adjacent track is recorded so that its center is located two blocks after the beginning of the sync signal recorded on the on-track. 1 block of sync signals are assigned to odd frames, and 0.5 blocks of sync signals are assigned to even frames.

As described above, in the ATF, the frequency of the sync signal differs depending on the A head and the B head, and the recording length of the sync signal differs between odd frames and even frames. Therefore, since all four consecutive tracks are given different ATFs,
It is possible to distinguish. The ATF pattern described above is a 4-track complete type that is repeated every 4 tracks.

By the way, when a track of a magnetic tape recorded in the formant shown in FIG. 14(a) is reproduced by each rotary head, an R as shown in FIG.
An F-fold signal is obtained. For example, if this RF multiplied signal is obtained by reproducing the odd frame track (A) in FIG.
F), a pilot signal f as shown in ('b) is obtained.

Section I is due to on-track pilot signals, and sections ■ and ■ are due to crosstalk between pilot signals of (B) odd frame tracks and (B) even frame tracks. When the rotating head is correctly scanning on-track, the envelope levels of sections ■ and ■, that is, ■■ and V■ of (C1) should be equal, but if there is a track deviation, ■■≠■■ Then,
The amount and direction of deviation of the rotary head from on-track can be determined by its magnitude and polarity. Therefore, by operating the capstan servo and adjusting the tape speed by 1 m based on the difference between ■■ and ■■, the rotary head can be run on-track.

However, as mentioned above, R-DAT does not have an erase head and performs the second and third recording by override, so it accurately detects the sync signal and samples ■ and ■ to generate the correct error signal. cannot occur (
Something happened.

That is, in R-DAT, recording can be performed within ±22 blocks from the center of the PCM area. Further, the recording level of the pilot signal fl (=130 KHz) is to be slightly lower than the level of other signals. This is because low frequency signals are recorded at a deep level on the tape so that the pilot signal f1 recorded in the override area can be erased by the erase signal. However, if the level of the pilot signal f is lowered in this way, when a new pilot signal f is recorded at the previously recorded sync signal f2 or f3, the previous sync signal will not be completely erased. Sometimes it remains.

Specifically, when a later recording is performed ahead of the previous recording, the sync signal of the later recording always precedes the unerased sync signal of the previous recording on the track. Therefore, there is no problem, but if the later recording is shifted backward, the unerased sync signal will come to precede the sync signal of the later recording. An example of this is when there is a deviation of 1 to 2 blocks later, and the AT
For F-1, one of the sync signals f2sf3 of the previous recording is added to the pilot signal f1 in (A) even frames and (A) odd frames, and for ATF-2, in (B) even frames and (B) odd frames. Part or all of it will remain.

When this happens, the level of the frequency component of the pilot signal in the reproduced RF signal at that time is sampled according to the sync signal of the previous recording. Although this pilot signal should originally be at the crosstalk level of the sampling signal of one adjacent track, the sampled frequency component is the on-track pilot signal itself, and the level obtained by this sampling is very low. It becomes a large value. After that, the frequency component of the pilot signal in the reproduced RF signal two blocks later is sampled, the difference between this sampling value and the sample value two blocks before is taken, and this level difference is used as the amount of track deviation to control the capstan servo. However, since what is sampled first is the on-track level, not the crosstalk level of the adjacent track, a very large level difference that is far from the actual track shift amount is obtained. If this happens, the capstan servo will be disturbed and the tape running will be adversely affected.

The above was a case where the previous sync signal remained in the pilot signal portion recorded later, but the sync signal was replaced by the erased signal f.
There is a good possibility that the noise may not be completely erased by 4 and may remain as noise.

〔the purpose〕

The present invention has been made in order to solve the above-mentioned problems, and eliminates malfunctions even if the sync signal of the previous recording remains erased due to overriding. An object of the present invention is to provide a digital signal reproducing device that can stably control a capstan servo based on a level difference between the two levels.

[Summary of the invention]

The present invention has been made to achieve the above-mentioned object, and the level of the pilot signal frequency component of the output of each rotary head before and after sampling performed in response to the detection of a sync signal is a cross of the pilot signal of one adjacent track. By determining whether the talk is appropriate or not, and determining whether or not to supply the above-mentioned crosstalk level difference to the capstan servo as a signal representing the amount of track deviation based on the determination result, the sync signal at the time of overwriting can be adjusted. Eliminates capstan servo disturbances caused by unerased data.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a system block diagram of an embodiment of a device according to the invention configured as a digital signal recording and reproducing device.

In the figure, 1 is a rotating drum with a diameter of 30φ, and the rotating drum '1 has an A head IA for recording and reproducing +azimuth.
Two rotating heads are arranged 180' apart from each other, and a B head IB that records and plays one azimuth, and an A head I.
Two pulse generators (PCs) PGA and PCB are arranged at intermediate positions between the A and B heads IBO.

2 is a crystal oscillator that generates a basic clock fM of 9.4 MHz, and the basic clock fM is supplied to each part of the system.

Reference numeral 3 denotes a system controller (system controller) that controls the system, and outputs a PB/REC switching signal to control switching of the toggle switch 4 consisting of switches SWI and SW2.

5 is a reference signal generator, which generates XHz (66Hz: 2P
G), YHz (depending on the number of FG of the capstan motor) and ZHz reference signals are generated.

Reference numeral 6 denotes a drum servo, which servo-controls the rotation of the drum motor based on the reference signal XHz under the control of the system controller 3. A reel servo 7 servo-controls the rotation of the reel motor based on a reference signal ZHz under the control of the system controller 3. Reference numeral 8 designates a capstan servo, which servo-controls the rotation of the capstan motor based on the reference signal YH2 when the switch 4 is switched to the B contact side by the system controller 3, and switches the switch 4 to the A contact side. During switched playback, the rotation of the capstan motor is servo-controlled based on the amount of track deviation.

9 is a HSWP (A/B) signal generator, and drum 1
HSWP that switches between A head IA and B head IB based on pulses from the two PCs above (A/100)
A signal is generated, and the HSWP (A/n) signal is H when the A head is generated and H when the B head is generated, and this signal is also supplied to each part of the system.

Reference numeral 10 denotes a phase inversion detection circuit, into which the basic clock f4 to which a large CK input is applied and the ISWP (A/100) signal are input, and the output is the S of the initial flag latch 11.
supplied to the input. Initial flag latch 11 is 8
The CY output of the initial counter 12 is input manually,
The Q output is supplied to the R input of the initial counter 12.

The initial counter 12 is configured to receive a threshold value from a table 13 under the control of the PB/REC signal from the system controller 3, and the CY output becomes H by counting the set value. The CY output is applied via the inverter 13a to PB/
, is input to the encode data processing unit 18 via the AND gate 13b which is opened and closed by the REC signal, and
AND gate 13 opened and closed by PB/RE C signal
head touch window flag latch 14 via c
S manpower is supplied.

The head touch window flag latch 14 is used to generate a window that prohibits the head touch detection operation during the noise period when switching the head.The Q output is input as an on signal to the decode data processing unit 17, and the R input is used for the processing. A clear signal is input from section 17.

A reproduction amplifier 15 amplifies signals from the rotary heads IA and IB and supplies the amplified signals to a decode data processing section 17, which will be described later. 16 is a recording amplifier, ) ISWP (A
/100) Based on the signal, encode data processing section 1 described below
Record data is received from 8 and supplied to rotary heads IA and IB via switch SWI.

The decode data processing section 17 receives the R from the reproduction amplifier 15.
After extracting data from the F-fold signal, performing 10/8 conversion (demodulation), deinterleaving, error correction, etc., it is sent to the D/A converter, and also performs head touch detection, ATF sync detection, tracking error detection, etc. , an error signal is supplied from the track deviation signal generating section 17a to the capstan servo 8.

The encoded data processing unit 18 performs interleaving, parity addition, 8/10 conversion, ATF signal addition, etc. on the A/D converted data, and then supplies the data to the recording amplifier 16.

In the above tJI configuration, a recording operation is performed when the PB/REC signal from the system controller 3 is L.

Since the PB/REC signal is L, switch 4 is set to b.
The capstan servo 8 is switched to the contact side, the reference signal YHz from the reference signal generator 5 is supplied to the capstan servo 8, the capstan servo is applied based on the reference signal YH2, and tracking is controlled.

The HSWP (A/B) signal output by the HSWP (A/B) generator 9 based on the pulses generated by PGA and PGB by the rotation of the drum 1 becomes H when the A head is IA and becomes L when the B head is IB. This HSWP (A/100) signal is input to the phase reversal detection circuit 10, and the HSWP (A/100) signal
B) When the signal level changes, that is, when it is detected that the head has switched, the output of the phase inversion detection circuit 10 becomes H for one basic clock period.

In response to the rise of the output of the phase reversal detection circuit 10 from low to high, the initial flag latch 11 is activated and its Q output becomes high. As a result, the initial counter 12 starts counting operation. In this example, when the initial counter 12 counts a number of basic clocks f9 corresponding to a fixed period of 3.75 m5 according to the set value from the table 13, its CY output rises, and this resets the initial flag latch 11. At the same time, the rising edge of the CY output is applied to the encode data processing section 18 as a recording start signal.

Based on this recording start signal, the encoded data processing section 18 outputs recording data in a predetermined formant.

Next, when the PB/RE signal from the system controller 3 is H, the switch 4 is set to the a side, and the rotating head IA
and IB are connected to the reproduction amplifier 15 and supplied to the RF multiplied signal decode data processing section 17.

The capstan servo 8 operates based on the amount of track deviation supplied from the decode data processing section 17. The amount of track deviation is an ATF error signal that corresponds to the level difference in the amplitude of crosstalk between pilot signals of both adjacent tracks, and the details will be described later.

H5WP (A/B) generator 9 and phase reversal detection circuit 1
0 operates in the same way as when recording, but the initial counter 1
2 becomes a playback mode counter based on the cent value from table 13, and the count value is, for example, 100 μs = 1 ms.
When the value corresponding to is reached, the CY output becomes H. This prohibits the head touch operation, which will be described later, while noise occurs when the head is switched, and sets the head touch window flag latch 14 via the AND gate 13c after the above-mentioned certain period of time, and outputs its Q output. This is to set it to H and output an on signal for head touch detection. When the decode data processing unit 17 detects a head touch, that is, a contact between the tape T and the head IA or IB to output an RF multiplied signal, the ON signal from the head touch window flag latch 14 is output from the head touch window flag latch 14. is cleared and the on signal becomes L.

Hereinafter, details of parts of the decode data processing section 17 particularly related to tracking control will be explained with reference to the block diagram of FIG. 2.

In the figure, the area above the dashed line is the analog system, and the area below is the digital system. The analog system includes a reproducing amplifier 15, a band pass filter (BPF) 101, and an envelope detector 102.
, the first sample hold (S/H) circuit 103, the 23rd
/H circuit 104, comparator 107, differential amplifier 10
8 and a semi-fixed resistor VR.

-4, Digital system includes crystal oscillator 2, head touch detection circuit 201, sync detection circuit 202, ATF timing generator 203, playback flag latch 204, system counter 205, timing generator 206.172 frequency divider 207, ATF initial flag latch 208,
It consists of a power-on reset circuit 209, a latch circuit 210, a protection counter 211, a noise error graph 212, a touch 213, an erroneous detection counter 214, a sampling counter 215, and OR gates 216 and 217.

First, to explain from the analog system, an RF multiplied signal is inputted to the input of the playback amplifier 150 from the rotary head IA and IB (Fig. 1), and its output is sent to each input of the BPF IOL, the head touch detection circuit 215, and the sync detection circuit 216. Supplied.

The BPFIOI passes only the 130 KHz component in the RF signal and inputs it to the envelope detector 102. The envelope detector 102 envelope-detects the 130 KHz component and applies it to the input of the S/H circuit 103 and the differential amplifier 108 .

The S/H circuit 103 samples and holds the output of the envelope detector 102 using the sampling signal SP1 applied to the C input from the sync detection circuit 202, and supplies this to one input of the comparator 107 and the output of the differential amplifier 108. Apply each. What is sampled and held by the S/H circuit 103 is the DC level of the crosstalk of the pilot signal of one adjacent track.

The S/H circuit 104 has the output signal of the differential amplifier 108 applied to its input, samples and holds this using the sampling signal SP2 from the ATF timing generator 203, and
It is supplied to the capstan servo 8 (Fig. 1) as an ATF error signal. The error signal is the DC level difference of crosstalk between both adjacent tracks.

The comparator 107 has one input applied with a voltage at a predetermined level determined in advance by adjusting the semi-fixed resistor VR.
The output of the envelope detector 102 is applied to the other human power. When the predetermined level is higher than the output of the envelope detector 102, the output of the comparator becomes H, and this is supplied as an OK multiplied signal to the input of the sync detection circuit 202.

Note that the predetermined level is set to a level that is 1/2 or more of the average value of the level of the on-track pilot signal appearing at the output of the envelope detector 102, and when the level is lower than this level, the cross of the pilot signal of the adjacent track is set. I try to judge that it is a talk component.

The differential amplifier 108 separates the output of the envelope detector 102, which is applied to the input power, and the S/D output, which is applied to the input power.
Take the difference from the output of the H circuit 103 and send it to the S/H circuit 1.
Enter in 04. That is, the envelope detector 102
When outputting the DC level of crosstalk of the other adjacent track, it outputs the difference in crosstalk between both adjacent tracks, that is, the amount of track deviation.

Next, to explain the digital system, the head touch detection circuit 201 is connected to the head touch window flange latch 1.
4 (Figure 1) and the basic clock f, detects that the RF multiplied signal is input, and supplies the signal to the S input of the regeneration flag latch 204, details of which will be described later. .

The sink detection circuit 202 receives the RF multiplied signal H3WP (A/B
) signal, the ATF window set signal from the timing generator 206, the ATF window off signal from the OR gate 217, the noise signal from the noise flag launch 212, the basic clock f from the crystal oscillator 2,
The enable clear signal from 216 (4 and 216) is input, and the sampling signal SPI, the enable signal, and the detection pulse signal are sent to its output. The sampling signal SPI is connected to the C input of the S/H circuit 103 and the latch 21.
The enable signal and the detection pulse signal are input to the R input of 0 to the ATF timing generation circuit 2.3, respectively. The sync detection circuit 2゜2 converts the RF multiplied signal into a digital signal, detects the beginning of the ATF sync patterns SYl and SY2 of the rotary heads IA and IB, outputs the sampling signal SPI, and then continuously detects the signals. It operates to output a detection pulse signal to the sink, and details will be described later.

The ATF timing circuit 203 receives an OK double signal which is the output of the comparator 107 , an ODD/EVEN signal which is the Q output of the 1/2 frequency divider 207 , an initial signal which is the Q output of the ATF initial flag latch 208 , and the sync detection circuit 202 . an enable signal and a detection pulse signal,
The post/picture signal from the timing generator 206, the enable clear signal from the OR gate 216, and the basic clock fM from the crystal oscillator 2 are input, and the output thereof is the sampling signal SP2, the false detection signal, and the ATFEN.
Send D signal. The sampling signal SP2 is connected to the C input of the S/H circuit 104 and the ATF initial flag launch 2.
The false detection signal is sent to the S input of the latch 210, one input of the OR gate 216, and the false detection counter 214.
The CK large input and the AT F E N D signal are input to one of the OR gates 216 and 217, respectively.

The ATF timing generator 203 is connected to the sink detection circuit 20
2, and when the signal is H, a timer counter (not shown) for timing generation becomes operational, and also receives a detection pulse signal from the sync detection circuit 202, counts it, and performs a specified If the detected pulse exceeds the specified value by the time, the sampling signal SP2
, and when it is below a specified value or at the L level of the OK multiplied signal which is the output of the comparator 107, it operates to output an erroneous detection signal, the details of which will be described later.

The crystal oscillator 2 oscillates at 9.4 MHz, which is the transmission rate of the R-DAT's transparent data, and outputs a basic clock f. H1i main clock r9 is the head touch detection circuit 201, sync detection circuit 202, ATF
The CK large inputs of the timing generator 203, system counter 205, and protection counter 211 are applied, respectively.

The latches 204, 208, 210, and 213 are constituted by R-S flip-flops whose Q output becomes H in response to a rising edge of the S input, and whose Q output becomes L in response to a rising edge of the R input.

The playback Franchise 204 receives the output of the head touch detection circuit 201 at the S input, the END signal which is the output of the timing generator 206 at the R input, and its Q output at the R input of the system counter 205. When the Q output of this regeneration flangel raft 204 is H, the regeneration operation is in progress.

The system counter 205 receives the Q output of the reproduction flag latch 204 and the CK large input basic clock f4 at its R input, and its outputs Q0 to Qx are input to the timing generator 206.

This system counter 205 is for roughly indicating the position on the track where each signal is recorded.

The timing generator 206 generates an ATF window set signal, a rear /17 signal, a window clear signal, and an END signal based on the Q, -Q, and outputs from the system counter, and sends the ATF window set signal to the sync detection circuit 202. , the rear/■ times signal ATF timing generator 203, the window clear signal to the OR gate 217, and the END signal to the regeneration flag latch 20.
4 R inputs respectively. This timing generator 206 decodes the output of the system counter 205 and generates the timing required for each part.

1/2 frequency divider 207 is H3WP to which CK large input is applied.
(A/100) Divide the signal by 1/2 and send ODD/EV to Q output
Generates an EN signal and sends it to the ATF timing generator 20
Supply to 3. The Q output of the ATF initial frang latch 208 is input to the R input of the 1/2 frequency divider.

ATF initial flag latch 208 connects AT to S input.
Sampling signal SP from F timing generator 203
2, the signal from the power-on reset circuit 209 is input to the R input, and the Q output is input to the R input of the 1/2 frequency divider 207 and the ATF timing generator 203. The ATF initial flag luff 208 is ATF.
Generates a flag indicating that the capstan servo is engaged.

The power-on reset circuit 209 outputs H when the power is turned on.
becomes.

The latch 210 connects the ATF timing generator 203 to the S input.
The sampling signal SPI from the sync detection circuit 202 is input to the R input, and the Q output is input to the R input of the protection counter 211. When the latch 210 detects an error, the Q output becomes H and is reset in response to the output of the sampling signal SP1.

The protection counter 211 is for counting a certain period of time from erroneous detection, and the basic clock f is applied with a high CK input only when the R input is H. It performs a counting operation and is cleared by the R input.

The Q output of the latch 210 is input to the R input, and the CY output is input to the OR gate 217.

The noise-if flag latch 212 is for temporarily storing whether or not there is noise during reproduction, and is composed of a D-type flip-flop. The latch 212 receives the Q output of the latch 213 and the CY output of the large CK input sampling counter 215 at its D input, and the Q output is supplied to the sync detection circuit 202 as a noise signal.

In the latch 213, the CY output of the false detection counter 214 is input to the S input, the CY output of the sampling counter 215 is input to the R input, and the Q output is supplied to the D input of the noise error flag latch 212.

The false detection counter 214 receives the false detection signal from the large CK input ATF timing generator 203 and the CY output of the sampling counter 215 at its R input, and the CY output is supplied to the S input of the latch 213 . This erroneous detection counter 214 counts how many times the sampling signal SPI is erroneously detected in a certain period, and when the value exceeds a certain value, the CY output becomes H.

The sampling counter 215 receives CK large input HSWP (
A/B) signal is input, CY output is false detection counter 2
14, the R input of the launch 213, and the CK large input of the noise error graph 212 are respectively supplied.

The OR gate 216 connects the false detection signal from the ATF timing generator 203 and the ATFEND signal to the protection counter 21.
CY output of 1 is input, and the sync detection circuit 2 is input to that output.
02 and an enable clear signal to the ATF timing generator 203.

OR gate 217 is a window clear signal from timing generator 206, ATF timing generator 20
The ATFEND signal from the protection counter 202 and the CY output from the protection counter 211 are respectively input, and an ATF window off signal is sent to the sync detection circuit 202 at its output.

In the above configuration, the head touch detection circuit 201 and the sync detection circuit 202 pass through the RF double signal regeneration amplifier 15.
and B P F'lo1.

Only the 130 KHz component of the RF multiplied signal supplied to BPFI O1 is passed. The amplitude level of the 130KHz component is converted to a DC level by the envelope detector 102, and then the S
It is applied to the input of the /H circuit 103 and the power of the differential amplifier 108.

The envelope detector 102 sequentially outputs the DC level of the amplitude of the crosstalk of the pilot signal of one adjacent track, the amplitude of the crosstalk of the pilot signal of the other adjacent track, and the amplitude of the pilot signal of both adjacent tracks. The DC level of the amplitude of the on-track pilot signal is output before or after the signal.

The S/H circuit 103 samples and holds the DC level of the pilot signal of one adjacent track at the timing of the sampling signal SPI from the sync detection circuit 202.

The crosstalk level of one adjacent track sampled and held is determined by the comparator 107 and the differential amplifier 10.
8 is applied to one person's power.

When the predetermined level input from the semi-fixed resistor VR is higher than the input from the S/H circuit 103, the comparator 107 becomes an OK multiplied signal H. In other words, it is determined that the crosstalk level of one adjacent track has been correctly sampled. In the opposite case, it is determined that the on-track level has been sampled. Therefore, when the OK double signal is L, it is determined that the sync has been erroneously detected. This OK double signal is supplied to the ATF timing generator 203.

The differential amplifier 108 inputs the DC level of the crosstalk amplitude of one adjacent track when the envelope detector 102 outputs the DC level of the crosstalk amplitude of the other adjacent track. Therefore, the output includes the difference in DC level of crosstalk between both adjacent tracks,
In other words, the track deviation amount is obtained, and this is the SIH circuit 1.
04 is input.

The S/H circuit 104 samples and holds the amount of deviation between both adjacent tracks using the sampling signal SP2. This S/
The output of the H circuit 104 is supplied to the capstan servo 8.

FIGS. 3(a) to 3(hl) are timing charts showing signal waveforms generated in each part by the above operations, corresponding to the symbols attached to each part.

The HSWP (A/100) signal shown in Figure 3(b) is
When reproduced by B, it becomes L. HS when the head does not switch
The phase of the WP (A/100) signal is inverted. When the phase is reversed, the Q output of the initial flag latch 11 (FIG. 1) becomes H, and the initial counter 12 (FIG. 1) operates. The CY output of the initial counter 12 becomes H at the timing when it is determined that the tape has passed a noisy portion, and the head touch window flag latch 14 (FIG. 1) is set to make its Q output H. When the Q output of the belly button touch window flag 14 becomes H, the head touch detection circuit 201 is activated.

When the head touch detection circuit 201 detects that the tape and the head are in contact and the RF multiplied signal is reproduced, its output becomes H.
, set the regeneration flag latch 2゜4 and
Set the output to H. When the Q output of the regeneration flag latch 204 becomes H, the system counter 205 starts counting. Based on this point, system counter 2
05 can make a rough judgment about the recorded position of each signal on the tape. The timing generator 206 is the Q of the system counter 205.

Based on the ~Qx output, an ATF window cent signal is supplied to the sync detection circuit 202 just before the recording of ATF-1 and ATF-2.

After converting the RF multiplied signal into a digital signal, the sync detection circuit 202 detects sync 1 (= f
z) and sync 2 (=f3) in the case of B head IB, each sync is detected based on the relationship shown in the table below depending on the frame.

Here, when the sync detection circuit 202 detects three syncs in a normal case or four syncs in a row in a noisy case, it outputs a sampling signal SPI, and sends a cross of the pilot signal f of one adjacent track to the S/H circuit 103. The talk level is sampled and held, and an enable signal is supplied to the ATF timing generator 203. A detection pulse signal is then supplied to the ATF timing generator 203 every time a continuous sync is detected.

The ATF timing generator 203 is connected to the sink detection circuit 20
The sink detection counter and timer operate in response to the H level of the enable signal from 2. The ATF timing generator generates the sampling signal S 0.25 block after the sampling signal SP1 is output from the sync detection circuit 202.
Check whether the crosstalk of adjacent tracks has been correctly sampled and held by the PI. Next 1.2
After 5 blocks, it is determined whether the sync is detected at a specified value or more, and if it is above the specified value, it is assumed that the sync has been detected correctly and the sampling signal SP2 is sent to S/H after 2 blocks.
The signal is supplied to a circuit 104 to sample and hold the crosstalk level difference between both adjacent tracks, and its output is supplied to the capstan servo 8 as the amount of track deviation.

If the above series of operations are performed correctly, ATF E
An ND signal is output, and is supplied to the sync detection circuit 202 and the ATF timing generator 203 as an enable clear signal via the OR gate 216. ATF
The END signal is also supplied to the sync detection circuit 202 as a window off signal via the OR gate 217, and in response, the window for sync detection by the sync detection circuit 202 disappears, and the operation of detecting the pattern of the sync signal is stopped. Ru.

Missampling, that is, the output of the comparator 107 changes the level of the on-track pilot signal to S/H.
If it is determined that the circuit 103 has sampled and held,
If the sink is not equal to or greater than the specified value, the erroneous detection signal is set to H, the Q output of the latch 210 is set to H, and the protection counter 211 is caused to perform a counting operation, and the erroneous detection counter 214 is caused to perform a +1 operation. When the above-mentioned false detection signal becomes H', it is also transmitted to the sink detection circuit 202 and the ATF timing generator 203 via the OR gate 216.
The enable clear signal to becomes H.

When the enable clear signal becomes H, the sink detection circuit 2
02 performs the operation of detecting the sync again from the beginning, and once the sync is detected, outputs the sampling signal SP1 again. Meanwhile, the ATF timing generator 203 sets the sync detection counter and timer to the initial state. As described above, the sync detection circuit 202 again detects the sampling signal S.
When PI is output, the second circuit 210 is reset, the Q output becomes L, and the protection counter 211 is set to the initial state.

After the CY output of the protection counter 211 becomes H after the erroneous detection signal is output once, that is, after a specified time (2.5 blocks), the sync detection circuit 202 and the ATF timing generator 203 are connected via the OR gate 216. The enable clear signal to becomes H, and the operation stops.

The sampling counter 215 increases by 1 at the rising edge of the H3WP (A/100) signal, but this is because the tape is managed by length, and if the number of false detections exceeds a certain level during that period, the false detection counter 214 increases. The CY output becomes H, which causes the Q output of the noise error flag 7 213 to become H, thereby informing the sync detection circuit 202 that the tape is noisy.

Further, the ATF window off signal sent to the sync detection circuit 202 via the OR gate 217 becomes H due to the window clear signal from the timing generator 206, but this is to prevent a large dropout.

4(a) to (C) and (A) to (G) are timing charts showing the outline of signal waveforms of each part of the digital system after the initial flag latch 11 is set during reproduction, Corresponding symbols are given in FIG.

FIG. 5 is a block diagram showing a specific example of the configuration of the head touch detection circuit 201 described above.

In the figure, the comparator 1-1 has an RF multiplied signal inputted to one input and a reference voltage +■ inputted to the other input. Comparator 1-2 has an RF multiplied signal on one input,
The reference voltage -■ is input to the other input.

The output of comparators 1-1 and 1-2 is OR gate 1-
3. D-type frimbflop (FF) via resistors 1-4
1-5 and is further connected to the D input of capacitor 1-5.
6 to ground.

D-type FF1-5 has a CK large input basic clock f.

is input, its Q output is connected to the input of AND gates 1-7, and its ζ output is connected to the input of AND gates 1-8.

The basic clock f9 is input to the inputs of the AND gates 1-7 and 1-8, and the outputs of each are connected to the UP large input and DOWN input of the up/down counter 1-9, respectively. Q tt of up/down counter 1-9
”Q o output is input to AND gate 1-8 via OR gate 1-10, CY output is input to C of D type FF1-11.
The K large inputs are connected to each other. The D input of the D type FF1-11 is connected to VCC, and the Q output is the output of the head touch detection circuit 2.1.

R of up/down counter 1-9 and D type FF1-11
For input, head touch window frang latch 14
The Q output of (FIG. 1) is applied.

In the above configuration, if the level of the comparator 1-1 is higher than the RF multiplied signal 10, the output becomes H1 low and L. If the level of the comparator 1-2 is higher on one side than the RF multiplied signal 1, the output becomes L if H1 is lower. That is,
When the signal is not within the range of the RF doubler (2), the output of the OR gates 1-3 becomes H.

The resistor 1-4 and the capacitor 1-6 constitute an integrating circuit, and the integrating circuit absorbs noise leaking into the output of the OR gate 1-3. The output of OR gates 1-3 from which spike noise has been removed by the integration circuit is D.
Applied to the D input of the FF1-5.

The D-type FF1-5 samples the state of the D input using the basic clock f,4 applied to the CK large input, and outputs the state to the Q output. The ζ output is the inverted output of the Q output. The Q output of the D-type FFl-5 is applied to the other input of the AND gate 1-7 to which the basic clock f9 is applied to one input, and the Q output of the D-type FFl-5 is applied to the I
], the UP large input basic clock f9 of the up/down counter 1-9 is input via the AND gate 1-7. Therefore, the up/down counter 1-9 up-counts the basic clock f9 when the Q output of the head touch window flag latch 14 is H, the window is standing, and the Q output of the D-type FF 1-5 is H.

When the Q output of the D-type FF1-5 is L, that is, when the RF multiplied signal level is within −V and it is determined that there is no signal, the ζ output becomes H. In this state, when any of the QA""Qn of the up/down counters 1-9 is H, that is, when the counter is not O, the basic clock f9 is applied to the DOWN input through the AND gates 1-8, The up/down counter 1-9 performs a down counting operation. Furthermore, when the contents of the counter become O and all the outputs of QA-QD become L due to this down count or reset, the output of OR gates 1-10 becomes L, and AND gates 1-8 are closed. For,
The basic clock f, is not supplied to the DOWN input.

When the up/down counter 1-9 counts up, a carry occurs and the CY output becomes H, and this rise causes the D-type FF1-11 to memorize the state of the D input. Since the D input is H, the Q output becomes H.

6(a) to 6('') are timing charts showing waveforms of various parts of the head touch detection circuit shown in FIG. 5 when the RF multiplied signal shown in (al) is input.

In a state where the RF multiplied signal is present, the amplitude is continuously greater than ±■, and in a state where there is no signal, that is, where the head is not in contact with the tape, there is almost no amplitude greater than the force (■).

Note that ±■ is set to a value that makes it possible to clearly distinguish between a signal and noise.

(In response to the RF multiplied signal input as shown in al), a waveform as shown in (b) appears in the output of the comparator 1-1, and a waveform as shown in (C) appears in the output of the comparator 1-2. And the output of OR gate 1-3 has (b
As is clear from the waveform of the logical sum of the waveforms l and (e) (a waveform as shown in dl appears; fd), there is gate leakage in the output of the gates 1-3. This gate leakage is removed by the integrating circuit, and the D-type FF 1-
A signal having a waveform as shown in tel is input to the input of 5.

As a result, a waveform as shown in tf> appears in the Q output of the D-type FF1-5, and during the period when the Q output is H, the AND gate 1-5 appears.
When the basic clock f, 4 passes through 7, a signal as shown in (gl) appears at the output of AND gates 1-7. On the other hand, a signal as shown in (h) appears at the output of AND gates 1-8. A signal appears.

Incidentally, noise components slightly exceeding ±V and gate leakage are removed by the integrating circuit, but when noise with a large amplitude appears singly, the integrating circuit cannot completely remove it.

Signals (g) and (h) are applied to the UP large input and DOWN input of the up/down counter 1-9, respectively.

When the up/down counter 1-9 counts a predetermined number, it sends a carry as shown in +1) to the CY output, and in response, the D-type FF1-11 stores the D input, and the Q output becomes U). Stand up as shown.

As described above, small noises and gate leakage are handled by the integrator circuit, and large noises are handled by the up/down counters 1-9.
It is possible to reliably determine whether the tape and head are actually in contact and the signal is being reproduced, or whether the signal is being reproduced without contact. That is, head touch is detected.

FIG. 7 shows a specific example of the configuration of the sync detection circuit 202.

The sink detection circuit 202 has an RF multiplied signal H3WP (A
/100) signal, basic clock f14, ATF window cent signal, ATF window clear signal, noise signal, and enable clear signal are input.

The ATF equalizer 2-1, to which the RF multiplied signal is supplied from the reproduction amplifier 15 (Fig. 1), has a band 40 of the ATF sync signal.
0KHz to 900K) (emphasizes z and outputs it to the limiter 2-2. The limiter 2-2 converts it into an RF multiplied signal digital signal by setting H2 if the signal amplitude is larger than a specified level and L if it is smaller.

The output of the limiter 2-2 is the CK large input basic clock f.

is supplied to the D input of the D-type FF 2-3, which is inputted, and also supplied to one input of the exclusive OR (EOR) gate 2-4. The Q output of type FF2-3 is supplied, and a phase reversal detection circuit is constituted by this EOR gate 2-4 and D type FF2-3.

The ATF window set signal is sent to the ATF window latch 2- to which the ATF window clear signal is input to the R input.
5, and the ATF window rafter 2-
The ATF window signal is output from the Q output of 5.

The output of the EOR gate 2-4 is that the CK large input basic clock f,4 is connected to the R input of the ATF window latch 2-5.
11 into which the ATF window signals from
It is supplied to the D input of the stage shift register 2-6. The Q1 output of the 11-stage shift register 2-6 passes through the inverter 2-7 to AND gates 2-8 and 2-9, Q2-Q, and the output goes to AND gates 2-8 and 2-9, Q6-Q, The output is to NOR gate 2-10 and AND gate 2-9, Q,
~Qll outputs are supplied to NOR gates 2-11, respectively, and outputs of NOR gates 2-10 and 2-11 are supplied to AND gates 2-8 and 2-9, respectively. Furthermore, an inverter 2 is connected to the inputs of AND gates 2-8 and 2-9.
-12 supplies the inverted and previous H3WP (A/100) signals, respectively. ANDGATE 2-8 and 2-
The output of 9 is supplied to the input of 2-13 (or game).

The output of OR gate 2-13 is CK large input basic clock f
D of the 29-stage shift register 2-14 to which M is input
supplied to the input. Q of 29-stage shift register 2-14
1 output is input to AND gates 2-15 to 2-20, Q, ~Q, which becomes H when sink 2, output is OR game) 2-
21 input, Q which becomes H when sink 1 is applied, ~Q11 output is input to OR gate 2-22, Ql! which becomes H when sink 2 is applied. ~Q14 output is input to OR gate 2-23, and QI8~Q2 becomes H on both sink 1 and sink 2.
゜Output is input to OR gate 1-2-24, and Q27-Q29 output, which becomes H when sink 1 is input, is input to OR gate 2-2.
25 inputs, respectively.

The output of OR gate 2-21 is connected to the input of AND gates 2-16 and 2-18, and the input of OR gate 2-26, and the output of OR gate 2-22 is connected to the input of AND gates 1-2-15 and 2-17, and the input of OR gate 2-26. -27 input, the output of OR gate 2-23 is AND gate 2-16 and 2
-18 input and the input of the OR gate 2-26, the output of the OR gate 2-24 is ant game) 2-15 to 2-1
8 and the input of OR gate 2-27, and the output of OR gate 2-25 is supplied to the input of AND gate 2-15, respectively. Also, or gate 2-26 and 2
The output of -27 is supplied to the input of AND gates 2-20 and 2-19, respectively.

The H3WP (A/100) signal is applied to the AND gates 2-15, 2-17 and 2-19, and the AND gate 2-16
, 2-18 and 2-20 are supplied with the H3WP (A/100) signal inverted by the inverter 2-12, respectively. Further, the AND gates 2-15 and 2-16 are supplied with a noise-like signal, and the AND gates 2-17 and 2-18 are supplied with a noise-like signal inverted by an inverter 2-28.

The outputs of the AND gates 2-19 and 2-20 are supplied to the OR gate 2-28', and the output of the OR gate 28 is output as a detection pulse signal via the AND gate 2-29. On the other hand, the above AND gates 2-15 to 2-18
The output of OR gate 2-30 is supplied to OR gate 2-30.
The output of -30 is outputted as a sampling signal SPI via AND gate 2-31, and an enable clear signal is supplied to the R input of ATF enable latch 2.
-32 S input. The Q output of the ATF enable latch 2-32 is output as an enable signal and is also supplied to the input of the AND gate 2-29. The mutual outputs are supplied to the inputs of AND gates 2-15 to 2-18 and 2-31 to control their opening and closing.

In the above configuration, the sync detection circuit 202 operates as follows.

From limiter 2-2, sink 1 for ATF in the RF signal
and a digital signal corresponding to the sink 2 is output, and the output of the EOR gate 2-4 becomes one clock in accordance with the phase inversion of the digital signal.

The shift register 2-6 to which the output of the EOR gate 2-4 is applied to the D input receives the CK high input when the window signal from the ATF window latch 2-5 applied to the R input is H. In response to the rise of the basic clock f, the D input is taken in and the Ql ratio output is sent out, and thereafter the basic clock f.

It is sequentially shifted every time the signal rises and is sent to the Q2 to Q11 outputs. That is, shift register 2-6 is EOR gate 2
-4 output is delayed by 1 to 11 clocks to output Q1 to Q11.
Send to output.

When the QI output is L, that is, when there is a change, this is passed through the inverter 2-7 to the AND gates 2-8 and 2.
-9, and when any one of the Q b -Q s outputs becomes low, one input of the AND gate 2-8 is set to H via the Nandt gate 2-10. Q2 to Q, the output is H when there is no change. At this time, H5WP
(A/B) If the signal is positive, inverter 2-12
H is applied to the input of AND gate 2-8 via.

In this state, all inputs of the AND gate 2-8 become H, and the output becomes H. Therefore, when this condition is not satisfied, the output remains L, does not change for at least 4 clocks, and changes for 5 to 7 clocks.) (SWP
When the (A/B) signal is L and reproduction is being performed by the B head IB, a 1/2 period of the sync 2 signal is detected. In addition, in reality, the sink 2 signal f3 (=784KH
z, fq/12), so the length that does not change is 6 clocks, but due to clock timing, jitter, etc., a margin of ±11 clocks is allowed.

From the output of AND gate 2-8, 1/2 of the sink 2 signal
A pulse corresponding to one clock period is outputted every cycle.

In addition, from the output of AND gate 2-9, the sink 1 signal ft (=520KHzXfM/
18), but the H3WP (A/100) signal is Hl, that is, A
It is detected when the head IA is performing reproduction, and is output from the AND gate 2-9. Note that the period with no change is 7 clocks, and a change occurs between 8 and 10 clocks.

When H5WP (A/100) is L, the sink 2 signal is sent from AND gate 2-8 to sink 1 (the word is H3WP (A/100)).
100) When the signal is H, it is output from the AND gates 2-9 through the OR gates 2-13, and the shift register 2
−14 applied to zero human power.

The 29-stage shift registers 2 to 14 store the state of the D input at the rising edge of the clock and send it to the Q and output, and thereafter are shifted every time the clock is applied and sent to the Q2 to Q and 9 outputs.

That is, the state of the D input is outputted to the Q, to Qz, output with a delay of 1 to 29 clocks.

When there is a change in the Q and output of the shift register 2-14, the Ql ratio output becomes H. Sink 2 signal (f3=780K
Hz - 1/12 fx), if there is a change 1/2 period before the Q1 output, then the error occurs (or game) 2-21
The output becomes H. Further, if there is a change one cycle before, the output of the OR gate 2-23 becomes H. Therefore, the output of the OR gate 2-26 becomes H if there is a change 1/2 and/or one period ago. The output of the OR gate 2-26 is the Q, output of the shift register 2-14 and H3WP (A/
B) is applied together with the signal to the input of AND gate 2-20. That is, in the case of sink 2, AND gate 2-
Ql after one clock delay after detecting sync 2 by 8
The output appears at the output, and at this time, changes from 1/2 period ago are passed through OR gates 2-21 and 2-26, and changes from one cycle before are sent to AND gates (OR gates) 2-23 and 2-26, respectively. When applied simultaneously to the inputs of AND gate 2-20, the output of AND gate 2-20 becomes H, and accordingly, the output of OR gate 2-28 becomes H.

The output of the OR gates 2-21, 2-23, and 2-24 connected to the output of the 29-stage shift register 2-14 becomes H when the sink is 2, so when the noise signal is L,
The output of the AND gate 2-18 becomes H, which is output as the sampling signal SPl via the OR gate 2-30 and the AND gate 2-31, and is also applied to the S input of the ATF enable latch 2-32, causing the ATF enable latch to become H. Q output of H2-32 becomes H2■ output becomes L. The Q output is output as an enable signal and is also applied to the AND gate 2-29.
After that, the detection pulse signal can be outputted.

In the case of sink 2, when the noise signal is H,
The output of the AND gate 2-16 becomes H, and a similar operation is performed.

On the other hand, when sink 1, or gate 2-22°-2-
The outputs of 24 and 2-25 become H, and the noise signal becomes L.
When , the output of AND gate 2-17 becomes H,
When the noise signal is H, the output of the AND gate 2-15 is H, and the same thing as described above is performed.

In other words, the sync detection is determined based on the noisy signal.
Switching between points and 4 points.

FIGS. 8(a) to 8(gl) are timing charts showing waveforms of various parts during detection of the sink 2, and corresponding symbols are given in FIG. 7.

Further, FIGS. 9A to 9E are timing charts showing waveforms of various parts when detecting the sync 1, and corresponding symbols are given in the figures.

FIG. 10 shows a specific example of the configuration of the ATF timing generator 203.

The ATF timing generator 203 has ODD/EVEN
A signal, a basic clock fM, a H3WP (A/100) signal, an enable signal, an enable clear signal, a rear/previous signal, an OK double signal initial signal, and a detection pulse signal are input.

Enable signal to E input, CK large input basic clock rM
, and the 0 and 25 block counters 3-1 each having an enable clear signal input to their R inputs have a value of 9.5.
When a count corresponding to μs is performed, the CY output becomes II, which is input to the E input of the high counter 3-2 and the C input of the decoder 3-3, respectively.

High counter 3-2 has CK large input basic clock f,,R
An enable clear signal is input to each input, and counts up every 0.25 block. The Q0 to Q (2° to 23) outputs of the counter 3-2 are input to the decoder 3-3.

Decoder 3-3 is for decoding each time,
Only when the C input is H, the O~8.16 and 17 outputs become active, and the 0~8 outputs send 0.25~2.25 block signals every 0.25 blocks, and the 16 and 17 outputs send 4 block signals. A block signal and a 4.25 block signal are respectively output.

The output of the decoder 3-3 is input to the gates 3-5 to 3-10, and the 0.5 block signal is input to the latch 3-12.
R input of , CK large input of D type FF3-13 is supplied, 1
The block signal is supplied to the CK input of the D-type FF3-14.

The decoder 3-15 to which the H3WP (A/B) signal and rear/possible signal are respectively input is the ATF currently being reproduced.
This is for decoding the position of the signal, and outputs the B-ATF-1, A-ATF-1, B-ATF-2, and A-ATF-2 signals to the 0 to 3 outputs, and sends this to the gate 3-16. and 3 to 17.

Table 3-18 to which the H3WP (A/100) signal and the initial signal are input holds the sink detection threshold value, and the held threshold value is switched by the H3WP (A/B) signal and the initial signal. and sets it in the sync detection counter 3-19.

The H3WP (A/100) signal sets each section for sync 1 when playing A head and for sync 2 when playing B head, and each section sets 50% of the number of consecutive sync patterns.
It becomes. However, when the initial signal is L, the number is set to 60% of the number when sync 2 is continuous.

The sink detection counter 3-19 counts the detection pulse signal and supplies the CY output to the S input of the latch 3-12.

In addition to the above, the ATF timing generator 203 includes gates 3-20 to 3-27 and inverters 3-28 to 3-30.

Then, the sample signal SP2 is output from the gate 3-9, the false detection signal is output from the gate 3-26, and the gate 3-2
ATFEND signals are output to the outputs of 7, respectively.

In the above configuration, when the sync detection circuit 202 generates the sampling signal SPI, the 0.25 block counter 3-1 starts counting in response to the enable signal and the OK multiplication signal, which become H at the falling edge of the sampling signal SPI. The CY output becomes H every time. The decoder 3-3 decodes the state of the high counter 3-2, and its output becomes H only when the CY output of the 0.25 block counter 3-1 is H.

When the O output of the decoder 3-3 appears, that is, 0.25 blocks after the generation of the sampling signal SPI,
If the crosstalk sample value of one adjacent track is below a predetermined level, the OK multiplied signal is H, so the AND gate 3-7 is inputted via the OK multiplied signal inverter 3-31. Decoder 3 is used for the output of
-3 D output does not appear. However, in the case of the OK double signal L, the output of the AND gate 3-7 becomes H, which is output from the OR game 3-26 as an erroneous detection signal.

When 1 output of decoder 3-3 becomes H, 0.5
As processing after blocking, this is applied to the input of the sink detection counter 3-19 via the OR gate 3-10, and is also applied to the R input of the latch 3-12 and the D-type FF 3-1.
3 CK large input is also applied.

Since the CY output of the sync detection counter 3-19 is input to the D input of the D-type FF 3-13 via the latch 3-12, it is determined whether there is a detected pulse signal greater than the specified value after 0.5 blocks. This will be sampled by the D-type FF3-13. At the same time, the latch 3-12 is reset and the sync detection counter 3-12 is reset.
19, set the threshold value again from Table 3-18.

When the 3 outputs of the decoder 3-3 are H, processing after one block is performed, and the CY output of the sync detection counter 3-19 is applied to the D-type FF 3-14 applied to the D input via the latch 3-12. After one block, sampling is performed to determine whether there is a detection pulse of a specified value.

The combinational circuit of gates 3-20.3-21.3-23 and 3-30 determines whether or not a prescribed detection pulse signal is present based on the ODD/EVEN signal. In the case of ODD, the Q outputs of D-type FF3-13゜3-14 are both H, and in the case of EVEN, the Q output of D-type FF3-13 is
When the output is H, it is assumed that there is a prescribed detection pulse signal, and the output of the OR gate 3-25 becomes H.

In similar processing, when the initial signal is H, the output of the OR gate 3-25 becomes H via the inverter 3-29 and the AND gate 3-22.

If the sink detection counter 3-19 does not detect the specified value, the output of the OR gate 3-25 becomes L. Therefore,
When the 4 outputs of decoder 3-3 are H, that is, 1.25
After blocking, when a specified number of detection pulse signals are not detected, the inverter 3-28 and the AND gate 3-8 are activated.
An erroneous detection signal of H is outputted from the output of the OR gate 3-26 via.

When the 7 output of the decoder 3-3 is H, that is, after 2 blocks, the presence of the specified detection pulse signal and the OK multiplication signal cause the output of the AND gate 3-9 to be used for sampling other adjacent tracks. Sampling signal SP2
Output.

Furthermore, when the 17 output of the decoder 3-3 is H and the A head is ATF-2 and the B head is ATF-1, the ATFEND signal is output via the gates 3-17, 3-5 and 3-27.
A signal is output. Then, when the 8 outputs of the decoder 3-3 become H when the A-head is ATF-1 or the B-head is ATF-2, the ATFEND signal is output via the gates 3-16, 3-6 and 3-27. .

FIGS. 11(a) to 11('') are timing charts showing waveforms of each part accompanying the above operation, and corresponding symbols are assigned to each part.

In the above embodiment, the signal level sampled and held in the S/H circuit 103 by the sampling signal SPI from the sync detection circuit 202 and a predetermined level are compared in the comparator 107, and the result is multiplied by OK. The signal is input to the ATF timing generator 203, and the sampling signal S
The output of P2 is controlled. That is, the difference between the signal level sampled and held by the sampling signal SP1 and the signal level two blocks after the sample and hold is used as an ATF error signal to control whether or not to be sampled and held in the S/H circuit 104. As a result, when the level sampled and held by the sampling signal SPI is abnormally large, it is determined that this level is not a proper crosstalk of the pilot signal of one adjacent track, and an ATF error signal is not formed based on the abnormal signal. This prevents tracking disturbances.

Similarly to the above, the circuit configuration for preventing tracking disturbance is not limited to this, and various methods can be considered.

FIG. 12 is a circuit diagram showing a variation thereof, in which the comparator 107 compares the output of the differential amplifier 108 with a predetermined level, and outputs an OK multiplied signal to the ATF timing generator 203 based on the result. It looks like this.

This was done based on the fact that if the signal level sampled and held in the S/H circuit 103 is abnormal, the difference between this signal level and the level two blocks later will also be abnormal, as shown in Figure 2. The same effect as that of the circuit can be obtained.

FIG. 13 is a circuit diagram showing another modification, in which a comparator 107 compares a predetermined level with the output of the S/H circuit 104 and applies the result to the D input of the latch 110. The latch 110 stores the state of the D input when the large CK input is applied to the sampling signal SP2 delayed for a certain period of time by the play circuit 111, and sends it to the ζ output. The ζ output is used as a control signal for the switch circuit 112. The switch circuit 112 has two switches SW1 and SW2 that interlock with each other, the a contacts of the switches SWI and SW2 are connected to the output of the S/H circuit 104, and the common contact of the switch SWI and the b contact of the switch SW2 are connected to the output of the S/H circuit 104.
One end of the contact is connected to the other end of the capacitor 113 which is grounded, and an ATF error signal is output from the common contact of switch SW2.

This circuit switches the switches SW1 and SW2 of the switch circuit 112 to the a contact side when the level difference sampled and held in the S/H circuit 104 is normal.
04 is output as an ATF error signal, and the capacitor 113 is charged. When the level difference becomes abnormal, switch SWI and SW2 to the b contact side,
The abnormal level difference is not output as an ATF error signal, and the level previously held in the capacitor 113 is output as an ATF error signal.

The same thing can be done only when the level difference is normal.
It is also possible to provide an S/H circuit that samples and holds the same level difference as the sampled and held level difference in the H circuit 104 instead of the capacitor.

〔effect〕

As explained above, according to the present invention, it is determined whether the sampled level is appropriate according to the sync signal, and the capstan servo is not controlled due to an inappropriate crosstalk level difference. Therefore, disturbance of the capstan servo can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment according to the present invention, FIG. 2 is a block diagram showing main parts of the present invention,
Figures 3 and 4 are timing charts showing signal waveforms of each part in Figure 2, Figure 5 is a circuit diagram showing the specific configuration of a part of Figure 2, and Figure 6 is in Figure 5. FIG. 7 is a block diagram showing the specific configuration of other parts in FIG. 2. FIGS. 8 and 9 are timing chart diagrams showing signal waveforms of each part in FIG. 10 is a circuit diagram showing a specific configuration of another part in FIG. 2, FIG. 11 is a timing chart showing signal waveforms of each part in FIG. 10, and FIG. 13th
The figures are circuit diagrams each showing a modification of a part of Fig. 2,
Figure 14 shows the track format and block format of R-DAT, and Figure 15 shows the AT of R-DAT.
A diagram showing the F track pattern and FIG. 16 are diagrams for explaining the principle of tracking control using the track pattern of FIG. 15. IA, IB... Rotating head, 103... Sample hold circuit, 107... Comparator, 108...
Differential amplifier, VR...semi-fixed resistance.

Claims (1)

[Scope of Claims] A plurality of signals including a tracking pilot signal and a sync signal consisting of a digital signal and a frequency signal with little azimuth effect are recorded in each of a plurality of diagonal tracks in independent recording areas in the longitudinal direction of each track. A recording in which the pilot signals are recorded in three consecutive tracks in a predetermined format, and the pilot signals are recorded in different positions, and the sync signal is recorded in a position corresponding to one adjacent track. The plurality of signals on the medium are reproduced by at least two rotary heads, the width of each rotary head being wider than the width of each track, and by reproducing each track, the on-track pilot signal and both adjacent tracks are output from each rotary head. obtain the crosstalk of the pilot signals of the two adjacent tracks, and control the capstan servo based on the level difference of the crosstalk of the pilot signals of both adjacent tracks.
In an apparatus in which each rotary head scans each track, a sync detection means detects the sync signal, and a pilot signal frequency is detected from the output signal of the rotary head in response to the detection of the sync signal by the sync detection means. A holding means for sampling and holding the level of the component, and a comparison means for comparing the level held in the holding means with a predetermined level, and the level held in the holding means is determined based on the comparison result by the comparing means. and the level of the pilot signal frequency component in the output signal of each rotary head after a certain period of time after the detection of the sync signal by the sync detection means is sent to the capstan servo as a signal representing the amount of track deviation. A digital signal reproducing device characterized in that the digital signal reproducing device determines whether or not to supply the signal.