JPS63180162A - Data processor - Google Patents

Abstract

PURPOSE:To minimize the increase of an undesired load on an internal data bus and to improve the efficiency of data transfer by increasing relatively the number of bits of the internal bus which connects a processor to each function block in response to connected areas. CONSTITUTION:An internal data bus IDB connected with a microprocessor MPU is connected to a function block of a 1st data memory DTM, etc., that is required for the relatively high-speed transfer of data to the MPU via an area of 16 bits. Thus reading/writing actions are carried out every 16 bits to such a function block requiring the high-speed transfer of data in case the MPU accesses said function block. As a result, the data transfer frequency is halved to improve the data transfer efficiency in comparison with a case where the bus IDB has single bit constitution of 8 bits. The area where the number of bits is increased is limited at a position between those function blocks requiring the high-speed transfer of data. Therefore, the area efficiency is never affected at all.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data processing device and also to a configuration method of an internal data bus, and is a technology that is effective when applied to, for example, a single-chip microcomputer with a built-in program memory and data memory. It is related to.

[Prior art]

2. Description of the Related Art As the degree of integration of semiconductor integrated circuits has improved, so-called single-chip microcomputers have been provided that have a control circuit, an arithmetic circuit, a memory, and an input/output circuit built into a single semiconductor substrate. Such single-chip microcomputers are described in "Microcomputer Handbook J P2S5 to P1" published by Ohmsha on December 25, 1985.
62, 4-bit, 8-bit, 16-bit, or even 3-bit, depending on the versatility of system needs.
It is expanded to 2 bits. In such a single-chip microcomputer, the access time to functional blocks such as built-in memory is substantially shorter than the access time to external devices, which can contribute to improving the throughput of the microcomputer.

[Problem that the invention seeks to solve]

By the way, the inventor of the present invention examined a single-chip microcomputer from the viewpoint of bus configuration, and found that a single-chip microcomputer has a timer counter, a communication interface, an analog
There is a tendency for various built-in functions comparable to those of conventional peripheral devices such as digital converters, and in such cases, if the internal data bus has a single bit configuration, the internal data transfer will be slower than the built-in functions. The problem was found that efficiency or access efficiency cannot be improved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can improve internal data transfer efficiency while minimizing undesirable increases in parasitic loads on internal data buses.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

In other words, in a data processing device in which a processor and a plurality of functional blocks controlled by the processor are formed on one semiconductor substrate, the number of bits of the internal data bus connecting the processor and each functional block is determined by the number of bits between the processor and the functional blocks. The size of the processor is relatively increased in accordance with the location where the processor is connected to functional blocks such as data memory and program memory, which require relatively high-speed data transfer between them.

[For production]

According to the above-mentioned means, the necessary number of data transfers between the processor and the functional blocks connected to the portion where the number of bits of the internal data bus connecting the processor and each functional block is relatively increased is as follows: The undesirable load parasitic on the internal data bus is reduced in accordance with the increase in the number of bits, and the increase in undesirable load on the internal data bus due to the increase in the number of bits is minimized. The objective is to improve internal data transfer efficiency while minimizing signal propagation delay caused by an increase in .

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a data processing device according to the present invention. The data processing device shown in the figure is
It is a so-called single-chip microcomputer formed on one semiconductor substrate.

Although not particularly limited, it is to be interfaced with an 8-bit external system data bus SDR.

The single-chip microcomputer of this embodiment includes a microprocessor MPU that is roughly divided into an arithmetic execution system EXC that executes arithmetic processing based on commands and a control system CNT that decodes commands and sequentially generates various control signals. Built-in, its microprocessor M
The plurality of functional blocks subject to access control of the PU include, but are not particularly limited to, a program memory PGMM that stores programs, a first data memory DTMI and a second data memory DTM2 that store data in a rewritable manner.
．． A first output circuit 1101 and a second output circuit 102 are provided to interface with external peripheral devices.

These functional blocks are intended to enable the single-chip microcomputer of this embodiment to incorporate various functions comparable to those of peripheral devices and to respond to various system needs, and each block is configured to have special functions. has been done.

That is, the arithmetic execution system EXC is a 16-bit A (not shown)
It is equipped with an LU and is configured to be able to perform high-speed 16-bit operations, and the control system CNT is configured to be able to fetch commands in 16 bits. The first output circuit 1101 is an input/output circuit with a high data transfer rate, such as a communication interface with a relatively high data transfer rate, such as a local area network, or a 16-bit timer/counter. The system data bus SDR is composed of input/output circuits that require simultaneous processing such as set operations using data with a larger number of bits than the bit configuration of the system data bus SDR. Moreover, the first data memory DTMI is.

Although not particularly limited, data for high-speed computation in the arithmetic execution system EXC is exclusively stored therein, and is configured to be capable of inputting and outputting 16-bit data similarly to the program memory PGMM. The second user output circuit 1102 is comprised of an input/output circuit with a relatively slow data transfer rate, such as an asynchronous communication interface, and a standard I10 port dedicated to an 8-bit system. Further, the second data memory is constituted by a low-speed, large-capacity dynamic RAM, although it is not particularly limited thereto.

Here, the microprocessor MPU and each functional block are coupled to B via an internal data bus that interfaces with the 8-bit system data bus SDB, but relatively high-speed data transfer is possible between them and the microprocessor MPU. The required functional blocks are the program memory PGMM, the first data memory DTM 1 and the first output circuit l101, and the microprocessor MPU.
The part that connects the internal data bus IDB with 16 bits and the microprocessor M
A second data memory DTM2, which is a functional block that does not necessarily require high-speed data transfer with the PU;
The part that connects the human output circuit 1102 and the microprocessor MPU has an internal data bus IDH with 8 bits.
Consists of bits.

In FIG. 1, MAA is a microprocessor MPU
When an address signal output from the arithmetic execution system EXC to the address bus AB is received and an internal functional block is designated by a predetermined bit of the address signal, the designated functional block is a 16-bit constituent part of the internal data bus IDB. or to which of the 8-bit components the address signal is coupled to, and when it is determined that the predetermined bit of the address signal specifies the functional block coupled to the 16-bit component, the microprocessor MPU This is an identification control unit that instructs the control system CNT that one access control is sufficient for read/write operations of 16-bit data.

Therefore, when the microprocessor MPU accesses a functional block that requires high-speed data transfer,
Since read/write operations can be executed in units of 16 bits, the number of data transfers is halved compared to when the internal data bus has a single bit configuration of 8 bits, and such data transfer efficiency is improved. This improvement helps reduce the number of command fetches and improve parameter transfer efficiency, contributing to improved data processing efficiency. Moreover, since the portion where the number of bits in the internal data bus IDB is increased is limited to the area between functional blocks that require high-speed data transfer, it does not hinder area efficiency and does not become parasitic on the internal data bus IDB. Signal propagation delays due to undesired load increases are also minimized.

According to the above embodiment, the following effects can be obtained.

(1) The internal data bus IDB to which the microprocessor MPU is connected has a 16-bit portion that is different from functional blocks such as the first data memory DTM that require relatively high-speed data transfer between the microprocessor MPU and the internal data bus IDB. When the microprocessor MPU accesses functional blocks that require high-speed data transfer, it can perform read/write operations on those functional blocks in units of 16 bits.

Compared to when the internal data bus has a single 8-bit configuration, the number of data transfers is halved, and such improved data transfer efficiency helps reduce the number of command fetches and improve parameter transfer efficiency. , can contribute to improving data processing efficiency.

(2) Since the portion of the internal data bus IDB where the number of bits is increased is limited to the area between functional blocks that require high-speed data transfer, it does not impede area efficiency;
The above effects can be obtained while minimizing the signal propagation delay caused by an undesirable increase in parasitic load on the internal data bus IDB.

Although the invention made by the present inventor has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, the configuration in which both the arithmetic execution system and the control system of the microprocessor are connected to an internal bus has been described, but a separate bus system for commands and other data or commands from the program memory can be used. A bypass supply method can be adopted.

Further, in the above embodiment, functional blocks that require relatively high-speed data transfer with the microprocessor are connected to a data memory, a program memory, a communication interface such as a local area network, and a communication interface such as a local area network. Although it has been described as a 16-bit timer/counter, it is not limited thereto; logically, it may be any functional block that requires relatively high-speed data transfer with the above-mentioned microprocessor. 6. For example, if it is desired to improve the operating efficiency of a microcomputer by reducing the number of instruction fetches, a program memory may be included in such a functional block.

Furthermore, the bit configuration of the internal data bus is 16 in the above embodiment.
The maximum data bit length of data that can be processed in the processor, data memory, etc. is not limited to the above-mentioned embodiments.
Further, the bit configuration of the internal bus is not limited to two levels, but can also be configured to three levels, for example, 8 bits, 16 bits, and 32 bits.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a single-chip microcomputer, which is the field of application that formed the background of the invention.
It is not limited to this, but it has a processor and is intelligent, and other than the processor, for example, DMA
C (dynamic memory access controller)
If the data processing device has built-in functional blocks such as It can be applied to conditions that have been formed.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the internal data bus to which the microprocessor is connected has a larger number of bits than the functional blocks that require relatively high-speed data transfer to and from the microprocessor. Because the microprocessor can access the increased bits of functional blocks that require high-speed data transfer, such functional blocks and the processor can The number of data transfers required during the process is reduced in proportion to the increase in the number of bits, and the undesirable increase in load on the internal data bus due to the increase in the number of bits is minimized.
Internal data transfer efficiency can be improved while minimizing signal propagation delays due to an increase in undesirable load parasitic on the internal data bus.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a data processing device according to the present invention. MPU... microprocessor, EXC... calculation execution system, CNT... control system, DTMI... first data memory, DTM2... second data memory, PGMM.
...Program memory, l101...1st person's output circuit, engineering 102...2nd person's output circuit, IDB...internal data bus, SDR...system data bus, MAA...
...Identification control unit.

Claims (1)

[Claims] 1. In a data processing device in which a processor and a plurality of functional blocks controlled by the processor are formed on one semiconductor substrate, bits of an internal data bus connecting the processor and each functional block 1. A data processing device characterized in that the number of parts is relatively increased in accordance with the number of parts connecting the processor and a predetermined functional block that requires relatively high-speed data transfer between the processor and the processor. 2. The data processing device according to claim 1, wherein the predetermined functional block that requires relatively high-speed data transfer is a program memory. 3. The data processing device according to claim 1 or 2, wherein the predetermined functional block that requires relatively high-speed data transfer is a program memory.