JPS63179537A - Mounting method of semiconductor device - Google Patents
Mounting method of semiconductor deviceInfo
- Publication number
- JPS63179537A JPS63179537A JP62012655A JP1265587A JPS63179537A JP S63179537 A JPS63179537 A JP S63179537A JP 62012655 A JP62012655 A JP 62012655A JP 1265587 A JP1265587 A JP 1265587A JP S63179537 A JPS63179537 A JP S63179537A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- circuit board
- bonding
- type semiconductor
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000000463 material Substances 0.000 claims description 6
- 239000011347 resin Substances 0.000 claims description 4
- 229920005989 resin Polymers 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 2
- 238000005476 soldering Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 4
- 239000007767 bonding agent Substances 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 239000006023 eutectic alloy Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〔概要〕
半導体装置の実装方法において、回路が形成されていな
い半導体装置のそれぞれの面を互いに接合することによ
り、回路基板に立体的に積み重ね実装し、実装効率を向
上したものである。[Detailed Description of the Invention] [Summary] In a semiconductor device mounting method, semiconductor devices on which no circuit is formed are stacked three-dimensionally on a circuit board by bonding each side of the device to each other, thereby improving mounting efficiency. This is what I did.
本発明は半導体装置を回路基板に実装する方法に関する
。The present invention relates to a method for mounting a semiconductor device on a circuit board.
電子装置を小型化するため、電子部品を高密度実装する
種々の方法が採られているが、一方法として、半導体装
置を立体的に積み重ね実装して実装効率を倍増する実装
方法が要望されている。In order to miniaturize electronic devices, various methods have been adopted for high-density mounting of electronic components, but there is a demand for a mounting method that doubles the mounting efficiency by stacking semiconductor devices three-dimensionally and mounting them. There is.
従来は第６図の側断面図に示すように、フェースダウン
型（Ｆａｃｅ Ｄｏｗｎ Ｔｙｐｅ）半導体装置１１、
例えばフリップチップ型（Ｆｌｉｐ Ｃｈｉｐ Ｔｙｐ
ｅ）半導体装置とペアチップ型（Ｂａｒｅ Ｃｈｉｐ
Ｔｙｐｅ）半導体装置１２を同じ回路基板１４上に実装
する場合、それぞれのスペースを専有し、別位置に配置
して実装される。Conventionally, as shown in the side sectional view of FIG. 6, a face-down type semiconductor device 11,
For example, flip chip type
e) Semiconductor device and Bare Chip type
Type) When semiconductor devices 12 are mounted on the same circuit board 14, they occupy separate spaces and are mounted at different locations.
即ち、フリップチップ型半導体装置１１は、回路基板１
４の所定位置のランド１４−１に載せてリフロー半田付
けされ、
一方、ペアチップ型半導体装置１２は、別の所定位置の
ランド１４−２に載せて接合材１２−１、例えばりフロ
ー半田より高融点の半田接着法、またはＡｕＳｉなどの
共晶合金接着法によって接合され、上面の電極パッド１
２−１はボンディング線１２−２、例えばＡＪ ＆１や
Ａｕ線などを用いて超音波ボンディング法や熱圧着法に
よってワイヤボンディング接続される。That is, the flip-chip semiconductor device 11 includes a circuit board 1
On the other hand, the paired chip type semiconductor device 12 is placed on a land 14-1 at a predetermined position of 4 and reflow soldered.On the other hand, the paired chip type semiconductor device 12 is placed on a land 14-2 at another predetermined position and soldered with a bonding material 12-1, for example, higher than flow soldering. The electrode pad 1 on the top surface is bonded by melting point solder bonding method or eutectic alloy bonding method such as AuSi.
2-1 is connected by wire bonding using a bonding wire 12-2, such as AJ&1 or Au wire, by ultrasonic bonding or thermocompression bonding.
しかしながら、このような上記実装方法によれば、フリ
ップチップ型半導体装置の上面やペアチップ型半導体装
置の下面は、回路が形成されていないために実装上、回
路素子としての機能を果たしていない場合が多く、実際
上の空きスペースとなっており、その分だけ実装効率を
低下させているといった問題があった。However, according to the above-described mounting method, the top surface of a flip-chip type semiconductor device or the bottom surface of a pair-chip type semiconductor device often does not function as a circuit element due to no circuit formed thereon. , there is a problem in that it is actually empty space, and the implementation efficiency is reduced by that amount.
本発明は上記問題点を解決する半導体装置の実装方法を
提供するものである。The present invention provides a method for mounting a semiconductor device that solves the above problems.
従来方法における上記問題点は、回路が形成されていな
い半導体装置のそれぞれの面を互いに接合することによ
って解決される。The above-mentioned problems in the conventional method are solved by bonding the respective surfaces of the semiconductor device on which no circuit is formed to each other.
立体的に積み重ねて接合することにより、実装スペース
を約半減することができる。By stacking and bonding three-dimensionally, the mounting space can be reduced by approximately half.
また、モールド成形することによって、単一部品となり
、取り扱いや実装が容易になる。Moreover, by molding, it becomes a single component, which makes handling and mounting easier.
以下第１図〜第５図に示す各実施例により本発明の要旨
を具体的に説明する。なお図中、同一符号は同一装置、
部材を示す。The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 to 5. In the figures, the same symbols indicate the same equipment,
Shows the parts.
第１図は実施例１の実装工程順を示す側断面図であって
、
第１図（ａ）は、フェースダウン型半導体装置１、例え
ばフリップチップ型半導体装置を回路基板４上のランド
４−１にリフロー半田付は法によって実装し、
第１図（ｂｌは、このフリップチップ型半導体装置ｌの
上面を洗浄後、接合材１−１、例えばリフロー半田より
低融点半田、または銀入りエポキシ系樹脂によるダイボ
ンディング接着法等により、上記上面にペアチップ型半
導体装置２の回路が形成されていない面を載せ、積み重
ね接合し、第１図（Ｃ）は、ペアチップ型半導体装置２
の電極パッド２−１を洗浄後、回路基板４のランド４−
１と電極パッド２−１とをボンディング線２−２、例え
ばＡｕ線やＡ１線などを用いて超音波ボンディング法や
熱圧着法によってワイヤボンディング接続する。FIG. 1 is a side cross-sectional view showing the order of the mounting process in Example 1. FIG. 1, reflow soldering is carried out by the method shown in FIG. The surface of the paired chip type semiconductor device 2 on which no circuit is formed is placed on the upper surface by a die bonding adhesive method using resin, etc., and the paired chip type semiconductor device 2 is stacked and bonded.
After cleaning the electrode pad 2-1 of the circuit board 4, the land 4-1 of the circuit board 4 is cleaned.
1 and the electrode pad 2-1 are connected by wire bonding using a bonding wire 2-2, such as an Au wire or an A1 wire, by ultrasonic bonding or thermocompression bonding.
第２図は実施例２の実装工程順を示す側断面図であって
、
第２図（ａｌは、フリップチップ型半導体装置１とペア
チップ型半導体装置２とを予め、回路基板４に実装する
前に接合したものであって、それぞれの回路形成されて
いない面同士を接合材１−１、例えばりフロー半田より
高融点の半田接着法、またはＡｕＳｉ等の共晶合金接着
法によって積み重ね接合し、
第２図（ｂ）は、フリップチップ型半導体装置１を回路
基板４のランド４−１上にリフロー半田付は法によって
実装し、
第２図（Ｃ）は、ペアチップ型半導体装置２の電極パッ
ド２−１を洗浄後、回路基板４のランド４−１にボンデ
ィング線２−２、例えばＡｕ線やＡＩ！線などを用いて
超音波ボンディング法や熱圧着法によってワイヤボンデ
ィング接続する。FIG. 2 is a side cross-sectional view showing the order of the mounting process in Example 2. The surfaces on which circuits are not formed are stacked and bonded to each other using a bonding material 1-1, such as a solder bonding method with a higher melting point than flow solder, or a eutectic alloy bonding method such as AuSi, FIG. 2(b) shows the flip chip type semiconductor device 1 mounted on the land 4-1 of the circuit board 4 by reflow soldering, and FIG. 2(C) shows the electrode pads of the paired chip type semiconductor device 2. After cleaning 2-1, a bonding wire 2-2, such as an Au wire or an AI! wire, is wire-bonded to the land 4-1 of the circuit board 4 by ultrasonic bonding or thermocompression bonding.
第３図は実施例３の側断面図であって、上記第１図、ま
たは第２図におけるフリップチップ型半導体装置１をビ
ームリード型半導体装置３にしたものである。FIG. 3 is a side sectional view of Embodiment 3, in which the flip-chip semiconductor device 1 in FIG. 1 or 2 is replaced with a beam-lead semiconductor device 3.
第４図は実施例４の側断面図であって、上記回路基板４
のランド４−１の替わりにリードフレーム５を用いたも
ので、第２図（ａ）において積み重ね実装されたフリッ
プチップ型半導体装置１をリードフレーム５上に載せて
リフロー半田付けし、ペアチップ型半導体装置２をリー
ドフレーム５にワイヤボンディング接続し、樹脂材６で
モールド成形したものである。FIG. 4 is a side sectional view of the fourth embodiment, showing the circuit board 4
A lead frame 5 is used in place of the land 4-1, and the stacked flip-chip type semiconductor devices 1 shown in FIG. The device 2 is connected to a lead frame 5 by wire bonding and molded with a resin material 6.
第５図は実施例５の側断面図であって、フリップチップ
型半導体装Ｗ１とペアチップ型半導体装置２との間に導
電性と熱伝導性の優れた接地用リード７、例えば銅合金
や４２アロイリード、または金合金やアルミ合金リボン
リードなどを挟んで接合したもので、接地用リード７は
回路基板の接地用ランド４−２にリフロー半田付け、ま
たは超音波ボンディング法や熱圧着法によって接続され
る。FIG. 5 is a side sectional view of Embodiment 5, in which a grounding lead 7 having excellent electrical conductivity and thermal conductivity is provided between the flip-chip type semiconductor device W1 and the pair-chip type semiconductor device 2. The grounding lead 7 is connected to the grounding land 4-2 of the circuit board by reflow soldering, ultrasonic bonding, or thermocompression bonding. be done.
上記それぞれの実施例は、何れも半導体装置の回路を形
成していない面を背中合わせにして接合したものであっ
て、実装効率を約２倍に高め、回路基板の高密度実装化
が図れる。In each of the above-mentioned embodiments, the surfaces of the semiconductor devices on which no circuit is formed are bonded back to back, and the mounting efficiency can be approximately doubled and the circuit board can be mounted at high density.
また、上記半導体装置間に接地用リードを挟着すること
により、静電シールドなどを強化できる。Furthermore, by sandwiching a grounding lead between the semiconductor devices, electrostatic shielding and the like can be strengthened.
以上、詳述したように本発明によれば、半導体装置の実
際上の空きスペースとなっている面を組み合わせ、立体
的に積み重ね２重実装することによって回路基板への実
装効率を格段に向上できるといった実用上極めて有用な
効果を発揮する。As described in detail above, according to the present invention, the mounting efficiency on a circuit board can be significantly improved by combining the surfaces of semiconductor devices that are actually empty spaces and stacking them three-dimensionally for double mounting. It exhibits extremely useful effects in practical terms.
第１図（ａ）、 （ｂ）、 （Ｃ）は本発明による実施
例１の実装工程順を示す側断面図、
第２図（ａ）、 （ｂ）、 （Ｃ）は本発明による実施
例２の実装工程順を示す側断面図、
第３図は本発明による実施例３の側断面図、第４図は本
発明による実施例４の側断面図、第５図は本発明による
実施例５の側断面図、第６図は従来技術による側断面図
、
である。
図において、
ｌはフェースダウン型半導体装置（フリップチップ型半
導体装置）、
１−１は接合材、
２はペアチップ型半導体装置、
２−１は電極パッド、
２−２はボンディング線、
３はビームリード型半導体装置、
４は回路基板、
４−１はランド、
５はリードフレーム、
６は樹脂材、
７は接地用リード、
を示す。
第２図FIGS. 1(a), (b), and (C) are side sectional views showing the order of mounting steps in Example 1 according to the present invention. FIGS. 2(a), (b), and (C) are implementations according to the present invention. FIG. 3 is a side sectional view of Embodiment 3 according to the present invention, FIG. 4 is a side sectional view of Embodiment 4 according to the present invention, and FIG. 5 is a side sectional view showing the mounting process order of Example 2. FIG. 6 is a side sectional view of Example 5, and FIG. 6 is a side sectional view of the prior art. In the figure, l is a face-down type semiconductor device (flip chip type semiconductor device), 1-1 is a bonding material, 2 is a paired chip type semiconductor device, 2-1 is an electrode pad, 2-2 is a bonding line, 3 is a beam lead type semiconductor device, 4 is a circuit board, 4-1 is a land, 5 is a lead frame, 6 is a resin material, and 7 is a grounding lead. Figure 2
Claims (1)
それぞれの面を互いに接合する工程を含むことを特徴と
する半導体装置の実装方法。 〔２〕上記接合した半導体装置（１、２）をそれぞれリ
ードフレーム（５）に接続した後、樹脂材（６）にてモ
ールド成形する工程を含むことを特徴とする特許請求の
範囲第１項記載の半導体装置の実装方法。 〔３〕上記半導体装置（１、２）間に接地用リード（７
）を挟着する工程を含むことを特徴とする特許請求の範
囲第１項記載の半導体装置の実装方法。[Scope of Claims] [1] A method for mounting a semiconductor device, comprising the step of bonding respective surfaces of semiconductor devices (1, 2) on which no circuit is formed. [2] Claim 1, which includes a step of molding with a resin material (6) after each of the bonded semiconductor devices (1, 2) is connected to a lead frame (5). A method for mounting the described semiconductor device. [3] Grounding lead (7) between the semiconductor devices (1, 2)
2. A method for mounting a semiconductor device according to claim 1, further comprising the step of sandwiching a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012655A JPS63179537A (en) | 1987-01-21 | 1987-01-21 | Mounting method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62012655A JPS63179537A (en) | 1987-01-21 | 1987-01-21 | Mounting method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63179537A true JPS63179537A (en) | 1988-07-23 |
Family
ID=11811374
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62012655A Pending JPS63179537A (en) | 1987-01-21 | 1987-01-21 | Mounting method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63179537A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5952725A (en) * | 1996-02-20 | 1999-09-14 | Micron Technology, Inc. | Stacked semiconductor devices |
| US6407456B1 (en) | 1996-02-20 | 2002-06-18 | Micron Technology, Inc. | Multi-chip device utilizing a flip chip and wire bond assembly |
| US6784023B2 (en) | 1996-05-20 | 2004-08-31 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US6951774B2 (en) * | 2001-04-06 | 2005-10-04 | Renesas Technology Corp. | Semiconductor device and method of manufacturing the same |
| US7109059B2 (en) | 1996-11-20 | 2006-09-19 | Micron Technology, Inc. | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
-
1987
- 1987-01-21 JP JP62012655A patent/JPS63179537A/en active Pending
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7166495B2 (en) * | 1996-02-20 | 2007-01-23 | Micron Technology, Inc. | Method of fabricating a multi-die semiconductor package assembly |
| US6337227B1 (en) | 1996-02-20 | 2002-01-08 | Micron Technology, Inc. | Method of fabrication of stacked semiconductor devices |
| US6407456B1 (en) | 1996-02-20 | 2002-06-18 | Micron Technology, Inc. | Multi-chip device utilizing a flip chip and wire bond assembly |
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