JPH02249981A - Semiconductor device and mounting method using the same and continuity testing method - Google Patents
Semiconductor device and mounting method using the same and continuity testing methodInfo
- Publication number
- JPH02249981A JPH02249981A JP1070643A JP7064389A JPH02249981A JP H02249981 A JPH02249981 A JP H02249981A JP 1070643 A JP1070643 A JP 1070643A JP 7064389 A JP7064389 A JP 7064389A JP H02249981 A JPH02249981 A JP H02249981A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- electrode
- substrate
- hole
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000012360 testing method Methods 0.000 title claims description 11
- 238000000034 method Methods 0.000 title claims description 10
- 239000008188 pellet Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 20
- 238000010998 test method Methods 0.000 claims description 9
- 229920005989 resin Polymers 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920001187 thermosetting polymer Polymers 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 229920002050 silicone resin Polymers 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置のパッケージ技術に関し、特に多
ビン化・低コスト化が要求されるモールドタイプのパッ
ケージ構造を備えた半導体装置およびそれを用いた実装
方法ならびに導通試験方法に適用して有効な技術に関す
る。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to packaging technology for semiconductor devices, and in particular to semiconductor devices having a mold-type package structure that requires a large number of bins and low cost, and the use thereof. This article relates to techniques that are effective when applied to the mounting method and continuity test method used.
［従来の技術］
コンビコータの大容量化、高速化に伴い、論理ＬＳＩや
画像処理ＬＳＩなどが実装されるパッケージの小型化お
よび多ビン化が要求されている。[Prior Art] As the capacity and speed of combi coaters increase, there is a demand for smaller packages in which logic LSIs, image processing LSIs, and the like are mounted and to increase the number of bins.
そして、これらの要求に対応できるパッケージ技術に関
しては、たとえば日経マグロウヒル社、昭和５９年６月
４日発行、「日経エレクトロニクスＪＰ１４１〜Ｐ１５
２に記載されている。Regarding packaging technology that can meet these demands, for example, Nikkei McGraw-Hill, published June 4, 1980, "Nikkei Electronics JP141-P15"
It is described in 2.
小型化および多ピン化に適したパッケージとしては、ピ
ン挿入タイプでは、Ｐ Ｇ Ａ （Ｐｉｎ Ｇｒｉｄ＾
ｒｒａｙ） 構造が、また表面実装タイプでは、ＱＦ
Ｐ（Ωｕａｃｌ Ｆｌａｔ Ｐａｃｋａｇｅ ）構造が
知らレテオリ、表面実装タイプのＱＦＰについては、ユ
ーザによるリードの縦方向の平坦度に対する要求が厳し
く、またユーザにおいてもリードを折り曲げないような
注意が必要とされている。また、半田作業においては、
熱衝撃によりリードフレームと樹脂との間に隙間が開き
、パッケージの耐湿性を悪くするために半田デイツプを
行うことができないという欠点がある。As a package suitable for downsizing and increasing the number of pins, the pin insertion type package is PGA (Pin Grid^
rray) structure, and surface mount type, QF
For surface mount type QFPs with a well-known P (Ωuacl flat package) structure, users have strict requirements for the vertical flatness of the leads, and users must also be careful not to bend the leads. . In addition, in soldering work,
There is a drawback that solder dipping cannot be performed because a gap opens between the lead frame and the resin due to thermal shock, which impairs the moisture resistance of the package.
一方、ピン挿入タイプのＰＧＡ構造は、ユーザにおける
実装が容易とされ、またパッケージの裏面全体をリード
ビンの取り出しに利用できることカラ、３００〜５００
ピンなどのような超多ビンが必要とされるＬＳＩに最適
なパッケージ構造とされている。On the other hand, the pin insertion type PGA structure is said to be easy for the user to mount, and the entire back side of the package can be used to take out the lead bin.
It is said to be an optimal package structure for LSIs that require a large number of pins and other bins.
［発明が解決しようとする課題］
ところが、前記のような従来技術においては、ＰＧＡ構
造とすることにより小型化および多ピン化されることに
ついては配慮がなされているものの、コスト的に高くな
る他、実装時の外部電極のブリッジやリードの位置ずれ
などに対する配慮がなされておらず、これらに関する不
良が発生する恐れがある。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, although consideration has been given to miniaturization and increase in the number of pins by using the PGA structure, it also increases the cost and increases the number of pins. However, there is no consideration given to bridges of external electrodes or misalignment of leads during mounting, and there is a risk that defects related to these may occur.
また、このような課題に鑑み、本発明者がさらに鋭意研
究したところ、ＰＧＡ構造でモールドタイプに形成する
ことにより、低コストでかつ多ピン化されたパッケージ
構造の半導体装置が得られることに本発明者は着目した
。In addition, in view of these problems, the present inventor conducted further intensive research and found that by forming a mold type semiconductor device with a PGA structure, it is possible to obtain a semiconductor device with a package structure that is low in cost and has a large number of pins. The inventor paid attention.
そこで、本発明の目的は、面に電極が分布されたモール
ドパッケージ構造とされ、低コストでかつ多ピン化され
た半導体装置およびそれを用いた実装方法ならびに導通
試験方法を提供することにある。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a low-cost semiconductor device having a molded package structure with electrodes distributed on its surface and a large number of pins, a mounting method using the same, and a continuity testing method.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
［課題を解決するための手段］
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions is as follows.
すなわち、本発明の半導体装置は、集積回路が形成され
た半導体ベレットが内蔵され、該半導体ベレットの集積
回路に接続される電極が分布されるモールドパッケージ
構造の半導体装置であって、前記モールドパッケージに
貫通される複数の開口部が形成され、該開口部に前記電
極が設けられているものである。That is, the semiconductor device of the present invention is a semiconductor device having a mold package structure in which a semiconductor pellet in which an integrated circuit is formed is built-in, and electrodes connected to the integrated circuit of the semiconductor pellet are distributed, A plurality of openings are formed to be penetrated, and the electrodes are provided in the openings.
また、前記電極の一端側が前記開口部の上面方向または
下面方向の一方向に、折り曲げられ、外部と接続される
ものである。Further, one end side of the electrode is bent in one direction toward the upper surface or the lower surface of the opening, and is connected to the outside.
さらに、前記電極に貫通孔が形成され、該貫通孔に外部
接続用のリードビンが垂設されるものである。Furthermore, a through hole is formed in the electrode, and a lead bin for external connection is vertically provided in the through hole.
また、本発明の半導体装置を用いた実装方法は、前記半
導体装置が、該半導体装置の電極を通じて基板または基
板に実装されたソケットの電極に接続されることにより
、前記基板に実装されるものである。Further, in the mounting method using the semiconductor device of the present invention, the semiconductor device is mounted on the substrate by connecting to the substrate or the electrode of a socket mounted on the substrate through the electrode of the semiconductor device. be.
さらに、本発明の半導体装置を用いた導通試験方法は、
前記半導体装置が配線パターンまたはスルーホールが形
成された基板に実装され、前記半導体装置の電極と前記
基板の配線パターンまたはスルーホールとの間において
導通試験が行われるものである。Furthermore, the continuity test method using the semiconductor device of the present invention includes:
The semiconductor device is mounted on a substrate on which a wiring pattern or a through hole is formed, and a continuity test is performed between an electrode of the semiconductor device and the wiring pattern or through hole of the substrate.
［作用コ
前記した半導体装置によれば、モールドパッケージに貫
通される複数の開口部が形成され、この開口部に半導体
ベレットの集積回路に接続される電極が設けられること
により、たとえば電極の一端側が開口部の上面方向また
は下面方向の一方向に折り曲げられたり、または電極に
形成された貫通孔にリードピンが垂設されることにより
外部との接続が可能とされる。[Function] According to the above-described semiconductor device, a plurality of openings are formed through the mold package, and electrodes connected to the integrated circuit of the semiconductor pellet are provided in the openings, so that, for example, one end of the electrode is Connection with the outside is made possible by bending the opening in one direction toward the upper surface or the lower surface, or by vertically disposing a lead pin in a through hole formed in the electrode.
また、前記した半導体装置を用いた実装方法によれば、
半導体装置が、この半導体装置の電極を通じて基板また
は基板に実装されたソケットの電極に接続されることに
より基板への実装が可能とされる。Furthermore, according to the mounting method using the semiconductor device described above,
A semiconductor device can be mounted on a substrate by being connected to an electrode of a substrate or a socket mounted on the substrate through an electrode of the semiconductor device.
さらに、前記した半導体装置を用いた導通試験方法によ
れば、半導体装置が配線パターンまたはスルーホールが
形成された基板に実装されることにより、半導体装置の
電極と基板の配線パターンまたはスルーホールとの間に
おいて導通試験が可能とされる。Furthermore, according to the continuity test method using the semiconductor device described above, the semiconductor device is mounted on a board on which a wiring pattern or through holes are formed, so that the electrodes of the semiconductor device and the wiring pattern or through holes of the board are connected. Continuity testing is possible between the two.
［実施例］
第１図は本発明の一実施例である半導体装置を示す断面
図、第２図は第１図の変形例を示す要部断面図、第３図
は第１図の他の変形例を示す要部断面図、第４図および
第５図は第１図の半導体装第２図の半導体装置を用いた
導通試験方法を説明する断面図、第７図は第３図の半導
体装置を用いた導通試験方法を説明する断面図である。[Example] FIG. 1 is a cross-sectional view showing a semiconductor device as an example of the present invention, FIG. 2 is a cross-sectional view of main parts showing a modification of FIG. 1, and FIG. 4 and 5 are cross-sectional views illustrating a continuity test method using the semiconductor device of FIG. 1 and the semiconductor device of FIG. 2. FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 3. FIG. 3 is a cross-sectional view illustrating a continuity test method using the device.
まず、第１図により本実施例の半導体装置の構成を説明
する。First, the configuration of the semiconductor device of this embodiment will be explained with reference to FIG.
本実施例の半導体装置１は、たとえばモールドタイプの
パッケージ構造であって、半導体ベレット２およびリー
ドフレーム（電極）３などで構成され、熱硬化性樹脂４
によりモールドされている。The semiconductor device 1 of this embodiment has a mold type package structure, for example, and is composed of a semiconductor pellet 2, a lead frame (electrode) 3, etc., and a thermosetting resin 4.
It is molded by.
半導体ベレット２の表面には、集積回路（図示せず）が
形成され、その所定箇所に電極バッド５が接合されてい
る。そして、電極バッド５を介して、リードフレーム３
の上面に金（Ａｕ）またはアルミニウム（Ａｌ）、ある
いは銅（Ｃｕ）系材料などのワイヤ６によりワイヤボン
ディングされている。また、半導体ベレット２は、銀（
Ａｇ）ペーストおよびシリコーン樹脂などで形成される
接合材７を介して、ニッケル右よび金などの薄膜を施し
た金属製の薄板で形成さ九るダイパッド８リードフレー
ム（電極）３は、たとえば長円形状の金属製の薄板で形
成され、その一端側に外部接続用のり−ドビンが挿通さ
れる貫通孔９が形成されている。An integrated circuit (not shown) is formed on the surface of the semiconductor pellet 2, and electrode pads 5 are bonded to predetermined locations thereof. Then, via the electrode pad 5, the lead frame 3
The wire 6 is wire-bonded to the upper surface of the wire 6 made of gold (Au), aluminum (Al), or copper (Cu)-based material. In addition, the semiconductor pellet 2 is made of silver (
Ag) A die pad 8 formed of a thin metal plate coated with a thin film of nickel or gold, etc., through a bonding material 7 formed of paste, silicone resin, etc. It is formed of a thin metal plate having a shape, and has a through hole 9 formed at one end thereof into which a glue dowel for external connection is inserted.
さらに、半導体ペレット２およびリードフレーム３は、
ワイヤボンディング後に、リードフレーム３の貫通孔９
側に上下に貫通された開口部１０が形成される構造にお
いて、エポキシ樹脂またはシリコーン樹脂などの熱硬化
性樹脂４によりモールドされている。Furthermore, the semiconductor pellet 2 and the lead frame 3 are
After wire bonding, the through hole 9 of the lead frame 3
In a structure in which an opening 10 is formed vertically through the side, it is molded with a thermosetting resin 4 such as epoxy resin or silicone resin.
次に、本実施例の作用について説明する。Next, the operation of this embodiment will be explained.
本実施例の半導体装置１は、たとえば以下の方法により
製造される。The semiconductor device 1 of this embodiment is manufactured, for example, by the following method.
まず、半導体ペレット２がグイバッド８上にグイボンデ
ィングされた後に、ワイヤ６により半導体ペレット２の
電極バッド５とリードフレーム３との間のワイヤボンデ
ィングが行われる。続いて、熱硬化性樹脂４により所定
の領域がモールド封止される。この時、リードフレーム
３０貫通孔９の位置にモールド金型が用いられることに
より、第１図にような開口部１０が形成される。First, after the semiconductor pellet 2 is bonded onto the bond pad 8, wire bonding is performed between the electrode pad 5 of the semiconductor pellet 2 and the lead frame 3 using the wire 6. Subsequently, a predetermined area is mold-sealed with thermosetting resin 4. At this time, a mold is used at the position of the through hole 9 of the lead frame 30, so that an opening 10 as shown in FIG. 1 is formed.
以上のように製造された半導体装置１においては、リー
ドフレーム３の貫通孔９側に上下に貫通された開口部１
０が形成されるモールドタイプのパッケージ構造とされ
ることにより、たとえば第２図および第３図のような構
造の半導体装置１を得ることができる。In the semiconductor device 1 manufactured as described above, the opening 1 vertically penetrates the through hole 9 side of the lead frame 3.
By adopting a mold type package structure in which 0 is formed, it is possible to obtain a semiconductor device 1 having a structure as shown in FIGS. 2 and 3, for example.
第２図の半導体装置１は、開口部１０の上面側からパン
チングピン１１によりパンチングされることによって、
リードフレーム３の貫通孔９側が下面側に折り曲げられ
て外部と接続が可能とされる。一方、第３図の半導体装
置１においては、リードフレーム３０貫通孔９にリード
ピン１２が挿通されることにより外部との接続が可能と
される。The semiconductor device 1 shown in FIG. 2 is punched from the upper surface side of the opening 10 by the punching pin 11.
The through hole 9 side of the lead frame 3 is bent downward to enable connection with the outside. On the other hand, in the semiconductor device 1 shown in FIG. 3, the lead pins 12 are inserted into the through holes 9 of the lead frame 30, thereby allowing connection to the outside.
また、第１図の半導体装置１にふいては、たとえば第４
図に示すようにピン１３が垂設された基板１４に実装す
ることもできる。さらに、第５図のようにスルーホール
１５が開設された基板１４に両面がピン１３タイプのソ
ケット１６を介在すさらに、第２図および第３図の半導
体装置１については、第６図および第７図のように配線
パターン１７およびスルーホール１５が形成された基板
１４に実装された状態において、半導体装置１のリード
フレーム３と基板１４の配線パターン１７またはスルー
ホール１５との間におけるテストプローブ１８による導
通試験が可能とされる。Further, in the semiconductor device 1 of FIG. 1, for example, a fourth
As shown in the figure, it can also be mounted on a substrate 14 on which pins 13 are vertically provided. Furthermore, as shown in FIG. 5, a socket 16 having pins 13 on both sides is interposed on the substrate 14 in which a through hole 15 is formed. Test probe 18 between lead frame 3 of semiconductor device 1 and wiring pattern 17 or through hole 15 of substrate 14 when mounted on substrate 14 on which wiring pattern 17 and through hole 15 are formed as shown in FIG. It is possible to conduct continuity tests using
このように、本実施例の半導体装置１においては、上下
に貫通された開口部１０が形成されるパッケージ構造と
されることにより、リードフレーム３またはリードピン
１２によるリード形成が容易とされ、導通試験および搬
送後にリード形成を行うことができる。これにより、ユ
ーザにおけるリード形成が可能とされ、リードフレーム
３およびリードピン１２０曲がり防止が可能である。As described above, the semiconductor device 1 of this embodiment has a package structure in which the openings 10 are vertically penetrated, so that lead formation using the lead frame 3 or the lead pins 12 is facilitated, and continuity testing is facilitated. And lead formation can be performed after transportation. This allows the user to form the leads and prevents the lead frame 3 and lead pins 120 from bending.
また、モールドタイプのＰＧＡ構造とすることにより、
ＰＧＡ構造の多ピン化とモールド構造による低コスト化
とを兼ね備えた半導体装置１を得ることができる。In addition, by using a mold type PGA structure,
It is possible to obtain a semiconductor device 1 that has both an increased number of pins in the PGA structure and a lower cost due to the molded structure.
以上、本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は前記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。As above, the invention made by the present inventor has been specifically explained based on Examples, but it should be noted that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. Not even.
たとえば、本実施例のリードフレーム３によるリード形
成ついては、半導体ペレット２の周囲に一列に形成した
場合について説明したが、本発明は前記実施例に限定さ
れるものではなく、格子状またはランダムに分布される
モールドタイプのパッケージ構造に広く適用可能である
。For example, regarding the lead formation using the lead frame 3 of this embodiment, the case where the leads are formed in a line around the semiconductor pellet 2 has been described, but the present invention is not limited to the above embodiment, and the leads are distributed in a lattice shape or randomly. It is widely applicable to mold type package structures.
また、本実施例においては、リードフレーム３の折り曲
げおよびリードピン１２の挿通により外部接続が可能と
されたが、これに限定されるものではなく、たとえば第
４図および第５図のように基板への実装、または第６図
および第７図のように導通試験に使用するなどパッケー
ジ構造の用途に応じて広く適用可能である。Furthermore, in this embodiment, external connection is possible by bending the lead frame 3 and inserting the lead pins 12, but the invention is not limited to this, and for example, as shown in FIGS. It can be widely applied depending on the purpose of the package structure, such as mounting or continuity testing as shown in FIGS. 6 and 7.
［発明の効果］
本願にふいて開示される発明のうち、代表的な下記のと
おりである。[Effects of the Invention] Among the inventions disclosed in this application, the following are representative.
（１）、モールドパッケージに貫通される複数の貫通孔
が形成され、この貫通孔に半導体ペレットの集積回路に
接続される電極が設けられることにより、たとえば電極
の一端側を貫通孔の上面方向また（１下面方向の一方向
に折り曲げたり、または電極に形成された貫通孔にリー
ドピンを垂設することができるので、半導体装置のリー
ド形成が容易とされ、外部との接続が可能である。(1) A plurality of through holes are formed through the mold package, and electrodes connected to the integrated circuit of the semiconductor pellet are provided in the through holes, so that, for example, one end of the electrode is directed toward the top surface of the through hole or (Since the lead pins can be bent in one direction toward the lower surface, or the lead pins can be vertically provided in the through holes formed in the electrodes, it is easy to form leads for the semiconductor device, and connection with the outside is possible.
Ｃ２）、前記（１）により、パッケージ面に電極を容易
にまた安価に設置できるので、低コストでかつ多ピン化
されたモールドタイプのパッケージ構造の半導体装置を
得ることができる。C2) According to (1) above, electrodes can be easily and inexpensively installed on the package surface, so it is possible to obtain a semiconductor device having a mold type package structure with a large number of pins at low cost.
（３）、半導体装置がその電極を通じて基板または基板
に実装されたソケットの電極に接続されることにより、
半導体装置の基板への実装が可能である。(3) By connecting the semiconductor device to the electrode of the board or the socket mounted on the board through its electrode,
It is possible to mount a semiconductor device on a substrate.
（４）、前記（３）により、半導体装置の実装時に外部
電極のブリッジあるいはリードの位置ずれやそれに伴う
不良の発生を防止することができる。(4) According to (3) above, it is possible to prevent bridges of external electrodes or misalignment of leads and associated defects when mounting a semiconductor device.
（５）、半導体装置が配線パターンまたはスルーホール
が形成された基板に実装されることにより、半導体装置
の電極と基板の配線パターンまたはスルーホールとの間
において導通試験が容易かつ確実に可能である。(5) By mounting the semiconductor device on a substrate on which a wiring pattern or through hole is formed, continuity testing can be easily and reliably performed between the electrode of the semiconductor device and the wiring pattern or through hole of the substrate. .
第１図は本発明の一実施例である半導体装置を示す断面
図、
第２図は第１図の実施例の変形例を示す要部断面図、
第３図は第１図の他の変形例を示す要部断面図、第４図
および第５図は第１図の半導体装置を用いた実装方法を
説明する断面図、
第６図は第２図の半導体装置を用いた導通試験方法を説
明する断面図、
第７図は第３図の半導体装置を用いた導通試験方法を説
明する断面図である。
１・・・半導体装置、２・・・半導体ペレット、３・・
・リードフレーム（電極）、４・・・熱硬化性樹脂、５
・・・電極パッド、６・・・ワイヤ、７・・・接合材、
８・・・グイパッド、９・・・貫通孔、１０・・・開口
部、１１・・・パンチングピン、１２・・・リードピン
、１３・・・ピン、１４・・・基板、１５・・・スルー
ホール、１６・・・ソケット、１７・・・配線パターン
、１８・・・テストプローブ。
／
＼
ｌ−で
第
図
１６：ソケット
第
図
第
図FIG. 1 is a sectional view showing a semiconductor device as an embodiment of the present invention, FIG. 2 is a sectional view of essential parts showing a modification of the embodiment of FIG. 1, and FIG. 3 is another modification of FIG. 1. 4 and 5 are cross-sectional views illustrating a mounting method using the semiconductor device shown in FIG. 1, and FIG. 6 is a sectional view showing a continuity test method using the semiconductor device shown in FIG. Cross-sectional view for explanation FIG. 7 is a cross-sectional view for explaining a continuity test method using the semiconductor device of FIG. 1... Semiconductor device, 2... Semiconductor pellet, 3...
・Lead frame (electrode), 4...Thermosetting resin, 5
... Electrode pad, 6... Wire, 7... Bonding material,
8... Gui pad, 9... Through hole, 10... Opening, 11... Punching pin, 12... Lead pin, 13... Pin, 14... Board, 15... Through Hall, 16...Socket, 17...Wiring pattern, 18...Test probe. / \ l- Figure 16: Socket Figure Figure
Claims (1)
該半導体ペレットの集積回路に接続される電極が分布さ
れるモールドパッケージ構造の半導体装置であって、前
記モールドパッケージに貫通される複数の開口部が形成
され、該開口部に前記電極が設けられていることを特徴
とする半導体装置。 ２、前記電極の一端側が前記開口部の上面方向または下
面方向の一方向に折り曲げられ、外部と接続されること
を特徴とする請求項１記載の半導体装置。 ３、前記電極に貫通孔が形成され、該貫通孔に外部接続
用のリードピンが垂設されることを特徴とする請求項１
記載の半導体装置。 ４、請求項１、２または３記載の半導体装置を用いた実
装方法であって、該半導体装置の電極を通じて基板また
は基板に実装されたソケットの電極に接続することによ
り、前記基板に前記半導体装置を実装することを特徴と
する半導体装置を用いた実装方法。 ５、請求項１、２または３記載の半導体装置を用いた導
通試験方法であって、配線パターンまたはスルーホール
が形成された基板に前記半導体装置を実装し、前記半導
体装置の電極と前記基板の配線パターンまたはスルーホ
ールとの間において導通試験を行うことを特徴とする半
導体装置を用いた導通試験方法。[Claims] 1. Contains a semiconductor pellet in which an integrated circuit is formed,
A semiconductor device having a mold package structure in which electrodes connected to an integrated circuit of the semiconductor pellet are distributed, wherein a plurality of openings are formed through the mold package, and the electrodes are provided in the openings. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein one end of the electrode is bent in one direction toward the top or bottom of the opening and is connected to the outside. 3. Claim 1, wherein a through hole is formed in the electrode, and a lead pin for external connection is vertically provided in the through hole.
The semiconductor device described. 4. A mounting method using the semiconductor device according to claim 1, 2 or 3, wherein the semiconductor device is mounted on the substrate by connecting to an electrode of a substrate or a socket mounted on the substrate through an electrode of the semiconductor device. A mounting method using a semiconductor device characterized by mounting. 5. A continuity test method using the semiconductor device according to claim 1, 2 or 3, wherein the semiconductor device is mounted on a substrate on which a wiring pattern or a through hole is formed, and the electrodes of the semiconductor device and the substrate are connected to each other. A continuity test method using a semiconductor device, characterized in that a continuity test is performed between a wiring pattern or a through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1070643A JPH02249981A (en) | 1989-03-24 | 1989-03-24 | Semiconductor device and mounting method using the same and continuity testing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1070643A JPH02249981A (en) | 1989-03-24 | 1989-03-24 | Semiconductor device and mounting method using the same and continuity testing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02249981A true JPH02249981A (en) | 1990-10-05 |
Family
ID=13437533
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1070643A Pending JPH02249981A (en) | 1989-03-24 | 1989-03-24 | Semiconductor device and mounting method using the same and continuity testing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02249981A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158563A (en) * | 1990-10-22 | 1992-06-01 | Matsushita Electric Ind Co Ltd | Integrated circuit device |
| US5717573A (en) * | 1994-08-05 | 1998-02-10 | International Business Machines Corporation | Interconnection card and methods for manufacturing and connecting the card |
| WO2022153902A1 (en) * | 2021-01-18 | 2022-07-21 | ローム株式会社 | Semiconductor device |
-
1989
- 1989-03-24 JP JP1070643A patent/JPH02249981A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04158563A (en) * | 1990-10-22 | 1992-06-01 | Matsushita Electric Ind Co Ltd | Integrated circuit device |
| US5717573A (en) * | 1994-08-05 | 1998-02-10 | International Business Machines Corporation | Interconnection card and methods for manufacturing and connecting the card |
| WO2022153902A1 (en) * | 2021-01-18 | 2022-07-21 | ローム株式会社 | Semiconductor device |
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