JPS63147354A - Package for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the title packages for semiconductor integrated circuit in the three dimensional directions to be connected to one another as well as to be mounted in high degree of integration by a method wherein through holes passing through the packages are made so that conductive pins may be arranged in the through holes to be protruded from both sides of the packages. CONSTITUTION:The title packages 1 for semiconductor integrated circuit is composed of a semiconductor element 3 diebonded onto a basic member 2; lead frames 5 connected to the semiconductor element 3 by wire bonding process through the intermediary of the semiconductor element 3 and wires 4; and a ceramic cap 6 sealing said basic member 2 while through holes passing through the package 1 are made. Then, conductive pins 7 are arranged in the through holes to be protruded from both sides of package 1. Furthermore, multiple said packages 1 are laminated by solder-bonding the conductive pins 7 protruded from both sides of package 1 to connect the semiconductor elements 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a package for a semiconductor integrated circuit characterized in that connection terminals such as leads are provided in both the upper and lower directions of the package for a semiconductor integrated circuit.

[Conventional technology]

Various types of conventional packages for semiconductor integrated circuits have already been put into practical use, but pancages for semiconductor integrated circuits were originally used to protect chips and knobs from the external environment and to allow chips to be handled. It would have been better if it fulfilled the basic functions such as The dual in-line package (DIP) shown in Figure 5 (a) accounts for more than 70% of all packages, and in addition to the above basic functions, standardization for mounting boards, automatic insertion machines, various testers, etc. has been completed. are doing.

In contrast, recently, semiconductor integrated circuits have become more highly integrated and faster, and in addition, due to the demand for electronic devices to be smaller and more functional, the density of packaging has been increasing. Due to these demands, there has been a strong demand for smaller size and higher density packaging for packages for semiconductor integrated circuits, and pancages such as those described below have been put into practical use. In the flat package shown in FIG. 5(b), the leads are exposed on the four sides of the package and surface-mounted on the printed circuit board, thereby satisfying both the functions of thin mounting and high-density wiring. The one-dress tinop carrier (LCC) shown in Figure 5 <c> is a flat pan cage with leads removed to achieve even smaller size and higher density packaging. , a conductor pattern is formed. A similar package is the plastic leaded chip carrier (PLCC) shown in Figure 5(d).This is a flat package with the ends of the leads bent, ensuring the same packaging density as the 12CC. Yes, since PLCC is made of plastic,
It is cheaper than ceramic LCCs, and many LSI manufacturers in the United States are beginning to adopt it. The pin grid array (PGA) shown in FIG. 5(e) has a matrix of pin terminals on the bottom of the package. The pin arrangement is 100 mil pitch, and it can be used by directly inserting it into a printed A board. this is,
This was developed to overcome the drawback that flat packages and LCCs have electrode terminals on the four sides of the chip, and as the number of terminals increases, the size becomes larger.

The above has described packages for semiconductor integrated circuits that are currently in practical use.The sealing methods for these pancages include the hermetic sealing method shown in Figure 4(a), and the hermetic sealing method shown in Figure 4(a).
It can be broadly divided into resin sealing methods as shown in b). Fourth
Figure (a) shows a type of hermetic sealing that is called ceramic sealing, in which a semiconductor element 52 die-bonded on a ceramic base 51 and a lead frame 53 are wire-bonded with a wire 54, and a ceramic cap 55 is lowered. Ceramic base 51 by melting point glass 56
The inside of the package is hermetically sealed with dry air 57. Furthermore, the resin sealing shown in FIG. 4(b) is performed by covering the semiconductor element 63 and wire 64 die-bonded onto the island 62 of the lead frame 61 with an epoxy resin 65. be.

[Problem that the invention seeks to solve]

The conventional packages for semiconductor integrated circuits described above were put into practical use due to the demand for miniaturization and high-density packaging, and the PGA shown in Figure 5(e) occupies the smallest area per number of pins. The size is decreasing in order of flat package, chip carrier, and DIP. However, the above-mentioned packages are used by being pushed into a printed circuit board or bonded to the surface of a printed circuit board, and are intended only for mounting on a flat surface, and are not suitable for three-dimensional connection. This has the problem of having to be carried out via a printed circuit board or the like. Therefore, 3
It has been difficult to achieve dimensional high-density packaging with conventional semiconductor integrated circuit packages.

The present invention solves the above problems, and aims to provide a package for semiconductor integrated circuits that enables connection of packages for semiconductor integrated circuits in three-dimensional directions and enables high-density packaging. do.

(Means for Solving the Problems) For this purpose, the semiconductor integrated circuit package of the present invention includes a semiconductor element that is die-bonded on a Go board, and a lead frame that is connected to the semiconductor element by wire bonding via wires. and a cap for sealing the base material, a through hole passing through the pan cage is provided, a conductive pin is disposed within the through hole, and the conductive pin is provided with a through hole penetrating the pan cage. It is characterized by protruding from both sides of the package, and furthermore, by soldering the conductive pins provided on both sides of a plurality of semiconductor integrated circuit packages, a plurality of such packages are stacked and the semiconductor elements are connected to each other. It is characterized by:

[Effect]

In the present invention, for example, as shown in FIG. 3, semiconductor integrated circuit packages 101 to 1 are mounted on a printed circuit board 100.
04 can be connected by soldering the respective pins 201 to 204, making it possible to three-dimensionally connect the pan cage for semiconductor integrated circuits.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows one of the semiconductor integrated circuit packages of the present invention.
FIG. 2 is a cross-sectional view showing an embodiment, FIG. 2 is a view for explaining the manufacturing process thereof, and FIG. 3 is a cross-sectional view showing an example of use of the semiconductor integrated circuit package of the present invention.

In FIG. 1, a package 1 for a semiconductor integrated circuit according to the present invention includes a ceramic base 2 forming a base material, a semiconductor element 3 die-bonded onto the base 2, and a wire 4 connected to the semiconductor element 3 via a wire 4. It is composed of a lead frame 5 connected by bonding, a ceramic cap 6 sealed to the lead frame 5, and a conductive pin 7 passing through the package. The semiconductor element 3 is sealed with a low boiling point glass 8 and the semiconductor element 3 is sealed with dry air 9.

Next, the manufacturing process of the semiconductor integrated circuit package of the present invention will be explained with reference to FIG. 2. First, as shown in FIG. 2(a), the ceramic base 2 and the lead frame 5 are
are provided with through holes 10.11 for penetrating the conductive pins 7 as shown in FIG. After forming the ceramic base 2 and the lead frame 5, the ceramic base 2 and the lead frame 5 are bonded together using a low boiling point glass 8 using a high temperature press method.

Next, as shown in FIG. 2(b), the semiconductor element 3 is die-bonded onto the ceramic base 2, and the semiconductor element 3 and the lead frame 5 are further wire-bonded with the wire 4. For the wire 4, an AU wire or an Aff wire is used, and a thermocompression bonding method, an ultrasonic bonding method, or the like is used.

Next, as shown in FIG. 2(C), the conductive pin 7 is vertically penetrated into the through hole 10.11, and the conductive pin 7 is connected to the ceramic base 2 and the lead frame 5 by soldering. 15 through holes 10 respectively
．． It is joined and fixed to 11.

Then, as shown in FIG. 2(d), the conductive pin 7 is passed through the through hole 14 provided in the ceramic cap 6, and the ceramic cap 6 and the lead frame 5 are heated at high temperature using a low boiling point glass 8. The conductive pin 7 and the ceramic cap 6 are joined by a pressure method, and the conductive pin 7 and the ceramic cap 6 are joined and fixed by a solder 15. The conductive pin 7 is used for three-dimensional connection as an external connection terminal.
A package 1 for a semiconductor integrated circuit capable of dimensional bonding is completed.

An example of the use of the pancage of the present invention will be explained with reference to FIG. 3. When connecting the semiconductor integrated circuit packages 101 to 104 onto the printed circuit board 100,
This can be done by soldering 01 to 204, which enables three-dimensional bonding of baffles for semiconductor integrated circuits, and similarly connects a large number of semiconductor elements to each other easily using the package.

It goes without saying that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made. For example, a conductive rubber sheet may be applied to the portion of the conductive pin 7 shown in FIG. 2(d) that protrudes from the package. moreover,
A metal cap may be used instead of the ceramic cassop 6. In that case, a metal base generally called a stem is used instead of the ceramic base.

In addition, the legs of the lead frame 5 shown in FIG. 5(d) may be extended in two directions on the left and right sides of the package side as in a DIP, or may be extended in four directions on the side of the package as in a flat package. Even for a pan cage such as an LCC, external connection terminals can be provided in the vertical direction of the buff cage. In this way, for any semiconductor integrated circuit pancage that is currently in practical use,
The present invention can be applied.

〔Effect of the invention〕

As explained above, according to the present invention, it is now possible to connect packages for semiconductor integrated circuits in a three-dimensional direction, which has been difficult in the past, and also in a three-dimensional direction without using a printed circuit board or the like as in the past. This has the advantage of allowing high-density packaging. Furthermore, it becomes easy to bond semiconductor integrated circuits together, and it becomes possible to easily increase the degree of integration of semiconductor elements.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing one embodiment of the package for semiconductor integrated circuit of the present invention, and FIGS. 2(a) to (d) are diagrams for explaining the manufacturing process of the package for semiconductor integrated circuit of the present invention. , FIG. 3 is a diagram for explaining an example of use of the semiconductor integrated circuit package of the present invention, FIGS. 4(a) and (b) are sectional views showing the sealing form of the semiconductor integrated circuit package,
FIG. 5 is a perspective view showing a conventional pancase for semiconductor integrated circuits, and FIG.
(b) is a diagram showing a flat package, and (C) is a diagram showing a leadless chip carrier (L
(d) is a diagram showing a plastic leaded chip carrier (PLCC), and (e) is a diagram showing a pin grid array (PGA). 1.101-104...Semiconductor integrated circuit package, 2.51...Ceramic base (base material), 3.52
．． 63...Semiconductor element, 4.54.64...Wire, 5.53.61...Lead frame, 6.55...
・Ceramic cap, 7.201-204... Conductive pin, 8156... Low boiling point glass, 9.57...
Dry air, 1O211, 14...Through hole, 12
．． 13...Solder plating layer, 15...Solder, 10
0...Printed circuit board, 62...Island on lead frame, 65...Epoxy resin. Applicant Dai Nippon Printing Co., Ltd. Representative Patent Attorney Hiroki Shirai (2 others) Figure 1 Figure 3 Figure 4

Claims (4)

[Claims] (1) A semiconductor element die-bonded onto a base material,
In a semiconductor integrated circuit package comprising a lead frame connected to the semiconductor element by wire bonding via wires and a cap sealing the base material, a through hole passing through the package is provided; A package for a semiconductor integrated circuit, characterized in that a conductive pin is disposed within a through hole, and the conductive pin protrudes from both sides of the package. (2) A package for a semiconductor integrated circuit according to claim 1, characterized in that conductive rubber is provided at the end of the conductive pin. (3) The package for a semiconductor integrated circuit according to claim 1, wherein high-density mounting in a three-dimensional direction is enabled by soldering the conductive pins to external terminals. (4) a semiconductor element die-bonded onto a base material;
A semiconductor integrated circuit package comprising a lead frame connected to the semiconductor element by wire bonding via wires and a ceramic cap sealing the base material, a through hole penetrating the package being provided, A conductive pin is arranged in the through hole, the conductive pin is made to protrude from both sides of the package, and the plurality of semiconductor integrated circuit packages are soldered together between the conductive pins provided on both sides of the package. A package for a semiconductor integrated circuit, characterized in that the packages are stacked and semiconductor elements are connected to each other.