JPH0945715A - Multichip package in which internal lead is directly electrically connected to bonding pad of substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid an exfoliation phenomenon between a lead frame pad and mlod resin and to reduce the size of a package and the number of times of processing sharply, by electrically connecting internal leads and the bonding pads of a board directly. SOLUTION: This multichip package comprises a board 110 provided with upper surface bonding pads 114, a plurality of chips 130, 140 mounted on the upper surface of the board 110, internal leads 150 arranged in line corresponding to each of the bonding pads 114 of the board, and bumps 116 for electrically connecting the internal lends 150 to the bonding pads 114 of the board. And the board 110 is mechanically supported by the internal leads 150, and the bonding pads 114 of the board are electrically connected directly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip package, and more particularly, to mechanically and electrically connecting internal leads and a bonding pad of a substrate without using a lead frame pad and a lead frame. To solve the problem of interfacial peeling between the pad and molding resin,
The present invention relates to a multi-chip package having no lead frame pad.

[0002]

2. Description of the Related Art At present, chip manufacturing technology focuses on manufacturing highly integrated and large capacity chips, but the chip interconnection speed and I / O speed are still satisfactory. It has not reached the standard.

As a result, chip interconnect speed has become an important factor in improving the operating speed and performance of semiconductor devices. In addition, packaging of semiconductor chips is also a very important factor in terms of performance of semiconductor devices.

Improvements in the performance of semiconductor devices are more severely limited by the packaging and interconnection technology of the chips, rather than by the technology of the chips themselves. In order to overcome such a limitation, a multi-chip package has been proposed. In the future, multi-chip packages are expected to be introduced into many semiconductor devices in order to cope with the trend toward higher performance of semiconductor devices.

FIG. 3 is a sectional view of a conventional multi-chip package. Referring to FIG. 3, in a conventional multi-chip package 100, a plurality of chips, for example, two chips 30 and 40 are mounted on an upper surface of a printed circuit board 10 (hereinafter abbreviated as a board), and a lead frame pad 20. Is attached to the lower surface of the substrate 10 by a conductive epoxy adhesive (not shown), and the chip 40 is attached to the upper surface of the substrate 10 by a non-conductive epoxy adhesive (not shown). belongs to. The plurality of bonding pads (not shown) provided on the upper surface of the chip 40 are electrically connected to the corresponding electrical connection terminals (not shown) provided on the upper surface of the substrate 10, respectively. The chip 40 and the substrate 10 are electrically connected. In addition, the other flip chip 30 is the substrate 10
Is electrically connected to an Au pad or a Pb pad (not shown) provided on the upper surface of the.

Further, the electrical connection terminals (not shown) are electrically connected to the corresponding bonding pads (not shown) of the substrate 10 through the wiring (not shown), and The Au pad or Pb pad is also electrically connected to the corresponding bonding pad of each of the substrates 10 via a wiring (not shown). Further, the substrate bonding pads are electrically coupled to their respective internal leads 50 via wires 70. In addition, the package 100 includes the internal leads 50, the chips 30, and 4.
0, the substrate 10, and the lead frame pad 20 are sealed with the molding resin 80 to protect them from the external environment.

[0007]

The conventional multi-chip package has the following drawbacks.

In a harsh environment of thermal inspection such as long-term temperature cycling, a peeling phenomenon occurs at the interface between the molding resin and the lead frame pad due to the difference in coefficient of thermal expansion between them. Therefore, in the manufacturing process, cracks may occur in the molding resin after the soldering process.

In a multi-chip package for mounting a large chip, the number of ILB (inner lead bonding) steps increases, resulting in a decrease in work productivity.

In view of the above, an object of the present invention is to solve the problem of the peeling phenomenon between the lead frame pad and the molding resin by directly electrically connecting the internal lead to the bonding pad of the substrate, and to package the package. An object of the present invention is to provide a multi-chip package that can significantly reduce the size and the number of ILB processes.

[0011]

In order to achieve such an object, a multi-chip package of the present invention includes a substrate having a bonding pad on the upper surface thereof, a plurality of chips mounted on the upper surface of the substrate, and a substrate. An internal lead aligned corresponding to each of the bonding pads and a bump electrically connecting the internal lead to the bonding pad of the substrate are provided, and the substrate is mechanically supported by the internal lead. The bonding pad of the substrate is directly electrically connected.

The bumps are preferably made of Au or Cu. A solder layer may be further provided on the upper surface of the bump, and a UBM (under bump m) may be further provided on the lower surface.
etallurgy) layer may be provided. In addition, it is preferable that a plating film with good wetting is provided on the internal lead at a portion electrically connected to the bonding pad of the substrate.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in more detail with reference to the drawings.

FIG. 1 is a perspective view of a multi-chip package in which the internal leads and the bonding pads of the substrate are directly electrically connected according to the present invention. FIG. 2 is a cross-sectional view of FIG.
It is sectional drawing of the A line.

Referring to FIGS. 1 and 2, in the multi-chip package 200 according to the present invention, the bonding pads 114 of the substrate provided on the upper surface of the substrate 110 and the respective inner leads 150 corresponding thereto are directly electrically connected. 3 of the multi-chip package 1 of FIG.
It has the same structure as 00.

The detailed structure of electrical connection between the bonding pad 114 of the substrate and the internal lead 150 is as follows. On the upper surface of the substrate 110, the bonding pads 114 and the UBM (under bump meta) of the substrate are sequentially arranged from the bottom.
llurgy) layer 115, a refractory metal layer 116 functioning as a bump, a solder layer 117, and an internal lead 150 are laminated. A passivation layer 113 is provided on the upper surface of the substrate 110 so as to surround the bonding pads 114 and the UBM layer 115 on the substrate. Internal lead 1
In addition, a portion of the board 50 electrically connected to the bonding pad 114 of the substrate has a wetting materia.
A metal plating film (not shown) that functions as l) may be provided. The refractory metal layer 116 is made of Au or Pb.
Can be configured more.

Such a structure is made by disposing a heater block (not shown) on the upper surface of the inner lead 150 and electrically connecting the respective materials for a predetermined time, temperature and pressure. This allows mechanical bonding between the substrate 110 and the internal leads 150.

[0018]

Therefore, the structure of the present invention has the following advantages.

First, internal leads can be attached to the bonding pads of the substrate without the use of lead frame pads. Therefore, the problem of peeling between the molding resin and the lead frame pad during the molding process of the package can be avoided.

Secondly, in a multi-chip package for mounting a large chip, since all the internal leads are bonded at the same time as the corresponding bonding pads of the substrate, the number of ILB processes is greatly reduced.

[Brief description of drawings]

FIG. 1 is a perspective view of a multi-chip package in which internal leads and bonding pads of a substrate are directly electrically connected according to the present invention.

FIG. 2 is a cross-sectional view taken along the line AA of FIG.

FIG. 3 is a sectional view of a conventional multi-chip package.

[Explanation of symbols]

 110 substrate 112 electrical connection terminal 113 passivation layer 114 substrate bonding pad 115 UBM (Under Bump Metallurgy) layer 116 refractory metal layer 117 solder layer 130 flip chip 132 bump 140 chip 142 142 bonding pad 150 internal lead 160 wire 200 multi Chip package

Claims (5)

[Claims] 1. A substrate having an upper surface provided with a bonding pad, and a plurality of chips mounted on the upper surface of the substrate,
An internal lead aligned corresponding to each of the bonding pads of the substrate and a bump electrically connecting the internal lead to the bonding pad of the substrate are provided, and the substrate is mechanically supported by the internal lead. The multi-chip package, wherein the internal lead and the bonding pad of the substrate are directly electrically connected. 2. The multi-chip package according to claim 1, wherein the bump is made of Au or Cu. 3. The multi-chip package according to claim 1, wherein a solder layer is laminated on an upper surface of the bump. 4. A UBM (under bump) is formed on the lower surface of the bump.
metallurgy) layer is provided,
The multi-chip package according to claim 3. 5. The plating film having good wetting is provided on a portion of the internal lead, which is electrically connected to the bonding pad of the substrate, according to claim 1 or 3. The described multi-chip package.