JPS63177053U - - Google Patents
Info
- Publication number
- JPS63177053U JPS63177053U JP1987066302U JP6630287U JPS63177053U JP S63177053 U JPS63177053 U JP S63177053U JP 1987066302 U JP1987066302 U JP 1987066302U JP 6630287 U JP6630287 U JP 6630287U JP S63177053 U JPS63177053 U JP S63177053U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- functional unit
- circuit device
- unit block
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 5
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987066302U JPS63177053U (enrdf_load_html_response) | 1987-05-01 | 1987-05-01 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987066302U JPS63177053U (enrdf_load_html_response) | 1987-05-01 | 1987-05-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63177053U true JPS63177053U (enrdf_load_html_response) | 1988-11-16 |
Family
ID=30904183
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987066302U Pending JPS63177053U (enrdf_load_html_response) | 1987-05-01 | 1987-05-01 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63177053U (enrdf_load_html_response) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998038680A1 (fr) * | 1997-02-28 | 1998-09-03 | T.I.F. Co., Ltd. | Module memoire |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61294833A (ja) * | 1985-06-21 | 1986-12-25 | Nec Corp | 半導体集積回路 |
-
1987
- 1987-05-01 JP JP1987066302U patent/JPS63177053U/ja active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61294833A (ja) * | 1985-06-21 | 1986-12-25 | Nec Corp | 半導体集積回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1998038680A1 (fr) * | 1997-02-28 | 1998-09-03 | T.I.F. Co., Ltd. | Module memoire |