WO1998038680A1 - Module memoire - Google Patents

Module memoire Download PDF

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Publication number
WO1998038680A1
WO1998038680A1 PCT/JP1998/000717 JP9800717W WO9838680A1 WO 1998038680 A1 WO1998038680 A1 WO 1998038680A1 JP 9800717 W JP9800717 W JP 9800717W WO 9838680 A1 WO9838680 A1 WO 9838680A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
module
pads
chip
substrate
Prior art date
Application number
PCT/JP1998/000717
Other languages
English (en)
Japanese (ja)
Inventor
Kouichi Ikeda
Original Assignee
T.I.F. Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by T.I.F. Co., Ltd. filed Critical T.I.F. Co., Ltd.
Publication of WO1998038680A1 publication Critical patent/WO1998038680A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Definitions

  • the present invention relates to a memory module that can be mounted on a memory board, a motherboard, or the like.
  • a memory bare chip or a processor bare chip cut out of a semiconductor wafer is mounted on a printed circuit board or the like in a packaged state.
  • the external dimensions of the package are considerably larger than the size of the various bare chips themselves, so there are certain limitations on the number of memory packages and cages that can be mounted on a printed circuit board or the like.
  • MCM multi-chip module
  • a multi-chip module in which a plurality of bare chips are mounted on a substrate having almost the same size as a packaging substrate is becoming popular.
  • the use of this multi-chip module makes it possible to (1) reduce the size and weight of the mounting area, (2) improve the performance and speed of high-density wiring and bare chip mounting, and (3) ensure high reliability.
  • the present invention has been made in view of the above points, and its purpose is to It is an object of the present invention to provide a memory module that can simplify wiring in a rule substrate.
  • the memory modules of the present invention are arranged adjacent to each other in units of two even-numbered memory chips having the same structure.
  • a part of control signals such as a chip select signal and a write enable signal and a part or all of data or an address are often connected in common.
  • wiring routing and the like can be reduced, and wiring in the module substrate can be simplified.
  • the above-described arrangement of the memory chips is suitable for a DRAM memory chip in which a plurality of chip pads are arranged in a row. That is, in this case, the pads of the same type and in the same order are arranged in parallel, so that the pads of the same type can be easily connected, and the wiring in the module substrate is reduced. It doesn't get complicated.
  • the chip pads are connected to each other. Since only the wiring and the common board pad between them are required to be connected, the connection by the wiring pattern in the module board can be reduced. When this connection is performed using a bonding wire, the bonding wire between the chip pad and the substrate pad does not intersect with another bonding wire. be able to.
  • FIG. 1 is a plan view schematically showing a memory module of the present embodiment
  • FIG. 2 is a sectional view taken along the line A—A ′ in FIG. 1,
  • FIG. 3 is a diagram showing the arrangement direction of each memory bay chip on the module substrate
  • FIG. 4 is a perspective view showing a part of the memory module
  • FIG. 5 is a circuit diagram of the memory module
  • FIG. 6 is a diagram showing the pattern layout of the module board
  • FIG. 7 is a view showing a state in which the memory module is mounted on an SODIMMM board.
  • FIG. 8 is a view showing a module board in the case where a bare chip for memory is mounted on a flip chip.
  • FIG. 9 is a plan view of a memory module showing an example in which bonding wires are alternately drawn.
  • FIG. 1 is a plan view schematically showing a memory module of the present embodiment
  • FIG. 2 is a sectional view taken along line AA ′ of FIG.
  • a memory module 10 has four memory base chips 1 of the same structure, which are individually cut out from a semiconductor wafer, placed on a rectangular module substrate 2 by a C 0 B (chip). On Board) This is implemented.
  • Each memory base chip 1 is a DRAM having a memory capacity of, for example, 4 M ⁇ 4 bits.Each of the memory bare chips 1 has a rectangular shape, and a plurality of packages are arranged in a line in the center along the long side. C3 is formed.
  • the module board 2 has an external dimension that can be mounted on a SO—DIMM (Single Outline Dual Inline Memory Module) board, which will be described later.
  • a plurality of pads 4 are formed substantially in a row. Two memory bay chips 1 are mounted on both sides of the pad 4, and the direction in which the pads 4 of the module board 2 are arranged is almost parallel to the direction in which the pads 3 of each memory bay chip 1 are arranged. It has become.
  • a plurality of pads 4 are formed on the module substrate 2 between two memory bare chips 1 arranged such that their long sides are adjacent to each other and in parallel with their respective pads 3. ing.
  • the pad 3 described above corresponds to a chip pad, and the pad 4 corresponds to a board pad.
  • the pad 4 of the module board 2 and the pad 3 of the memory bare chip 1 are connected by bonding wires 5.
  • the nodes 4 include one in which two bonding wires 5 are connected and one in which one bonding wire 5 is connected.
  • Bare chips for memory 1 For terminals commonly connected to a plurality of memory bare chips 1 such as address terminals of the memory, by connecting a plurality of bonding wires 5 to a pad 4 on the module board 2, the pad is connected. 4 is being shared.
  • the total number of the pads 4 can be smaller than the total number of the pads 3 of the entire memory bare chip 1.
  • the two bonding wires 5 can be connected to each other at the same time through the common pad 4. The amount of wiring can be reduced. For example, when the module substrate 2 is configured using a multilayer substrate, the number of layers of the substrate can be reduced, and the cost of the memory module 10 can be reduced.
  • the memory bare chips 1 are arranged such that the pads 3 of the memory bare chips 1 are arranged in two rows in parallel with the longitudinal direction of the module substrate 2, and furthermore, the pads 4 of the module substrate 2 are sandwiched therebetween.
  • the bonding wire 5 from each memory bare chip 1 is connected to the common pad 4 of the module board 2. Then, a plurality of bonding wires 5 are connected to the common pad 4 at the shortest distance.
  • the corresponding pads 3 of the two memory bare chips 1 are connected to each other, it is only necessary to connect the common pads 4 of the module substrate 2 with the bonding wires 5. There is no need to perform wiring using different wiring layers within the module, and wiring within the module substrate 2 can be simplified.
  • the corresponding identical pads 3 are shared by the common package of the module substrate 2. ⁇ Even if you try to connect to the board 4, you cannot connect directly because the wire bonding 5 crosses each other. For example, it will once pass through another wiring layer in the module board 2, Wiring becomes complicated.
  • each pad 4 on the module substrate 2 is concentrated between the two bare memory chips 1 arranged so that the long sides are adjacent to each other, each pad 4 is located outside the corresponding bare memory chip 1.
  • Pad 4 occupies compared to forming pad 4 separately The area can be reduced, and the memory module 10 can be reduced in size and mounted with high density.
  • FIG. 3 is a diagram showing the arrangement direction of each memory bare chip 1 on the module substrate 2.
  • four memory bare chips 1 arranged with a plurality of pads 4 on a module substrate 2 interposed therebetween are arranged in such a manner that all of them are oriented in the same direction.
  • at least two memory bare chips 1 adjacent to each other with the pad 4 interposed therebetween may be arranged in the same direction.
  • the resin 10 covers the upper surface of the wire-bonded memory bare chip 1 with a resin 6 to prevent disconnection or the like. If the resin 6 is formed thick, the height of the memory module 10 becomes too high.
  • a sealing frame 7 having a predetermined height is attached near the outer periphery of the module substrate 2, and the resin 6 is poured into the sealing frame 7.
  • the thickness of the resin is set to match the height of the sealing frame 7.
  • FIG. 4 is a perspective view showing a part of the memory module 10 shown in FIG.
  • external connection terminals 8 formed in a concave shape are provided on the outer surface of the module substrate 2, and these external connection terminals 8 are wirings formed on the surface or inside the module substrate 2. It is electrically connected to the pads 4 on the surface of the module substrate 2 via the pattern 9.
  • solder by pouring solder into the recesses of these external connection terminals 8, electrical connection with the main board and the like, as well as mechanical fixing, are performed.
  • the memory module 10 of the present embodiment is obtained by cutting out the memory bare chip 1 formed on the semiconductor wafer and mounting it on the module substrate 2 without packaging. (For example, 4) memory bare chips 1 can be mounted without difficulty.
  • FIG. 5 shows a memory device constructed using four memory chips 1 having the same structure.
  • FIG. 3 is a circuit diagram of the memory module 10. In this figure, some terminals such as a power supply terminal and a ground terminal are omitted for simplification. As shown in the figure, some of the terminals of each memory chip 1 are connected in common to all the memory bare chips 1. More specifically, the address terminals A0 to A11 of each memory bare chip are commonly connected to the external connection terminals ADRO to ADR11, respectively, the control terminal RAS is connected to the external connection terminal RE, and the control terminal WE is connected to the external connection terminal WE. In addition, the control terminal OE is commonly connected to the external connection terminal OE.
  • the data terminals I / O0 to 1/03 are separately connected to the external connection terminals DO to D15, respectively.
  • the control terminal CAS is connected to the external connection terminals CE 0 and CE 1 as a set of two memory bare chips 1.
  • FIG. 6 is a diagram showing a pattern layout of the module substrate 2, wherein the hatched portions in the drawing show the wiring patterns, and the dotted lines in the drawing show the mounting positions of the memory bare chips 1.
  • the module board 2 is composed of, for example, a four-layer printed wiring board.
  • Pads 4 are formed substantially in a line in the longitudinal direction at the center of the uppermost layer, and solid pads for grounding are provided on both sides of the pads 4.
  • Pattern 21 is formed.
  • the ground solid pattern 21 is also formed on the lowermost layer.
  • a wiring pattern 22 is connected to each pad 4, and the other ends of these wiring patterns 22 are connected to through holes 23 except for a part.
  • the through-hole 23 is connected to an inner layer pattern or a lowermost layer pattern, and the patterns of these layers are respectively connected to the external connection terminals 8.
  • a plurality of corresponding pads are connected to each other by a wiring pattern 22.
  • the number of the external connection terminals 8 can be reduced because one external connection terminal 8 is shared in correspondence with the pads 3 of the plurality of memory base chips 1. Is not much different from the total number of pads 3 for one bare chip for memory.
  • the memory module 10 of the present embodiment has a plurality of memory bare chips 1 mounted on the module substrate 2 by COB, and wiring between the memory bare chips 1 is performed by an SO-DIMM substrate or the like instead of the module.
  • the module base The amount of wiring of the S0—DIMM board or the like can be much smaller than that of mounting the memory bare chip 1 mounted on the board 2 individually on the main board.
  • the memory module 10 as a multi-chip module can have a smaller mounting area than mounting the packaged memory chips individually, reducing the wiring length and reducing the effects of wiring delay and noise. You can do it.
  • FIG. 7 is a plan view showing an example in which the memory module 10 of the present embodiment is mounted on the SO-DIMM board 11, and FIG. 7 (a) shows one of the SO-DIMM boards 11.
  • Figure 7 (b) shows the other side.
  • a controller 13 for checking the bare chip 1 for each memory is mounted on one surface.
  • Each memory module 10 is mounted by the above-described LCC method, and the bypass capacitor 12 and the controller 13 are mounted by the SMT (Surface Mount Technology) method.
  • SMT Surface Mount Technology
  • the SO-DIMM board shown in Fig. 7 has the same result as mounting a total of 16 memory ICs with 8 on each side.
  • the memory bare chip 1 that constitutes the memory module 10 has 4 MX each.
  • the memory capacity of each memory module 10 is 8 Mbytes
  • the total memory capacity of the SO-DIMM is 32 Mbytes.
  • FIG. 4 is a diagram showing a module substrate when a bare chip for memory is mounted on a flip chip.
  • the dotted line part shown in FIG. 8 indicates the mounting position of the memory base chip 1.
  • the bonding wire 5 is drawn almost symmetrically from the two memory bare chips 1 arranged on both sides of the pad on the module board 2 as shown in FIG.
  • the bonding wire 5 may be alternately drawn out from the memory bare chips 1 on both sides.
  • the number of the memory bare chips 1 mounted on the memory module 10 is as follows.
  • the number is not limited to four and is not particularly limited as long as it is two or more.
  • the failure rate of the memory module 10 may increase. Therefore, the type of memory chip 1 to be implemented (for example, the number of bits and the memory capacity) is taken into consideration, and the number of memory modules 10 to be implemented is determined based on the number of memory modules 10 to be manufactured. It is desirable to determine the number of tips 1. Since ordinary computer equipment often manages the memory capacity in multiples of four, it is desirable that the number of memory base chips 1 mounted on the module substrate be even.
  • a memory module when configured as a multi-chip module, by arranging adjacent memory chips having the same structure in units of two even-numbered memory chips, When inputting and outputting the same type of signals and data to and from each memory module, the number of wirings in the module substrate is reduced, and the wirings can be simplified.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)

Abstract

Module mémoire dont le câblage de la carte de module peut être simplifié. Ledit module possède une carte (2) sur laquelle sont montées quatre puces (1) nues de mémoire ayant la même structure. Chaque puce (1) de mémoire est dotée de plots de connexion (3) placés sur une ligne dans le sens longitudinal. Au centre de la carte (2) de module, des plots de connexion (4) sont placés sur une ligne dans le sens longitudinal. Les puces (1) nues sont situées des deux côtés de la ligne sur laquelle se trouvent les plots de connexion (4) de la carte (2), deux puces étant placées de chaque côté et dans le même sens. Grâce à cette configuration des puces nues, les plots de connexion (3) des deux côtés de la carte (2) sont disposés dans le même ordre et les plots de connexion du même ordre sont disposés adjacents les uns aux autres. Par conséquent, pour connecter électriquement les plots (3) de même type, il est simplement nécessaire de connecter les plots (3) au plot commun (4) sur la carte (2) de module à l'aide de fils (5) de connexion.
PCT/JP1998/000717 1997-02-28 1998-02-23 Module memoire WO1998038680A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6184197 1997-02-28
JP9/61841 1997-02-28

Publications (1)

Publication Number Publication Date
WO1998038680A1 true WO1998038680A1 (fr) 1998-09-03

Family

ID=13182728

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/000717 WO1998038680A1 (fr) 1997-02-28 1998-02-23 Module memoire

Country Status (1)

Country Link
WO (1) WO1998038680A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014078760A (ja) * 2014-02-03 2014-05-01 Fujitsu Ltd マルチチップモジュール

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177053U (fr) * 1987-05-01 1988-11-16
JPH01235264A (ja) * 1988-03-15 1989-09-20 Toshiba Corp 半導体集積回路装置
JPH047867A (ja) * 1990-04-26 1992-01-13 Hitachi Ltd 半導体装置及びその製造方法
JPH05291348A (ja) * 1992-04-10 1993-11-05 Nippon Steel Corp 半導体パッケージ
JPH06140535A (ja) * 1992-10-27 1994-05-20 Mitsubishi Electric Corp テープキャリアパッケージ型半導体装置
JPH0786537A (ja) * 1993-09-16 1995-03-31 Kawasaki Steel Corp 半導体装置およびその製造方法
JPH09134928A (ja) * 1995-10-28 1997-05-20 Samsung Electron Co Ltd ウェーハから一度に切断された半導体チップグループを用いた高密度実装型パッケージ及びその製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63177053U (fr) * 1987-05-01 1988-11-16
JPH01235264A (ja) * 1988-03-15 1989-09-20 Toshiba Corp 半導体集積回路装置
JPH047867A (ja) * 1990-04-26 1992-01-13 Hitachi Ltd 半導体装置及びその製造方法
JPH05291348A (ja) * 1992-04-10 1993-11-05 Nippon Steel Corp 半導体パッケージ
JPH06140535A (ja) * 1992-10-27 1994-05-20 Mitsubishi Electric Corp テープキャリアパッケージ型半導体装置
JPH0786537A (ja) * 1993-09-16 1995-03-31 Kawasaki Steel Corp 半導体装置およびその製造方法
JPH09134928A (ja) * 1995-10-28 1997-05-20 Samsung Electron Co Ltd ウェーハから一度に切断された半導体チップグループを用いた高密度実装型パッケージ及びその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014078760A (ja) * 2014-02-03 2014-05-01 Fujitsu Ltd マルチチップモジュール

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