JPS6317564B2 - - Google Patents

Info

Publication number
JPS6317564B2
JPS6317564B2 JP24920684A JP24920684A JPS6317564B2 JP S6317564 B2 JPS6317564 B2 JP S6317564B2 JP 24920684 A JP24920684 A JP 24920684A JP 24920684 A JP24920684 A JP 24920684A JP S6317564 B2 JPS6317564 B2 JP S6317564B2
Authority
JP
Japan
Prior art keywords
hole
mark
marks
inner layer
printed wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP24920684A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61125715A (ja
Inventor
Shinji Okamoto
Toshinori Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP24920684A priority Critical patent/JPS61125715A/ja
Publication of JPS61125715A publication Critical patent/JPS61125715A/ja
Publication of JPS6317564B2 publication Critical patent/JPS6317564B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/0061—Tools for holding the circuit boards during processing; handling transport of printed circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Machine Tool Sensing Apparatuses (AREA)
  • Drilling And Boring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP24920684A 1984-11-26 1984-11-26 多層印刷配線板の孔マ−ク位置検出法 Granted JPS61125715A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24920684A JPS61125715A (ja) 1984-11-26 1984-11-26 多層印刷配線板の孔マ−ク位置検出法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24920684A JPS61125715A (ja) 1984-11-26 1984-11-26 多層印刷配線板の孔マ−ク位置検出法

Publications (2)

Publication Number Publication Date
JPS61125715A JPS61125715A (ja) 1986-06-13
JPS6317564B2 true JPS6317564B2 (enrdf_load_stackoverflow) 1988-04-14

Family

ID=17189490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24920684A Granted JPS61125715A (ja) 1984-11-26 1984-11-26 多層印刷配線板の孔マ−ク位置検出法

Country Status (1)

Country Link
JP (1) JPS61125715A (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274806A (ja) * 1985-05-31 1986-12-05 Japan Steel Works Ltd:The プリント基板の基準穴加工装置
US4899440A (en) * 1986-12-31 1990-02-13 Systems Analysis And Integration Method and apparatus for locating targets on a panel and performing work operations thereon
JP2777425B2 (ja) * 1989-10-12 1998-07-16 日本ミクロン株式会社 多段ボンディング端子構造のピングリッドアレーの製造方法，その内層端子の削り出し装置及びピングリッドアレー用多層基板
WO1998022252A1 (fr) * 1996-11-20 1998-05-28 Ibiden Co., Ltd. Appareil d'usinage laser, et procede et dispositif de fabrication d'une carte imprimee multicouche
US7732732B2 (en) 1996-11-20 2010-06-08 Ibiden Co., Ltd. Laser machining apparatus, and apparatus and method for manufacturing a multilayered printed wiring board
US6056008A (en) * 1997-09-22 2000-05-02 Fisher Controls International, Inc. Intelligent pressure regulator
US6367678B1 (en) * 2000-04-18 2002-04-09 Ballado Investments Inc. Process for stacking layers that form a multilayer printed circuit

Also Published As

Publication number Publication date
JPS61125715A (ja) 1986-06-13

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