JPS63173148A - Memory pariry generating/monotoring circuit - Google Patents

Abstract

PURPOSE:To generate and manage program transfer and DMA transfer, by providing a bidirectional buffer operated by receiving a data control signal and a bidirectional buffer operated by receiving a parity control signal. CONSTITUTION:A CPU1 outputs an address signal S4, an I/O input signal S2, and the data control signal S13, and inputs a data signal S3 from an I/O3 by switching the direction of the bidirectional buffer 16. Next, the CPU outputs the signal S4, a MEM output signal S5, the signal S13, and the parity control signal S14, and writes the signal S3 on a MEM4 by switching the directions of the bidirectional buffers 11 and 17, anc writes a parity signal S7 generated at a PTYGEN/CHK6 on a MEM (PTY) 5. The CPU1 outputs the signal S4, a MEM input signal S6, the signal S13, and the signal S14, and reads the data from the MEM4, and parity from the MEM5 by switching the directions of the buffers 16 and 17, anc checks a data and parity rule at the leading edge of the signal S6 by the PTY6, and outputs a parity error signal if contraction is generated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory parity generation/monitoring circuit, and more particularly to a memory parity generation/monitoring circuit that generates/monitors both program transfers and direct memory access transfers. .

[Conventional technology]

Generally, when writing data to memory, a memory parity generation/monitoring circuit generates parity from the data and writes it to parity memory, and when reading data from memory, it compares the data with the read parity and uses the parity rule. An alarm is generated when the

To generate and monitor memory parity, a central processing circuit uses program transfer to transfer data, and a direct memory access controller (hereinafter referred to as DMAC) that can perform high-speed data transfer without using a central processing circuit. Direct memory access transfer (hereinafter referred to as OM
(referred to as A transfer). FIG. 3 is a block diagram showing a conventional memory parity generation/monitoring circuit. In the same figure, 1st DATA terminal Ia, ADDR terminal 1b, 4th
As shown in Figure (h), AENI terminal 1c and Mw terminal 1 output low level path control signal S8 during DMA transfer.
d, central processing circuit (hereinafter referred to as CPU) equipped with MR terminal 1e, IW terminal 1f and IR terminal 1g, 2 is ADD
R terminal 2&, AEN outputs a low-level bus control signal 810 during program transfer as shown in FIG. 4 (1).
2 terminal 2b, MW terminal 2c, MR terminal '2d,
The I10 human power signal S8 shown in FIG. 4(d) is input to the IW end! R terminal 3b and data signal S8 shown in Fig. 4)
Peripheral circuit (hereinafter referred to as I) equipped with DATA terminal 3C input by
10), 4 is the address signal S shown in FIG.
The ADDR terminal 4a to which 4 is input, the MR terminal 4 to which the MEM output signal S shown in FIG. 4(,) is input, and the MR terminal 4 to which the MEM input signal S6 shown in FIG.
Memory (hereinafter referred to as MIJ) equipped with C and DATA terminals 4d
), 5 is the ADDR terminal 5a, MW terminal 5b, Ma
The terminal 5c and the parity signal S shown in FIG. 4(c).

A parity memory (hereinafter referred to as HEM (PTY)) is provided with a DATA terminal 5d for input, and 6 is an input terminal 5m.

A memory parity generation/monitoring circuit (hereinafter referred to as PTYGEN/CHK) comprising an input/output terminal 6b and an output terminal 6c; 7 is a memory parity generating/monitoring circuit comprising an input terminal 7m, an input/output terminal 7b and an output terminal 7c, and performs the operations described above. A generation/monitoring circuit (hereinafter referred to as PTY (JN/C), 8 is shown in Fig. 4, 6) is provided with an output valid OE terminal 8m, an input terminal 8b, and an output terminal 8c to which the path control signal S8 shown in Fig. 4 is input. Bus control signal S8 input to OE terminal 8a
9 is an output valid terminal OE terminal 9a to which the path control signal S8 shown in FIG. 4(h) K is input; and 9 is the data control signal shown in FIG. 4(j). S.

has a T terminal 9b, an input terminal 9c, and an input/output terminal 9d, and when the bus control signal S8 input to the output valid OK terminal 9a is low level, the output is valid and the data control input to the an,'r terminal 9b. A bidirectional buffer 10 from which data is outputted to the following system bus when the signal S (see FIG. 4(1)) is at a high level is shown in FIG. 4(h).
An output valid OE terminal t to which the path control signal s8 shown in is input.
oa, T terminal 10b.

It has an input terminal 10e and an input/output terminal 10d, and the output is valid when the path control signal s8 input to the output valid OE terminal 10m is low level, and the data is valid when the signal input to the T terminal 10b is high level. The bidirectional buffer 11 outputs to the system bus shown below is shown in Fig. 4(i).
It includes an output valid OE terminal 11a, an input terminal 11b, and an output terminal 11c to which a path control signal 810 shown in is input,
A path control signal S□ is input to the output valid OE terminal 11a.

When the signal input to the 'r terminal 11b is at a high level, the output is valid and is 1, and when the signal is at a high level, the data is output to the system bus shown below.12 is a one-way buffer.
Bus control signal S□ shown in Figure (1). The output valid OE' terminal 12a is inputted, the T terminal 12b and the input/output terminal 11c are inputted with the data control signal 811 shown in Fig. 4←).
and a bus control signal S□ input to the output valid OE terminal 12&. A bidirectional buffer 1 whose output is enabled when T is at a low level, and data is output to the following system bus when a signal input to the T terminal 12b is at a high level.
3 is a bus control signal S□ shown in FIG. 4 (1). The output valid OE terminal 134. T terminal 13b, input terminal 1
3c and an input/output terminal 13d, the output is valid when the bus control signal S0° input to the output valid OE terminal 13& is low level, and the data is valid when the signal input to the T terminal 1'3b is high level. are bidirectional buffers that are output to the following system buses, 14 is a system bus, 15
15b is an AND gate that outputs the parity error signal ALL shown in FIG. 4(A), and 15c is a fourth
This is an AND gate that outputs the data control signal 811 shown in Figure 3).

Next, the operation of the memory parity generation/monitoring circuit having the above configuration will be explained with reference to FIGS. 4(a) to 4(4). First, parity generation during program transfer will be explained. In the case of this program transfer, the control right of the system bus is held by the CPU, and the path control signal S8 shown in Fig. 4 (color) is output from the AENI terminal 1C.
is enabled at low level. Therefore, C
PU1 receives the address signal S2. as shown in FIG. 4(-). I10 input signal S2. shown in FIG. 4(d). The data control signal S shown in FIG. 4(j) is output, the direction of the bidirectional buffer 9 is switched, and the data signal S8 shown in FIG. 4(b) is inputted from Ilo 3.

Next, the CPUI sends the address signal S shown in FIG. 4(a),
.

The MEM output signals S and l shown in Fig. 4(,) are as shown in Fig. 4(,).
j), and switches the direction of the bidirectional buffer 9 and the bidirectional buffer 10 to
4, write the data signal S3 shown in FIG. 4(b),
MEM (PTY) 5 has PTYGEN/CHK 6
K! The generated parity signal S shown in FIG. 4(C) is converted to W1! It's crowded. Next, to explain the monitoring, C.
PUI is the address signal S4. shown in FIG. 4(a). Outputting the MEM input signals S and l shown in FIG. 4(f)K, l data control signal S9 shown in FIG. The parity was read from field M (PTY) 5, and the parity rule of the data and parity was checked by PTYGEN/CHK 6 at the rising edge of the MEM input signal S shown in Fig. 4 (f>), and an unreasonableness occurred. When the low level parity error signal 5L11 is output,
When no unreasonableness occurs, the parity error signal S1. is at a high level. Then Φ)
Parity generation during DMA transfer will be explained.

First, in the case of DMA transfer, the system path is controlled by DMA.
C2 has a bus control signal S shown in FIG. 4 (1). is enabled when it is low level. And DM
AC2 is the address signal S4 shown in Figure 4 (-), the VO input signal S shown in Figure 4 (d), the MEM output signal S shown in Figure 4 (,), and the MEM output signal S shown in Figure 4 (,). Outputs the data control signal all, switches the direction of the bidirectional buffer 12 and the bidirectional buffer 13, and connects the PTYGEN/CHK7
From the data signal S shown in Fig. 4 (color) to Fig. 4 (C
) is generated, data is written into MEM4, and parity is written into MEM(PTY)5. Next, monitoring will be explained. First, DMA C2
The address signal 341m shown in Fig. 4 (a) K is shown in Fig. 4 (f
) MEM input signals s, e shown in Figure 4 (g) K! Data control signal 8 shown in Figure 4)
11, bidirectional buffer 12 and both PTYG
EN/CHK 7 checks the parity rule of the data and parity at the rising edge of the MEM input signal S6 shown in Figure 4 (f), and if an unreasonableness occurs, it is set to low level as shown in Section 4 (a). A parity error signal 811 is output.

[Problem that the invention seeks to solve]

The conventional memory parity generation/monitoring circuit described above is based on the CP
Although either U or DMAC controls the system path, there is a drawback that PTYGEN/CHK must be provided corresponding to 0° C. and omc, respectively.

[Means to solve the problem]

The memory parity generation/monitoring circuit of the present invention provides a bidirectional buffer that operates in response to a data control signal and a bidirectional buffer that operates in response to a parity control signal, thereby generating memory parity during program transfer and DMA transfer. The generation/monitoring circuit is activated.

[Effect]

According to the present invention, one memory parity generation/monitoring circuit can generate and monitor both program transfer and DMA transfer.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a memory parity generation/monitoring circuit according to the present invention. In the same figure, 1
6 is the T terminal 16a, the input terminal 16b and the input/output terminal 1
60, a bidirectional buffer that outputs data toward the system path when the T terminal 1Sa is at a high level; 1T is a T terminal 17a, an input terminal 17b, and an input/output terminal 17c.
1B is a bidirectional buffer that outputs data toward the Toki system bus whose T terminal 17& is at a high level.
The AND circuit 19 outputs the data control signal 818 shown in Figure U), and the parity control signal 14 shown in Figure 2K
This is an AND circuit that outputs .

Next, the operation of the memory parity generation/monitoring circuit having the above configuration will be explained with reference to FIGS. 2(-) to 2(a). First, parity generation at the time of prisoner program transfer will be explained. In the case of this program transfer, the CPU has control over the system bus, and the bus control signal S shown in FIG. 2 (h) is output from its AENI terminal 1c.
8 is at low level and is enabled. therefore,
The CPU 1 receives the address signal S6. shown in FIG. 2 (-). Second
I10 human power signal S2 shown in figure (d) and figure 2 (j)
outputs the data control signal 81B shown in FIG.
16 and inputs the data signal S3 shown in FIG. 2(b) from 1103. Next, the CPUI is shown in Figure 2 (
, ) shown in the address signal S6. Figure 2 (a) ME shown by K
M output signal S,.

The data control signal S□ shown in FIG. 2 (j) and the parity control signal 814 shown in FIG. Write the data signal S3 shown in Figure (b), and write PTYGEN/CI(
A parity signal S shown in FIG. 2(c) generated by K6 is written. Next, to explain monitoring, CP
U1 is the address signal S4 l4 shown in FIG.
MEM input signal S6. shown in Figure (f). The data control signal 5ill shown in FIG. 2(j) and the parity control signal 814 shown in FIG. PTY) Read the parity from 5. Then, the parity rule of the data and parity of PTYGEN/CHK6 is shown in FIG. 2(f).
It is checked at the rising edge of the input signal S6, and if an unreasonable condition occurs, a low level parity error signal is output.
Parity error signal 5i11 when no unreasonableness occurs
is at a high level as shown in Figure 2 (a). next,
φ): Parity generation during DMA transfer will be explained.

First, in the case of DMA transfer, control of the system bus is given to the DM.
AC2 has a path control signal S4+ as shown in FIG.
I10 human power signal S shown in Fig. 2 (d), l Fig. 2 (
It outputs the MEM output signal S shown in FIG. 2(j) and the parity control signal 814 shown in FIG. Switch direction and PTYGEN/C)I
K6 generates the parity signal S7 shown in FIG. 2(C) from the data signal S8 shown in FIG. 2(b), and
Data is written to φ conversion M (PTY) 5, and parity is written to φ conversion M (PTY) 5. Next, to explain the monitoring, DMAC2
are the address signals S shown in FIG. 2(a), lFIG. 2(f)
) shown in MEM input signal S6. VO output signal S l shown in 2nd oral history), data control signal S □ shown in Fig. 2 (j>)
8. It outputs the parity control signal 814 shown in FIG.
PTY) Read the parity from 5. And P.T.Y.
The parity rule of the GEN/CHK 6 data and parity is checked at the rising edge 9 of the MEM input signal S6 shown in FIG.
As shown in b), the parity error signal S1 is at a low level.
Outputs 2.

〔Effect of the invention〕

As explained in detail above, the memory parity generation/monitoring circuit according to the present invention has advantages such as being able to generate and monitor both program transfer and DMA transfer with one memory parity generation/monitoring circuit. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a memory parity generation/monitoring circuit according to the present invention, and FIG. 2(a) to FIG. 2A
1 is a diagram showing the waveforms of each part in FIG. 1, and FIG. 3 is a block diagram showing a conventional memory parity generation/monitoring circuit.
4(-) to 4(a) are diagrams showing waveforms at various parts in FIG. 3. 1...Central processing circuit, 2...Direct memory access controller, 3...Peripheral circuit, 4...
・Memory, 5...Parity memory, 6 and 7...
...Memory parity generation/monitoring circuit, 8 and 11...
...Unidirectional buffer, 9-13...Bidirectional buffer, 14...System bus, 151-150...
AND circuit, 16 and 1T...bidirectional buffer,
18 and 19...AND circuit.

Claims (1)

[Claims] A central processing circuit that controls the bus when transferring programs between peripheral circuits and memory circuits, a unidirectional buffer that operates in response to bus control signals that become valid during program transfer, and A direct memory access controller that controls the bus when performing direct memory access transfers that do not go through the central processing unit, a unidirectional buffer that operates in response to bus control signals that become valid during direct access memory transfers, and data control signals. A bidirectional buffer that operates in response to a parity control signal, a bidirectional buffer that operates in response to a parity control signal, and a bidirectional buffer that generates parity when writing data to a memory circuit and monitors parity rules when reading data from a memory circuit. A memory parity generation/monitoring circuit comprising a common memory parity generation/monitoring circuit.