JPS6263363A - Memory address control system - Google Patents

Abstract

PURPOSE:To easily connect the CPU having the large memory address space and the CPU having small memory address space to the bus where the I/O buffer is connected by converting the address between the CPU and the bus. CONSTITUTION:The address sent from a CPU is inputted through an address bus 1 to an address comparing part 2. At the address comparing part 2, it is decided whether or not the inputted address is the address of the I/O buffer, and the result is sent to an address converting part control signal 4. At an address converting part 3, by the address converting part control signal 4 from the address comparing part 2, the address supplied to the address bus 1 is sent to an address bus 5 as it is and the address supplied from the address bus 1 is converted and sent to the address bus 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory address control system, and particularly to a method for controlling a bus in an information processing device by controlling a plurality of CPUs, I10 buses, and buses having different memory address spaces. Motsu I
Conventional technology related to memory address control g173 formula that enables control of bus connecting 10 devices] Conventionally, when multiple CPUs are connected to 1I10 device having I10 buffer, the I10 buffer is connected to the bus, Furthermore, the structure was such that the CPUs were connected to the bus via a bus arbiter, and multiple CPUs used the bus exclusively to access the I10 packa.

[Problem that the invention seeks to solve]

However, in the conventional memory address control method described above, the address from the CPU is output as is, so when multiple CPUs with different memory address spaces are connected to the bus, I1 connected on the address bus
The address of the I10 buffer of a 0 device is rounded to fit a CPU with a small memory address space, or the address of the Noah's address is rounded to fit a CPU with a small memory address space. C
In the 13U memory address space, there was a drawback that the I10 buffer of the I10 device existed in the middle, or the address control of the I10A and 7A of the 13U device became complicated0 [Resolve the problem with F4 ] The memory address system of the present invention (I bandai is 110 of the addresses output from the CPU) and the ratio between the address comparison section that uses the Tsunoa address and the address comparison section j! ! ! 2
and an address converting section that converts the result into a serial address (ft).

〔Example〕

Next, Example 1c of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. 0 Memory address f! shown in FIG. 1! The tlJ sword ceremony is CP
and address bus 1 from which addresses are sent from U1.

Among the addresses supplied from the CPU, the address e of the I10 buffer is output by the address comparator 2, the address from the CPU is -1I10, the address converter 3 converts the address from the CPU to the address of Noah, and the ratio MFa in the address comparator 2. Addresses sent from the 0CPU, which is configured to include an address converter control signal 4 that notifies the address bus 3 of the result, and an address bus 5 to which 10 buffers are connected, pass the address bus 1 through the 11!1 series. , the input address is I10 in the rear address comparison unit 2, which is input to the address comparison unit 2.
0 address conversion unit 3 that determines whether or not it is a buffer address and sends the result to address conversion unit control signal 4;
Then, the address conversion unit control signal 4 from the address comparison unit 2
, the address supplied to address bus 1 is
2 is a system showing an example of the use of the memory address control method shown in FIG. 1. This is a schematic diagram of CPU 6 with a large address space and CPU 7 with a small address space.
It includes the memory address control system 8 shown in FIG. 1, a path arbiter 9, a bus 10, and an I10 buffer 11.

It is assumed that the address of the I10 buffer 11 is located at an optimized position in the address space of the CPU 6. Since the address space of the CPU 7 is small, the I10 buffer 7a 11 may not be able to access it directly. [Effects of the Invention] The memory address control method of the present invention enables the CPU 6 with a large address space to coexist. This has the effect that a CPU with a large memory address space and a CPU with a small memory address space can be easily connected to the same path.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing one embodiment of the present invention, and the WJ2 diagram is shown in Figure 1! ! FIG. 1 is a system schematic diagram showing an example of use of the embodiment. 1.5...address bus, 2...address comparison section, 3...address conversion section, 4...
・・・Address conversion unit control signal, 6, 7...C
PU, 8...Memory address control method, 9...
... Bus arbiter, 10 ... Pass, 11
...I10 buffer 701 ...,. Agent Patent Attorney Uchihara f+′・:Also:1・
7-・ (,=

Claims (1)

[Claims] In a system where multiple CPUs with different memory address spaces share an I/O buffer, an address provided between a CPU with a small memory address space and a bus to which the I/O buffer is connected, and which is supplied from the CPU. an address comparator that generates an address conversion unit control signal when is an address of an I/O buffer; and an address comparison unit that outputs an address of the I/O buffer instead of the address when the address conversion unit control signal is supplied. A memory address control method comprising: an address control section.