JPH01180653A - Data access system - Google Patents

Abstract

PURPOSE:To eliminate the need for a bus switching and to improve the economicity of an information processing system by synthesizing a second address lower part transmitted through a bus and a second address upper part transmitted not through the bus and preparing an address to a second address space. CONSTITUTION:An address control means 500 sends a first address upper part a1 to show the position of a window area WDW in a first address space 200 and a second address lower part a2' to a bus 400 and transmits a second address upper part a1' to an address converting means 600 not through the bus 400 when a processor 100 refers to a position to be designated by the second address upper part a1' to show the position of a partial area B as a reference object in a second address space 300 and the second address lower part a2 to show a reference position in the partial area B as the reference object. Thus, the necessity of switching the bus from the first address space 200 to the second address space 300 is eliminated and the economicity of the information processing system is improved.

Description

[Detailed Description of the Invention] [Summary] Data access in an information processing system that includes a first address space that can be directly referenced by a processing device and a second address space that has the same address as the first address space. Regarding the method, the purpose is to make it possible to refer to a second address space that has the same address as the first address space that is directly referenced from the processing device, without impairing the economic efficiency of the information processing system as much as possible. providing a window area in a predetermined area within the address space of the second address space, dividing the second address space into a plurality of partial areas each having an area smaller than or equal to the window area, and providing an address control means in the processing device;
An address conversion means is provided between the second address space and the bus, and the address control means includes a second address upper part indicating a position of a partial area to be referenced in the second address space by the processing device; a first address upper part indicating the position of the window area within the first address space; , and a second lower part of the address to the bus, and transmits the upper part of the second address to the address translation means without passing through the bus, and the address translation means transmits the first address upper part and the second address upper part from the bus. When the second lower address part is received, the second address upper part a, I and the second address lower part transmitted from the processing device without going through the bus are sent to the second address space. Configure it to do so.

[Industrial application field]

The present invention relates to an information processing system, and in particular, data access in an information processing system that includes a first address space that can be directly referenced by a processing device, and a second address space that has the same address as the first address space. Regarding the method.

In an information processing system, in addition to read/write memory that can be directly referenced by a processing device, if a buffer memory that is not directly referenced by the processing device is provided, for example, for direct memory access transfer, an address that can be directly referenced by the processing device is provided. It is not rare that a part of the space is not allocated to the buffer memory, but an address space that overlaps with an address space that can be directly referenced by the processing device is provided to the buffer memory.

In such an information processing system, when it becomes necessary for the processing device to refer to the buffer memory, it is desired to realize a means for the processing device to refer to the buffer memory as economically as possible.

[Conventional technology]

FIG. 6 is a diagram showing an example of a conventional data access method, and FIG. 7 is a diagram illustrating the address space in FIG. 6.

In FIG. 6, ■ is a processor (MPU) that is the center of control of the information processing system, and 2 is a dedicated memory (R) that stores programs, etc. executed by the processor 1.
OM), 3 is an input/output device (10) through which the processor (MPU) 1 transmits and receives data, 4 is a read/write memory (RAM) in which the processor 1 temporarily stores data, etc., 5 is independent of the read/write memory 4 Bank memory provided in (
BKM), 6 is a direct memory access control device (DMA) that controls data transfer to the bank memory 5.
C), 7 is a selector (SEL), 8 is an address bus (AB) through which the processor 1 sends the address A specifying the reference target, and 9 is a data bus (D) through which the processor 1 sends and receives data to and from the reference target. B).

When the switching signal sw transmitted from the processor 1 via the control signal line 14 is set to logic "0", the selector 7 controls the address bus 8 and the data bus 9 to reach the write/read memory 4. Address line 10 and data line 1
1, and the switching signal sw is set to be connected to logic “
1", the address bus 8 and data bus 9 are set to be connected to the address line 12 and data \a13 leading to the bank memory 5. Normally, the processor 1
Since the switching signal sw is set to logic "O", the write/read memory 4 is connected to the address bus 8 and data bus 9 via the address line IO, data line LL, and selector 7.
It is connected to the.

Now, if the address A sent by the processor 1 to the address bus 8 has a 16-bit configuration, the first address space 200 that can be directly referenced by the processor 1 is 64 kilowords.
The first address space 200 is allocated to the read-only memory 2, the input/output device 3, and the read/write memory 4 that are directly referenced by the processor 1. In FIG. 7, addresses A=(0000)H to (7F) are stored in the write/read memory 4.
FF)H (however, H indicates hexadecimal display, the same applies below) 3
Addresses A = (8000)H to (FFFF) that allocate 2 kilowords and remain in read-only memory 2 and input/output device 3
32 kilograms of H are assigned.

On the other hand, the bank memory 5 is usually referenced only by the direct memory access control device 6, but when the processor 1 needs to refer to the bank memory 5, it is transmitted to the selector 7 via the control signal line 14. The switching signal sw is set to logic "1", and the selector 7 is connected to the address bus 8 and the address line 10, as well as the data bus 9 and the data line 1.
1, and address bus 8 and address line 12,
Also, data bus 9 and data line 13 are connected.

In this state, when processor l sends address A=(0000))I to (7F F F)□ to address bus 8, address A is sent to selector 7 and address line 1.
2 to the bank memory 5, refers to the position specified by the address A in the bank memory 5, and stores the data to be transmitted via the data bus 9, the selector 7, and the data line 13, or Data stored in the location specified by address A in bank memory 5 is extracted via data line 13, selector 7, and data bus 9.

[Problem that the invention seeks to solve]

As is clear from the above description, in a conventional data access method, all the lines (
6 and 7) from the write/read memory 4 side to the bank memory 5 side.
However, there was a risk that the economic efficiency of the information processing system would be impaired.

An object of the present invention is to enable a processing device to refer to a second address space having the same address as a first address space directly referred to, without impairing the economic efficiency of the information processing system as much as possible.

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the present invention.

In FIG. 1, 100 is a processing device, 200 is a first address space that can be directly referenced by the processing device 100, 300 is a second address space having the same address as the first address space 200, and 400 is a bus. .

WDW is a window area provided in a predetermined area within the first address space 200 according to the present invention.

B is a partial area in which the second address space 300 is divided into a plurality of areas each below the window area WDW according to the present invention.

500 is an address control means provided in the processing device 100 according to the present invention.

Reference numeral 600 denotes address conversion means provided between the second address space 300 and the bus 400 according to the present invention.

C Effect] The address control means 500 generates a second address upper part a that indicates the position of the partial area B that the processing device 100 refers to in the second address space 300.

” and the second address lower part a21 indicating the reference position in the partial area B to be referenced, the position of the window area WDW in the first address space 200 is The first address upper part a and the second address lower part a2 shown in FIG.
It is transmitted to the address translation means 600 without going through.

When the address conversion means 600 receives the first address upper part a and the second address lower part a2° from the bus 400, the address conversion means 600 converts the second address transmitted from the processing device 100 without going through the bus 400. The upper parts a, l and the second lower address part a2'' are sent to the second address space 300.

Therefore, only the lower part of the second address transmitted from the processing device via the bus and the lower part of the second address transmitted without going through the bus are combined and sent to the second address space. This eliminates the need to switch the bus from the first address space to the second address space, improving the economic efficiency of the information processing system.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a diagram showing a data access method according to an embodiment of the present invention, FIG. 3 is a diagram illustrating the bank address control process in FIG. 2, and FIG. 4 is a diagram showing the bank address conversion in FIG. FIG. 5 is a diagram illustrating the process, and FIG. 5 is a diagram illustrating the address space in FIG. 2. Note that the same reference numerals refer to the same objects throughout the plan.

In FIG. 2, the address control means 5 in FIG.
00, a bank address control unit (BAC) 101 is provided in the processor (MPU) 1, and a bank memory control unit (BMC) 15 is provided as address conversion means 600 in FIG. It is provided between the bus (DB) 9 and the address line 12 and data line 13 leading to the bank memory (BKM) 5.

2 to 5, if the address A sent by the processor 1 to the address bus 8 has a 16-bit configuration, then the first address space 2 that can be directly referenced by the processor 1 is
00 is a 64 kiloword, but in Fig. 5, address A = (0000) is written in the write/read memory (RAM) 4a.
)I to (6FFF)H, and address A = (8000)o to (FFFF)o 32 to the continuous memory (ROM) 2 and input/output device (10) 3.
In addition to assigning the kilo word, address A=(7
4 kilowords from 000)H to (7FFF)H are assigned.

On the other hand, the bank memory 5 constituting the second address space 300 has a storage capacity of 64 kilowords, and similarly to the first address space 200, addresses A'=(0000)H to (FFFF)o Referenced.

The bank memory 5 includes 16 banks B each having the same storage capacity (4 kilowords) as the window area WDW provided in the first address space 200. It is divided into BIS to BIS.

Therefore, the upper 4 bits of the address A' used in the bank memory 5 (hereinafter referred to as the second upper part a, ") specify the position of each bank B0 to BIS, and the lower 12
A bit (hereinafter referred to as the second address lower part a21) specifies a location within each bank B0-B1.

Note that the write/read memory 4a is directly connected to the address bus 8 and the data bus 9 without going through a selector (SEL) 7 (FIG. 6) or the like.

In addition to the address bus 8 and the data bus 9, a control signal line 14a is provided between the processor 1 and the bank memory control section 15 for transmitting the second upper address part a, ".

In this state, the processor 1 accesses the first address space 20
When referring to an area other than the window area WDW in 0, for example, the write/read memory 4a, the bank address control unit 101
The referent of processor 1 is analyzed in step 5 of Figure 3.
ll), if it is determined that the bank memory 5 is other than the bank memory 5 (step 512), address A=(0000), l to (6FF
F) Send 8 to address bus 8. The address A is transmitted to the read-only memory 2, the input/output device 3, the write/read memory 4a, and the bank memory control unit 15 via the address bus 8, and the address in the read/write memory 4a designated by the address A is The location is referenced.

On the other hand, when the processor 1 refers to the bank memory 5, the bank address control unit 101 analyzes the reference target of the processor 1 (step 5ll), and if it determines that it is the bank memory 5 (step $12), the bank address control unit 101 Address A' = (000
0) to (FFFF)H second address upper part at
”= (0) to (F)H are sent to the control signal line 14a (step 314), and (7)H indicating the position of the window area WDW is set as the first address upper part a, and the second Address lower part a! ° to first address lower part a
An address A is created to be t and sent to the address bus 8 (step 515).

The address A sent by the processor l to the address bus 8 is transmitted via the address bus 8 to the continuation-only memory 2, the input/output device 3, the write/read memory 4a, and the bank memory control section 15. However, when the bank memory control unit 15 receives address A via the address bus 8 (step 521 in FIG. 4), it analyzes the received address A (step 522). The upper address part a of the first address is the window area WDW
If it is determined that it is other than (7)□, which is assigned to
It is determined that bank memory 5 is not a reference target, and address A is ignored (input step 524).

On the other hand, as a result of the analysis in step S22, if it is determined that the first address upper part a is (7)11, it is determined that the bank memory 5 is the reference target, and the data is transmitted from the processor 1 via the control signal line 14a. The received second address upper parts a,l and the first address lower part a2 received via the address bus 8, i.e. the second address lower part a.
Step 525: Synthesize address A' by 2°.
), the combined address A1 is sent to the address line 12 leading to the bank memory 5 (step 526), and the data bus 9 and the data line 13 leading to the bank memory 5 are connected (step 527).

The bank memory 5 allows the processor 1 to refer to the location specified by the address A' transmitted via the address line 12, and connects the data bus 9 and the bank memory control unit 1.
5 and the data line 13, or the data stored in the position specified by the address A' in the bank memory 5 is stored in the data line 13 and the bank memory control unit. 15 and data bus 9.

As is clear from the above description (according to this embodiment, when the reference target is address A1 of the bank memory 5, the bank address control unit 101 sends the second address upper part a1° to the control signal line 14a). , and address A (al
= (7) n -, at = a21] to the address bus 8, and the bank memory control unit 15 determines that the address upper part a of the received address A is (7) Only in the case of H, address A"(al' = aB% at' = a2
) is synthesized and sent to the address line 12, and the data bus 9
By simply performing simple control such as simply connecting the data line 13 and the data line 13, there is no need to switch between the 16 address buses 8 as in the selector 7 shown in FIG. 6, resulting in an economical configuration.

Note that FIGS. 2 to 5 are only one embodiment of the present invention, and for example, the first address space 200 and the second address space 300 are not limited to what is shown in the figures, and other Many modifications may be considered, but the effects of the present invention remain the same in any case. Further, the window area WDW and the areas of the banks B0 to BI5 are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention remain the same in any case. Furthermore, it goes without saying that the information processing system to which the present invention is applied is not limited to what is illustrated.

〔Effect of the invention〕

As described above, according to the present invention, in the information processing system, the lower part of the second address transmitted from the processing device via the bus, and the upper part of the second address transmitted without passing through the bus. By simply combining and creating an address for the second address space, there is no need to switch the bus from the first address space to the second address space.
The economic efficiency of the information processing system is improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a data access method according to an embodiment of the present invention, and FIG.
Figure 4 illustrating the bank address control process in Figure 4.
5 is a diagram illustrating the address space in FIG. 2, FIG. 6 is a diagram illustrating an example of a conventional data access method, and FIG. 7 is a diagram illustrating the bank address conversion process in FIG. 2. FIG. 6 is a diagram illustrating the address space in FIG. 6; In the figure, l is the processor (MPU), 2 is the read-only memory (ROM), 3 is the input/output device (10), and 4 is the input/output device (10).
and 4a is a write/read memory (RAM), 5 is a bank memory (BKM), 6 is a direct memory access control device (DMAC), 7 is a selector (SEL),
8 is address bus (AB), 9 is data bus (DB)
, 10 and 12 are address lines, 11 and 13 are data lines, 14 and 14a are control signal lines, 15 is a bank memory control unit (BMC), 100 is a processing device, 101 is a bank address control unit (BAC), and 200 is a The first address space, 300 is the second address space, 400 is the bus, 500 is the address control means, 600 is the principle of address failure (9) Hayabusa 1 ,'Kaya 2
I17 ゛゛゛□s@i゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛□s@i゛゛゛□s@i゛゛□s＠゛

Claims (1)

[Claims] A first address space (200) that can be directly referenced by the processing device (100) via the bus (400), and a second address having the same address as the first address space (200). A window area (WDW) is provided in a predetermined area within the first address space (200), and a window area (WDW) is provided in a predetermined area within the first address space (200), and the second address space (300) is The processing device (100) is divided into a plurality of partial areas (B) having areas smaller than or equal to the window area (WDW), and the processing device (100) is provided with an address control means (500).
and the second address space (300) and the bus (400) are provided.
), and the address control means (500) is arranged between the processing device (1
00) indicates the position of the partial area (B) to be referred to in the second address space (300), and the second address upper part (a_1'), and the partial area (B) to be referred to.
Second address lower part (a_2') indicating the reference position within
When referring to the position specified by the window area (WDW) in the first address space (200),
) and the second address lower part (a_2') indicating the location of the bus (4).
00), and the upper part of the second address (
a_1′) to the address conversion means (600) without passing through the bus (400), and the address conversion means (600)
), the first address upper part (a_1) and the second address lower part (a_2') are received from the processing device (100) without going through the bus (400). Upper part of the second address (a_1
') and the second lower address part (a_2') to the second address space (300).