JP2754211B2 - Multiprocessor control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a multiprocessor control method in a multiprocessor system in which a plurality of processors access respective corresponding individual areas of a common memory, each processor corresponds to a different individual area on the common memory. Also in this case, the purpose is to enable processors of the same standard to be used, and a plurality of processors (100) and each of the processors (100)
In a multiprocessor system including a common memory (5) having a plurality of individual areas (50, 51, 52,...) Corresponding to each of the plurality of processors (100) and the common memory (5), Is provided with an address conversion means (200), and all the processors send out the pre-conversion address (a ₀ ) assigned to a specific individual area (for example, 50) among a plurality of individual areas of the common memory (5). When the access source processor has a function and accesses the individual area corresponding to the access source in the common memory (5), the access source processor sends the address before conversion (a ₀ ) to the address conversion means (200). and sent enable signal (e) identifies the access source processor, the address conversion means before conversion received address (a _0), by the above enable signal (e), the pre-conversion Converted to dress (a ₀₎ is the applied to the individual areas corresponding to the access source processor the translated address (a '), and transmitted to the common memory (5), the corresponding individual from the access source processor in the shared memory Make it possible to access the area. Also, multiple processors (100) and common memory (5)
Address conversion means (200) provided between the pre-translation address (a ₀ ) sent from the access source processor and the enable signal (e) for identifying the access source processor. '), The conversion rule (γ) for the conversion is designated so that the individual area corresponding to the access source processor can be changed.

[Industrial applications]

The present invention relates to a multiprocessor system, and more particularly to a multiprocessor control method in a multiprocessor system in which a plurality of processors access respective corresponding areas of a common memory.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional multiprocessor system.

In FIG. 4, nine data link control units 1 (individual data link control units are referred to as 1-0 to 1-8, hereinafter the same) are connected to a common control unit 4 via a common bus 6 and a common memory. 5 is connected.

Of the nine data link control units 1, eight data link control units 1-0 to 1-7 are currently used and the synchronizer unit 2
The data is transmitted / received via the corresponding data link 3 via the corresponding data link 3, and the remaining one data link control unit 1-8 is used as a spare as an unusable data link control unit 1-8.
Data transmission / reception is executed instead of 0 to 1-7.

The common memory 5 is provided with individual areas 50 to 58 for the data link controllers 1-0 to 1-8 to transmit and receive commands and statuses to and from the common controller 4, respectively.

Therefore, each data link control unit 1-0 to 1-8
In order to access the corresponding individual areas 50 to 58, individual addresses a ₀ assigned to the individual areas 50 to 58, respectively.
Or a a _8, it is necessary to transmit the common memory 5 through the common bus 6.

[Problems to be solved by the invention]

As is apparent from the above description, in the conventional multiprocessor system, each data link control unit 1-0
To 1-8, to respectively access the specific discrete regions 50 to 58 in the common memory 5, is necessary to send the respective individual addresses a ₀ to a ₈ given to each individual area 50 to 58 As a result, the same data link control unit 1 cannot be used, and the economics of the multiprocessor system may be impaired.

It is an object of the present invention to enable processors of the same standard to be used even when each processor corresponds to a different individual area on a common memory.

[Means for solving the problem]

The object of the present invention is to provide a plurality of processors (100) and the respective processors (100) as shown in the principle diagram of FIG.
In a multiprocessor system including a common memory (5) having a plurality of individual areas (50, 51, 52,...) Corresponding to each of the plurality of processors (100) and the common memory (5), Is provided with an address conversion means (200), and all the processors transmit the pre-conversion address (a ₀ ) assigned to a specific individual area (for example, 50) among a plurality of individual areas of the common memory (5). When the access source processor accesses the individual area corresponding to the access source in the common memory (5), the address conversion means (20
0), the pre-translation address (a ₀ ) and an enable signal (e) for identifying the access source processor are sent out, and the address translating means receives the pre-translation address (a ₀ ).
And the enable signal (e), the pre-conversion address (a ₀ ) is converted into a converted address (a ′) assigned to an individual area corresponding to the access source processor, and transmitted to the common memory (5). The multiprocessor control method is characterized in that an access source processor can access a corresponding individual area in a common memory.

Also, a plurality of processors (100) and a common memory (5)
Address conversion means (200) provided between the pre-translation address (a ₀ ) sent from the access source processor and the enable signal (e) for identifying the access source processor. This is achieved by designating the conversion rule (γ) for conversion to ') so that the individual area corresponding to the access source processor can be changed.

[Action]

The address translation means 200 transmits the common memory 5 sent from each processor 100 attempting to access the common memory 5.
The pre-conversion address a ₀ assigned to the specific individual area 50 of
An enable signal e for identifying the processor 100 of the access source is received, converted to a converted address a ′ assigned to the individual area 50 corresponding to the processor 100 of the access source, and transmitted to the common memory 5.

The address converting means 200, changes the pre-conversion address a ₀ and the enable signal e that is input by specifying the conversion rule r the translated address a 'to output, the discrete areas 50 corresponding to each processor 100 Make it possible.

Therefore, since each processor accesses a different individual area, the same address can be transmitted, and processors of the same standard can be used, thereby improving the economy of the multiprocessor system.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Second
FIG. 3 is a diagram showing a multiprocessor system according to one embodiment of the present invention, and FIG. 3 is a diagram showing an example of an address conversion unit in FIG. The same reference numerals indicate the same objects throughout the drawings.

In FIG. 2, a plurality of processors in FIG.
9 data link controllers 1-0 to 1-8 as 100
The address conversion unit 7 is provided as the address conversion means 200 in FIG.

The address conversion unit 7 shown in FIG. 3 shows a case where the common memory 5 shown in FIG. 2 has a 16-bit address space and each of the individual areas 51 to 58 has 4096 addresses. .

Initially, the register 71 of the address conversion unit 7 stores the index address b of the conversion memories 73-0 to 73-8 from the common control unit 4.
As bits B ₄ to B _{7 (0) H} (where H is a hexadecimal display)
Is set.

2 and 3, the data link control units 1-0 to 1-7 are initially used, and the data link control units 1-8 are used.
Are reserved, and the individual areas 50 to 58 of the common memory 5 are
Correspond to the data link control units 1-0 to 1-8, respectively.

In this state, in order for the data link control unit 1-0 to access the corresponding individual area 50 in the common memory 5, the address a ₀ (= 50) assigned to a specific individual area (for example, 50) in the common access 5 A _{0 to} A ₁₅ , where A _{12 to} A ₁₅ are (0)
Is referred to as _H), and transmitted to the address conversion portion 7 through the common bus 6, also transmitting the specific enable signal e ₀ in the address conversion portion 7 to the data link controller 1-0.

In the address conversion unit 7, the data link control unit 1
−0, the address before conversion transmitted via the common bus 6
Of a ₀ , the address bits A _{0 to} A ₁₁ are transmitted as they are to the common memory 5 as the address bits A ₀ ′ to A ₁₁ of the converted address a ₀ ′, and the address bits A _{12 to} A ₁₅ are the index address b transmitting the index address bits B ₈ through B ₁₁ in the conversion memory 73-8.

On the other hand, in response to the enable signal e ₀ which is transmitted from the data link controller 1-0, (0) as an index address bits B ₀ through B ₃ of the index address b from the conversion memory 72 converts _H is extracted memory 73 -0 to 73-8, and from the register 71, the set index address bit
B ₄ to B ₇ = _{(0) H} is transmitted to the conversion memory 73-0 to 73-8.

As described above, the index address b = (0.0.0) _H is transmitted to the conversion memories 73-0 to 73-8, and the conversion memories 73-0 to 73-8 are transmitted.
(0) _H is extracted from the area corresponding to (0.0.0) _H of 0 as the address bits A ₁₂ ′ to A ₁₅ ′ of the converted address a ′ and transmitted to the common memory 5.

As a result, the address bit A ₁₂ to A ₁₅ before conversion data link controller 1-0 is sent to the common bus 6 addresses a ₀
Is transmitted to the common memory 5 as the converted address a ′ converted into the address bits A ₁₂ ′ to A ₁₅ ′ = (0) _H , and the individual area 50 can be accessed.

Next to the data link controller 1-1, accesses the corresponding individual area 51 in the shared memory 5, data link controller 1-0 same address a ₀ and, via the common bus 6 Address Translation transmitted to part 7, also transmits a unique enabling signal e ₁ to the address conversion portion 7 to the data link controller 1-1.

Address converting unit 7, in the same manner as described above, of the pre-conversion address a ₀ transmitted from the data link controller 1-1 via the common bus 6, the address bits A0 to A ₁₁ is the Mom,
'Address bit A _0' of translated addresses a0 to A ₁₁ '
Transmitted to the common memory 5 as address bits A ₁₂ to A
₁₅ conversion memory 73 as an index address bits B ₈ through B ₁₁
-0 to 73-8.

On the other hand, in response to the enable signal e ₁ which is transmitted from the data link controller 1-1, the conversion from the memory 72 as an index address bits B ₀ to B ₃ (1) converting _H is extracted memory 73-0 to 73 It is transmitted to -7, and from register 71, like the previously described index address bits B ₄ to B ₇ = (0)
_H is transmitted to the conversion memories 73-0 to 73-8.

As described above, the index address b = (0.0.0) _H is transmitted to the conversion memories 73-0 to 73-8, and the conversion memories 73-0 to 73-8 are transmitted.
(1) _H is extracted from the area corresponding to (001) _{H of} 0 as address bits A ₁₂ ′ to A ₁₅ ′ of the converted address a ′ and transmitted to the common memory 5.

As a result, the address bit A ₁₂ to A ₁₅ of the pre-conversion address a ₀ that sent the data link controller 1-1 common bus 6
Is transmitted to the common memory 5 as the converted address a 'converted into the address bits A ₁₂ ′ to A ₁₅ ′ = (1) _H , and the individual area 51 can be accessed.

In the same way, for the data link controller 1-7, stored in the corresponding individual areas 57 in the common memory 5, common data link controller 1-0 same address a ₀ and the bus 6
Address bits by the address transmitted to the conversion unit 7, also when transmitting a specific enable signal e ₇ to the address conversion portion 7 to the data link controller 1-7, the address bit A ₁₂ to A ₁₅ is the address converting unit 7 via the A ₁₂ 'to A _15' =
(7) It is converted to _H , transmitted to the common memory 5 as the converted address a ', and the individual area 51 can be accessed.

Note Preliminary data link controller 1-8 and sends the converted pre-address a ₀ and the enable signal e ₈ to the common bus 6 by the same process, the address bit A ₁₂ to A ₁₅ is, address bits by the address converting unit 7 A ₁₂ 'to A _15' =
(8) Converted to _H , and the individual area 58 can be accessed.

Next, when the data link control unit 1-0 becomes unusable due to an obstacle and the corresponding data link 3 is transmitted / received in place of the spare data link control unit 1-8, the common control unit 4 uses the address conversion unit 7 And the address p specifying the register 71 in the index address bits B _{4 to} B ₇ =
(1) When sending the _H to the common bus 6, the register 71 in the address conversion portion 7, the index address bits B ₄ to B ₇ =
(1) _H is set.

In this state, the data link control unit 1-8, transmits the address a ₀ in the address conversion portion 7 through the common bus 6,
Also, an enable signal unique to the data link control unit 1-8.
e ₈ is transmitted to the address conversion unit 7.

In the address conversion unit 7, the data link control unit 1
-8, the pre-translation address transmitted via the common bus 6.
Of a _0, the address bits A0 to A ₁₁ is transmitted to the common memory 5 as a mom, 'address bits A0' of translated addresses a ₀ to A ₁₁ ', the address bit A ₁₂ to A ₁₅ is the index address b transmitted to the conversion memory 73-0 to 73-8 as an index address bits B ₈ through B _11.

On the other hand, in response to the enable signal e ₈ transmitted from the data link controller 1-8, the conversion from the memory 72 of the index address b Index address bits B ₀ to a B ₃ (8) transform _H is extracted memory 73 -0 to 73-8, and from the register 71, the set index address bit
B ₄ to B ₇ = _{(1) H} is transmitted to the conversion memory 73-0 to 73-8.

As described above, the index address b = (0.1.8) _H is transmitted to the conversion memories 73-0 to 73-8, and as a result, the area corresponding to (018) _H in the conversion memory 73-1 is shifted to (0) _H But,
Address bits A ₁₂ ′ to A ₁₅ ′ of translated address a ′
And transmitted to the common memory 5.

As a result, the address bit A ₁₂ to A ₁₅ before conversion data link controller 1-8 is sent to the common bus 6 addresses a ₀
Is transmitted to the common memory 5 as the converted address a ′ converted into the address bits A ₁₂ ′ to A ₁₅ ′ = (0) _H , and the individual area 50 can be accessed.

Next, the data link control unit 1-1 to 1-7, to the corresponding access individual areas 51 to 57 in the common memory 5, common data link controller 1-0 same address a ₀ and bus 6 is transmitted to the address conversion portion 7 through, also when transmitting a specific enable signals e ₁ to e ₇ to the address conversion portion 7 to the data link controller 1-1 to 1-7, the address converting unit 7, the transfer Of the converted address a ₀ , the address bits A _{0 to} A ₁₁ are left as they are, and the converted address a ₀ ′
Address bits A0 'to A _11' is transmitted to the common memory 5 as address bits A ₁₂ to A ₁₅ conversion memory 73-0 as an index address bits B ₈ through B ₁₁ index address b
To 73-8.

On the other hand, in response to the enable signal e ₁ to e ₇ transmitted from the data link controller 1-1, as an index address bits B ₀ to B ₃ from the conversion memory 72 (1) _H to (7) _H is extracted is transmitted to the conversion memory 73-0 to 73-8 Te, and from register 71 have been set index address bits B ₄ to B ₇ = (1) _H is transmitted to the conversion memory 73-0 to 73-8 You.

As described above, the index addresses b = (0.1.1) _{H to} (0.1.7) _H are transmitted to the conversion memories 73-0 to 73-8.
From the area corresponding to the index address b of the conversion memory 73-1 = (0.1.1) _{H to} (0.1.7) _H , (1) _{H to} (7) _H
Are the address bits A ₁₂ ′ to A ₁₂ of the translated address a ′.
₁₅ 'and transmitted to the common memory 5.

As a result, the address bits of the pre-conversion address a ₀ to the data link controller 1-1 to 1-7 are sent to the common bus 6
A _{12 to} A ₁₅ are address bits A ₁₂ ′ to A ₁₅ ′ = (1)
_{H to} (7) are converted to _H , transmitted to the common memory 5 as the converted address a ', and the individual areas 51 to 57 can be accessed.

Note the data link controller 1-0 in use stopped, sends a pre-conversion address a ₀ and the enable signal e ₀ in the common bus 6, the address bits A ₁₂ to A ₁₅ is, translated addresses a by the address converting unit 7 'Address bits
A ₁₂ ′ to A ₁₅ ′ = (8) are converted to _H , and the individual area 58 can be accessed.

Similarly, when the data link control unit 1-7 becomes unusable due to a failure or the like and the corresponding data link 3 is transmitted / received instead of the spare data link control unit 1-8, the common control unit 4 sends the address by setting the index address bits B ₄ to B ₇ = (8) _H in the register 71 in the conversion unit 7, the data link control unit 1-8 sends the address a ₀ and the enable signal e _8, the index address b = (0.
8.8) is transmitted to the conversion memories 73-0 to 73-8, and the index address b = (0.8.8) to (7) of the conversion memory 73-8.
_H is transmitted to the common memory 5 as the converted address bits A ₁₂ ′ to A ₁₅ ′, and the individual area 57 can be accessed. When the data link control unit 1-7 sends the address a ₀ and the enable signal e ₇ , Index address b = (0.
8.7) is transmitted to the conversion memories 73-0 to 73-8, and the index address b of the conversion memory 73-8 is changed from (0.8.7) to (8).
_H is transmitted to the common memory 5 as the converted address bits A ₁₂ ′ to A ₁₅ ′ so that the individual area 58 can be accessed. Further, the other data link control units 1-0 to 1-6 control the address a ₀ and the enable signal. When e _{0 to} e ₆ are sent out,
The index addresses b = (0.8.6) to (0.8.6) are transmitted to the conversion memories 73-0 to 73-8, respectively.
From the index address b = (0.8.0) to (0.8.6), (0) _{H to} (6) _H are converted address bits A
It is transmitted to the common memory 5 as ₁₂ 'to A _15', respectively made accessible to the individual area 50-56.

As is clear from the above description, according to the present embodiment, the common control unit 4 sets the index address bits B _{4 to} B ₇ = (0) _H in the register 71 in the address conversion unit 7, thereby making the current operation possible. each data link controller 1-0 to 1-7 are the same pre-conversion address a _0, by respectively transmitting the specific enable signals e ₀ through e ₇ to the address conversion portion 7,
The respective individual areas 50 to 57 can be accessed.

The data link control unit 1-0 to 1-7 becomes unusable, when the spare data link controller 1-8 is substituted, the common control section 4 to the index address bits B ₄ in the register 71 from the B ₇ = (1) _{H to} (8) By setting _H , the data link control unit 1-8 allows the pre-conversion address a ₀
And the transmit enable signal e ₈ to the address conversion portion 7, the data link control unit 1-0 to 1 substituting respectively
The individual areas 50 to 57 corresponding to -7 can be accessed. Note that the other data link control units 1-0 to 1-7
The corresponding individual areas 50 to 57 remain accessible.

Therefore, the common control unit 4 also performs the data link control unit 1-0.
Data link 3 regardless of the operation state of
, The individual areas 50 to 57 are accessed, so that there is no need to consider a spare substitute.

FIGS. 2 and 3 are merely examples of the present invention. For example, the number of the data link control units 1 and the areas of the individual areas 50 to 58 are not limited to those illustrated. Nonetheless, many other variations are considered, but in each case the effect of the invention remains the same. The processor 100 to which the present invention is applied includes a data link control unit 1 shown in FIG.
Needless to say, it is not limited to this.

〔The invention's effect〕

As described above, according to the present invention, in the multiprocessor system, each processor can transmit the same address to access a different individual area, and a processor of the same standard can be used.
The economy of the multiprocessor system is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing a multiprocessor system according to an embodiment of the present invention, FIG. 3 is a diagram showing an example of an address conversion unit in FIG.
FIG. 1 is a diagram showing an example of a conventional multiprocessor system. In the figure, 1 is a data link control unit, 2 is a synchronization control unit, 3 is a data link, 4 is a common control unit, 5 is a common memory, 6 is a common bus, 7 is an address conversion unit, 50 to 58 are individual areas, 71 is a register, 72 and 73-0 to 73-8 are translation memories, 100 is a processor, 200 is address translation means,
Is shown.

Claims (2)

(57) [Claims] A plurality of processors (100) and a plurality of individual areas (50, 51, 52,...) Corresponding to each processor (100).
···), in a multiprocessor system having a common memory (5), an address translation means (200) is provided between the plurality of processors (100) and the common memory (5); Has a function of transmitting a pre-translation address (a ₀ ) assigned to a specific individual area (for example, 50) among a plurality of individual areas of the common memory (5), and the processor that accesses the common memory (5) When accessing the individual area corresponding to the access source in the above, the address conversion means (200) is transmitted from the access source processor.
In response, the pre-translation address (a ₀ ) and an enable signal (e) for identifying the access source processor are sent out, and the address translating means receives the pre-translation address (a ₀ )
With the enable signal (e), the pre-conversion address (a ₀ ) is converted into a converted address (a ′) assigned to the individual area corresponding to the processor of the access source and transmitted to the common memory (5). A multiprocessor control method, wherein an access source processor can access a corresponding individual area in a common memory. 2. An address conversion means (200) provided between a plurality of processors (100) and a common memory (5).
Defines the conversion rule (γ) for converting from the pre-translation address (a ₀ ) sent from the access source processor and the enable signal (e) for identifying the access source processor to the translated address (a ′). 2. The multiprocessor control method according to claim 1, wherein an individual area corresponding to the access source processor can be changed by designating.