JPS60142767A - Asynchronous type bus dominating system - Google Patents

Abstract

PURPOSE:To shorten the time when a central processing unit cannot dominate a bus by limiting a bus dominating right of a direct memory access channel controller only to a direct memory access channel with priority. CONSTITUTION:A common bus 8 connects a CPU6 and each memory block (MB)7 via a direct memory access channel controller (DMAC)10. The MBs 7 is divided into MB1-MBn and MBn-MBN and DMA11-DMAnm as the direct memory channel block (DMA)9 with priority are subordinated to the MB1- MBn. Moreover, DMA request lines BREQ1-Qn are connected in paralle with with DMAC10 from each DMA9. Thus, the bus dominating right of the DMAC10 is exerted only to the limited DMA in this way so as to shorten the time when the CPU6 cannot dominate the bus.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a system in which a central processing unit and a memory and a memory and a plurality of direct memory access channels are connected by a common bus. Regarding the control of multiple direct memory access channels, all direct memory access channels are given priority over the central processing unit via an asynchronous bus control system.〇Φ) Conventional technology and problems Generally, in medium-sized or larger computers, Since direct memory access channel devices have become standard equipment, data input/output is performed through registers. As a result, the data processing speed is significantly slowed down, so in small computers, a device that can handle a large amount of data is connected to the input/output device without using a register.

For example, FIG. 1 shows a conventional system having an asynchronous bus, including a central processing unit (hereinafter referred to as CPU) 1 and a memory 2. Memory 2 and multiple direct memory access channels (DM
At to N) 3 are connected by a common bus 4, and each D
MA is a direct memory access channel controller (D
It is connected to the CPU via MAC) 5. Data is exchanged between the CPU 1 and the memory 2, and between the memory 2 and the DMA 3. Note that the data processing order between MA3 and memory 2 is from DMA to IMAN.

For example, the CPU 1 sends a command from which address in memory 2 to which DMA 3 all the data is to be sent.
When Cs is received, the movement line between the CPU 1 and the memory 2 is interrupted, and the commanded output operation k is performed between the DMAs and the memory 20 by the DMA Ca. When the normal output ends, it is notified by DMACaK in the form of an interrupt.
pu1 is notified, and the CPU and memory 2 operations are resumed. Note that the data processing priority order of DMA5 and memory 2 is Ff, and the order is DMA1 to DMAn.

DMA5 i-j has dominion over the entire bus 4 as described above, and during data exchange between the DMAak memories 2, the CPU 1 has no choice but to wait as described above. D
In a system in which a large number of MA5 t'' units are operated, there is a problem that this wait time cannot be ignored.

(c) Object of the Invention The object of the present invention is to provide a computer system with a common bus structure in which the control of the bus by a direct memory access channel control device extends only to a limited memory address space. .

An object of the present invention is to provide an asynchronous bus control method that shortens the time during which a central processing unit cannot control the bus (wait time). A common bus connects the memory and a plurality of direct memory access channels, and the central processing unit gains control of the direct memory access channels of the bus via a direct memory access channel control device that controls the direct memory access channels. In an asynchronous bus control method that is given priority to the above, the bus and the memory are divided into a plurality of three-pronged blocks, and each of the direct memory access channels is subordinated to a part or all of the plurality of memory blocks. At the same time, the direct memory access channel is divided into prioritized blocks, and the bus control of the direct memory access channel block is limited to the control block of the memory block via the memory access channel control device. This is achieved by providing a unique asynchronous bus control method.

(e) Examples of the invention Hereinafter, embodiments of the invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the asynchronous bus control system of the present invention.

In the figure, 6 is a CPU, and 6 is a memory block (MB).

~N), 8 is the CPU 6 and each MB 7k DMACs.

9 is a direct memory access channel pro (DMAlt to DMA1 m), 10 il
: Indicates a direct memory access channel controller (DMAC).

In the present invention, the conventional single common bus 4 and memory 21r shown in FIG. 1 are divided into a plurality of blocks 4-. For example, the memory 2 has 1 to n blocks (MB1 to MBn) and n-N blocks (MBn to
MBN) memory is divided into 20 (MB) sections, and the memory is divided into 1 to n
DMAa shown in FIG. 1 is subordinated to each block MB7. ) Roughly speaking, the DMA3t is divided into DMA blocks 9 and prioritized (
DMA,t-IDMAs m,D MAt
t ~D MAt ml-DMAn, ~DMAnm
) o In addition, from DMA Pro, ri9, n DMA request lines E
REQI~n are held in parallel to DMACl0.

As described above, in DMACl0, which has n DMA request lines BREQ, ~n in parallel, when a bus control request is issued, that is, when BREQn is active as shown in FIG. memory block M
At the same time as accessing Bn (read/write operation),
A wait is placed on the CPU 6 (cannot control the bus), and event 1 (bus usage state) shown in Fig.
When the 0 bus control request that causes the event 2t shown in FIG. 3 to be forcibly interrupted, the event switching interrupt processing is performed as shown in FIG.
), when BREQn becomes inactive,
The CPU event 2 shown in FIG. 3e is returned to the event 1 as shown in FIG. CYClrn is composed of instruction fetch a, address fetch b, and data write/read C as shown in the figure, and the DMAC 10 issues an event switching interrupt at the time indicated by the arrow at address 7
Wait.

In the present invention, as described above, the event of the CPU 6 is only interrupted when there is a bus cycle CYC that accesses all MBn, and no other events in progress are affected. For example, DMA+1 to DMA+m If the bus mastership request is BREQ, CPU 6 and MBI 7
The events between are interrupted and other MB2 to MBn and CP
The event between U is being executed. In addition, DMA+1
-DMA+m is data processed according to the assigned priority order.

As described above, in the present invention, the bus mastership of DMACl0 extends only to a limited memory address space, and unlike the bus mastership of the conventional DMAC5, which does not cover the entire bus, the CPU 6 cannot dominate the bus ( Waiting time) can be shortened.

Furthermore, in FIG. 2, for example, MB, and DMA+s
~D If MAI m and events are included in one block and each block is configured to correspond to MBI ~ Mn, the DMA execution rights of each block will operate completely independently, and will continue to operate as before. If there is a DMA, other DMAs will not have to wait, and bus control of the DMA between blocks only needs to be given to the bus of the corresponding MB and CPU, while the other DMAs are
Since PU processing is performed, the delay in CPU processing is reduced.

Note that if the configuration is such that DMA is not subordinated to MBn+1 to MBN as shown in the figure, the memory block can be made unaffected by DMA, and since CPU processing is not interrupted, there is less delay in CPU processing. ) Effect of the Invention 7 - As explained in detail above, the asynchronous bus system of the present invention has the following advantages:
The memory is divided into memory blocks, direct memory access channels are subordinated to each memory block, the bus control of the direct memory access channels is limited to the bus between the corresponding memory block and the CPU, and control is extended to others. Since the direct memory access channel does not have bus control over the entire bus compared to conventional methods, the time during which the central processing unit cannot control the bus (wait) can be shortened. In a system in which all channels are operated, the effect of μ is particularly strong.

[Brief explanation of drawings]

Figure 1 is a system configuration diagram illustrating a conventional asynchronous bus control system, Figure 2 is a configuration diagram showing one embodiment of the asynchronous bus control system of the present invention, and Figure 3 is an explanation of the event switching principle. Figure 4 is an enlarged diagram of the CPU bus cycle. In Figure 4, 6 is the CPU, 7 is the memory block, 8-8 is the common bus, 9 is the direct memory access channel block, and 10 is the direct memory 0, which is an access channel control device.

Claims (1)

[Claims] A common bus connects the central processing unit, the memory allocation memory, the plurality of direct memories, and the plurality of direct memory access channels, and the control of the direct memory access channel over the bus controls the direct memory access channel. In an asynchronous bus control method in which direct memory access is given priority to the central processing unit via a channel control device, the bus and the memory are divided into a plurality of blocks, and a part of the plurality of memory blocks is configured. Alternatively, the direct memory access channels are made dependent on each of the direct memory access channels, and the direct memory access channels are divided and prioritized into blocks, and the bus control m of the paper direct memory access channel block is controlled by the memory access channel control device. An asynchronous bus control method characterized in that only the corresponding block of the memory block is controlled via the memory block.