JPS6197769A - Bus controller - Google Patents

Abstract

PURPOSE:To use effectively a bus line and to process data at a high speed by using one bus line as a common bus or as a divided bus by cutting it on its way. CONSTITUTION:As shown in the figure a switch is connected to numbers 101-103 so that a space between boards connected to the bus line can be turned on and off. When the bus line 73 is turned off through a bus control unit 5, a CPU1 can independently read and write data only in a memory 2 even while a DMAC4 is holding the bus. A part for functioning as a bus master outputs a command to the bus control unit 5 and decides that the bus line is turned off and on at which point. In this case the priority of the command outputted to the bus control unit is based on that of bus interruption, for instance.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus architecture chair for computers or computer-applied equipment.

For computers or computer-applied equipment, etc.
In order to exchange data between the central CPU and terminal devices, a path line is used to connect them. Conventionally, in data processing devices that use such a path line, one bus master is If you hold the bus,
A potential bus master is severely restricted in its operation and often has to wait for another bus master's bus hold to be released, which has the disadvantage of prolonging the processing time. Currently, the method of dealing with this drawback is to prepare multiple pass lines, but this has drawbacks such as higher costs and the possibility that the effects of bus hold cannot be sufficiently covered. Ta.

1-Drinking The present invention was made in view of the above-mentioned circumstances.
In particular, when there are two or more bus masters on one pass line, even when one bus master has to hold the bus, other bus masters can use the bus, in other words: This was done with the aim of allowing one pass line to be used either as a common bus or as a divided bus by dividing it in the middle.

In order to achieve the above object, the present invention provides a data processing system in which one bus is shared by two or more bus masters, which includes a bidirectional switch for dividing the entire bus into a plurality of sections. By turning the 9 switches ON or OFF, the entire bus can be made into a common bus, or the whole can be made into multiple independent buses, allowing multiple bus masters to use divided buses independently and simultaneously. It is characterized by this. Hereinafter, the present invention will be explained based on examples.

FIG. 1 is a block diagram for explaining one embodiment of the present invention, in which 1 is a CPU, and 2.3 is a memory.

4 is DMAC (Direct Me+*ory
Access Controller), 5 is a bus control unit, 6 is an external device, 71 to 7 are pass lines, 8 is a control line, 101 to 103
is a switch.

FIG. 2 shows the switch 10. This is a circuit diagram showing an example of ~103. In the figure, AI HA2 is a two-state driver, and its ON/OFF control is performed by τ positive. When ■ is in the H state, it is OFF and the pass line is A,
It is cut between 8.

Also, if you want to transmit data between A and 8.

The pass line is made conductive by setting OE to L' and setting T to 'H' or L' depending on the direction.

As shown in FIG.
Connect to 03 and turn on between the boards connected to the pass line.
, so that it can be turned off.

In FIG. 1, suppose that the DMAC 4 of the CPU 1 is currently holding the bus and performing DMA transfer from the memory 3 to the external device 6. Conventionally, the CPU's actions have been greatly restricted during this time. Therefore, in the present invention, the bus control unit 5 turns off the pass line 73.
By doing this, even while DMAC4 is holding the bus, C
PUI independently reads data from memory 2,
Can be WRITE. The bus master issues a command to the bus control unit 5 to turn on the pass line at which point.

Decide whether to turn it off. In this case, the priority of commands to the bus control unit is 1, for example, based on the priority of bus interrupts.

FIG. 3 is a configuration diagram showing another embodiment of the present invention.

In this embodiment, the present invention is applied to a system with a dual bus structure having two bus control units. In the figure, reference numerals 51 and 52 are bus control units, and other parts have the same functions as those in FIG. 1. are given the same reference numerals as in FIG.

As is clear from the above description, according to the present invention, data processing can be performed at high speed by effectively utilizing pass lines.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram for explaining one embodiment of the present invention, Fig. 2 is an electric circuit diagram for explaining an example of a switch used in carrying out the present invention, and Fig. 3 is an electrical circuit diagram for explaining an example of a switch used in carrying out the present invention. FIG. 3 is an overall configuration diagram showing another embodiment of the invention. 1...aptr, 2,3...memory, 4...D
M.A.C. 5+ 51 y 52... Bus control unit, 6... External device, 71-74... Pass line, 8
...Control line, 101-103...Switch. Figure 1 Figure 3

Claims (3)

[Claims] (1) In a data processing system in which one bus is shared by two or more bus masters, a bidirectional switch is provided to divide the entire bus into multiple sections, and this switch is turned on and off.
By setting it to N or OFF, the entire bus can be made into a common bus, or by making the whole into multiple independent buses, it is possible for multiple bus masters to use divided buses independently and at the same time. bus controller. (2) The bus controller according to claim (1), wherein the bidirectional switch is constituted by an electronic switch such as a MOS. (3) The bus controller according to claim (1), wherein a switch is also provided between the end points of the common bus, so that it can be configured as a loop bus.