JPS63170971U - - Google Patents
Info
- Publication number
- JPS63170971U JPS63170971U JP6244387U JP6244387U JPS63170971U JP S63170971 U JPS63170971 U JP S63170971U JP 6244387 U JP6244387 U JP 6244387U JP 6244387 U JP6244387 U JP 6244387U JP S63170971 U JPS63170971 U JP S63170971U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- circuit package
- mounting
- perspective
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
第１図は、本考案による集積回路用パツケージ
の一実施例を示す斜視図、第２図は、本考案によ
る集積回路用パツケージの一実施例を示す斜視図
、第３図は、本考案による集積回路用パツケージ
の他の実施例を示す斜視図、第４図は、本考案に
よる集積回路用パツケージの他の実施例を示す斜
視図、第５図は、従来の集積回路用パツケージを
用いたプリント配線基板を示す斜視図である。
１……集積回路用パツケージ、２……リード線
、３……リード引出し線、４……メインキヤビテ
イ、５……サブキヤビテイ、６……サブキヤビテ
イ、７……サブキヤビテイ、８……サブキヤビテ
イ、１０……ボンデイング用電極部、１１……ボ
ンデイングパツド、１２……ボンデイングワイヤ
、１３……集積回路チツプ、１４……プリント配
線配線基板、１６……プルアツプ抵抗、１７……
バイパスコンデンサ、１８……バイパスコンデン
サ、１９……プルアツプ抵抗。
FIG. 1 is a perspective view showing an embodiment of an integrated circuit package according to the present invention, FIG. 2 is a perspective view showing an embodiment of an integrated circuit package according to the present invention, and FIG. 3 is a perspective view showing an embodiment of an integrated circuit package according to the present invention. FIG. 4 is a perspective view showing another embodiment of the integrated circuit package according to the present invention, and FIG. 5 is a perspective view showing another embodiment of the integrated circuit package according to the present invention. FIG. 2 is a perspective view showing a printed wiring board. DESCRIPTION OF SYMBOLS 1... Integrated circuit package, 2... Lead wire, 3... Lead out line, 4... Main cavity, 5... Sub cavity, 6... Sub cavity, 7... Sub cavity, 8... Sub cavity, 10... ...Bonding electrode part, 11...Bonding pad, 12...Bonding wire, 13...Integrated circuit chip, 14...Printed wiring board, 16...Pull-up resistor, 17...
Bypass capacitor, 18...Bypass capacitor, 19...Pull-up resistor.
Claims (1)
ジにおいて、前記集積回路用パツケージ内に前記
集積回路チツプをマウントするメインキヤビテイ
と、デイスクリート部品をマウントするサブキヤ
ビテイを有することを特徴とする集積回路用パツ
ケージ。 An integrated circuit package for mounting an integrated circuit chip, the integrated circuit package having a main cavity for mounting the integrated circuit chip and a subcavity for mounting discrete components within the integrated circuit package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6244387U JPS63170971U (en) | 1987-04-24 | 1987-04-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6244387U JPS63170971U (en) | 1987-04-24 | 1987-04-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63170971U true JPS63170971U (en) | 1988-11-07 |
Family
ID=30896729
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6244387U Pending JPS63170971U (en) | 1987-04-24 | 1987-04-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63170971U (en) |
-
1987
- 1987-04-24 JP JP6244387U patent/JPS63170971U/ja active Pending