JPS63169118A - 雑音除去回路 - Google Patents

雑音除去回路

Info

Publication number
JPS63169118A
JPS63169118A JP62000830A JP83087A JPS63169118A JP S63169118 A JPS63169118 A JP S63169118A JP 62000830 A JP62000830 A JP 62000830A JP 83087 A JP83087 A JP 83087A JP S63169118 A JPS63169118 A JP S63169118A
Authority
JP
Japan
Prior art keywords
switch means
circuit
level
connection point
series circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62000830A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0431603B2 (enrdf_load_stackoverflow
Inventor
Kazumasa Ando
和正 安藤
Akira Wada
晃 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Priority to JP62000830A priority Critical patent/JPS63169118A/ja
Priority to US07/066,094 priority patent/US4760279A/en
Priority to DE8787109329T priority patent/DE3776209D1/de
Priority to EP87109329A priority patent/EP0251275B1/en
Publication of JPS63169118A publication Critical patent/JPS63169118A/ja
Publication of JPH0431603B2 publication Critical patent/JPH0431603B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
JP62000830A 1986-07-02 1987-01-06 雑音除去回路 Granted JPS63169118A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP62000830A JPS63169118A (ja) 1987-01-06 1987-01-06 雑音除去回路
US07/066,094 US4760279A (en) 1986-07-02 1987-06-24 Noise cancelling circuit
DE8787109329T DE3776209D1 (de) 1986-07-02 1987-06-29 Rauschunterdrueckungsschaltung.
EP87109329A EP0251275B1 (en) 1986-07-02 1987-06-29 Noise cancelling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62000830A JPS63169118A (ja) 1987-01-06 1987-01-06 雑音除去回路

Publications (2)

Publication Number Publication Date
JPS63169118A true JPS63169118A (ja) 1988-07-13
JPH0431603B2 JPH0431603B2 (enrdf_load_stackoverflow) 1992-05-27

Family

ID=11484547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62000830A Granted JPS63169118A (ja) 1986-07-02 1987-01-06 雑音除去回路

Country Status (1)

Country Link
JP (1) JPS63169118A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202111A (ja) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd 半導体集積回路の入力バッファ回路
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator
JP2009017391A (ja) * 2007-07-06 2009-01-22 Sanyo Electric Co Ltd 音声多重放送信号の信号処理装置
JP2009130441A (ja) * 2007-11-20 2009-06-11 Fujitsu Microelectronics Ltd データ保持回路

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202111A (ja) * 1989-01-30 1990-08-10 Nec Ic Microcomput Syst Ltd 半導体集積回路の入力バッファ回路
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator
JP2009017391A (ja) * 2007-07-06 2009-01-22 Sanyo Electric Co Ltd 音声多重放送信号の信号処理装置
JP2009130441A (ja) * 2007-11-20 2009-06-11 Fujitsu Microelectronics Ltd データ保持回路
US8441294B2 (en) 2007-11-20 2013-05-14 Fujitsu Semiconductor Limited Data holding circuit

Also Published As

Publication number Publication date
JPH0431603B2 (enrdf_load_stackoverflow) 1992-05-27

Similar Documents

Publication Publication Date Title
US4760279A (en) Noise cancelling circuit
US4568842A (en) D-Latch circuit using CMOS transistors
US3982138A (en) High speed-low cost, clock controlled CMOS logic implementation
GB1589414A (en) Fet driver circuits
US3976949A (en) Edge sensitive set-reset flip flop
US9762216B1 (en) Level shifter circuit using boosting circuit
JPS63131721A (ja) 高速ｃｍｏｓ駆動回路
US5963054A (en) High voltage CMOS logic circuit using low voltage transistors
JP2796644B2 (ja) 半導体論理回路装置
JPH01286618A (ja) 出力回路およびそれを用いた論理回路
JPS63300623A (ja) 半導体バツフア回路
US4570085A (en) Self booting logical AND circuit
JPH022238B2 (enrdf_load_stackoverflow)
US4420695A (en) Synchronous priority circuit
JPS63169118A (ja) 雑音除去回路
US5532634A (en) High-integration J-K flip-flop circuit
US4954730A (en) Complementary FET circuit having merged enhancement/depletion FET output
JPS6310913A (ja) 雑音除去回路
US5982198A (en) Free inverter circuit
US5182472A (en) Logic circuit with bipolar CMOS configuration
JPS63142719A (ja) ３ステ−ト付相補型ｍｏｓ集積回路
US5048016A (en) Circuit configuration for increasing the output voltage of an electronic switching stage
JPH0774620A (ja) バツフア回路
JPH0145162Y2 (enrdf_load_stackoverflow)
JPS61214817A (ja) Ｃｍｏｓ集積回路

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term