JPS63169118A - Noise elimination circuit - Google Patents

Abstract

PURPOSE:To attain a stable action of the titled circuit without increasing consumption current by making the turning on/off state of the first and second switching means of a first series circuit and that of the third and the fourth switch means of a second series circuit opposite to each other against a signal of same level, and obtaining an output from a connecting point between the first and the second series circuits. CONSTITUTION:The first and the fourth switch means Q1, Q2 switch complementally with each other and the second and the third switch means Q3, Q4 switch also complementally with each other, and the output is obtained from the connecting point between the second switch means Q3 and the third switch means Q4. By making use of the fact that an input signal subjected to a delay means 19 is delayed for a prescribed time from the shifting of input signal, an output terminal is set in a high-impedance status by using the first through fourth switch means Q1-Q4 at a time when noise is inputted, and in such a way, an immediately preceding output data is held. As a result, a stable action of the titled circuit is obtained without enhancing the consumption current.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a noise removal circuit for removing noise contained in a signal.

(Prior Art) Conventionally, a circuit as shown in FIG. 6 has been used as a noise removal circuit capable of dealing with noise in both positive and negative directions. This circuit consists of two delay circuits 11x, 112 and an AND gate 12! , and an OR gate 122, the first stage removes noise in the positive direction, and then the noise in the negative direction is removed in the second stage. However, the noise removal circuit having such a configuration has the disadvantage that the configuration is complicated, the number of elements is large, and the area occupied by the pattern is also increased.

As a noise removal circuit capable of eliminating such drawbacks, a circuit as shown in FIG. 7 has been proposed in Japanese Patent Application No. 155708/1982. This circuit consists of an input signal ei and this signal e
When i and the signal ea delayed by the delay circuit 19 are at the same level, an output signal eo is obtained from the output terminal 20, and when they do not match, the potential at the output terminal 20 is held dynamically.
This removes noise in both positive and negative directions for a time shorter than the delay time of the delay circuit 19.

However, this circuit risks malfunctioning under certain conditions. In other words, when the load capacitance connected to the output terminal 20 is smaller than the capacitance of the connection point (intermediate drain) N1 between MOS transistors Q1 and 03, or the capacitance of the connection point (intermediate drain) N2 between Mo8 transistors Q4 and 02. In this case, the logic level may be reversed when dynamically holding the output, resulting in poor circuit stability.

This will be explained in detail below with reference to the timing chart of FIG. When the input signal ei changes from the ground level ("L" level) to the voltage level ("H" level) at time 10, MOS transistor Q1 turns off and Q2 turns on. From this time to, delay circuit 1
The signal ea becomes "H" level after a delay time Δt of 9, and the MOS transistor Q3 is turned off and the MOS transistor Q4 is turned on. As a result, the output signal eo becomes "L" level. In this state, when low-level noise is superimposed on the input signal 61 at time t1, the MOS transistor Q1 is turned on and the MOS transistor Q2 is turned off.

At this time, MOS transistors Q3 and Q4 are connected to the delay circuit 1.
Since the previous on/off state is maintained until time t3 when the output ea of No. 9 is inverted, there is no DC bus from the power supply VCC to the ground point, and the "L" level of the previous output is dynamically maintained. Between times t1 and t2, the connection point N1 between MOS transistors Q1 and 03 is connected to the MOS transistor Q
1 is turned on, it is charged to the power supply voltage level.

When the level of input signal ei returns to "H" level at time t2, MOS transistors Ql and Q3 are turned off.
Q2 and Q4 are turned on, and the output signal eo is low
level. After this t3. During t4, the output signal eO must be dynamically held at the "L" level, but since the MoS transistor Q3 is in the on state, the charge dynamically held at the connection point N1 is transferred to the output terminal 20. The potential at this terminal 20 rises. At this time, if the capacitance of the connection point N1 is larger than the load capacitance connected to the output terminal 20, the potential of the output signal eo exceeds 1/2 of the power supply voltage. Normally, the circuit threshold of the 0M08 circuit is set to 1/2 of the power supply voltage, so if the potential of the output signal eo exceeds V CC / 2, the output signal eO
The logic level changes from "L" level to "H level".

A similar phenomenon also occurs when noise at the power supply voltage level is superimposed on the signal e1 when the input signal ei is at the "L" level. That is, the input signal ei becomes “L” at time t5.
” level to “H” level, MOS transistor Q1 turns off and Q2 turns on (at this time, M
(OS transistor Q3 is in an on state and Q4 is in an off state), and the output terminal 20 is in a high impedance state and the "H" level is dynamically maintained.

The connection point N2 between these ff11M0S transistors Q4 and Q2 is discharged to the ground potential.

Then, when the input signal ei returns to the "L" level at time t6, the MOS transistors Ql and Q3 are turned on.
Q2 and Q4 are turned off, and the output signal eO is “H”
level. After this t7. During t8, the output signal eO must be dynamically held at the "H" level, but since the MOS transistor Q4 is in the on state, the charge that should be held on the output terminal 20 side flows into the connection point N2. The potential on the output terminal 20 side decreases. At this time,
If the capacitance of the connection point N2 is larger than the load capacitance connected to the output terminal 20, the potential of the output signal eO becomes 1/2 of the power supply voltage.
becomes lower. Therefore, the logic level of the output signal eO is inverted from the "H" level to the "L" level.

As described above, the circuit shown in FIG. 7 may malfunction if the capacitance at the connection point N1-N2 is larger than the load capacitance connected to the output terminal 20, and has the disadvantage of poor stability.

In order to eliminate such drawbacks, a latch circuit technique may be provided at the output terminal 20 as shown in FIG. However, if a latch circuit is provided, the output signal eO of the output terminal 20
When inverting the voltage, the voltage is supplied from the power supply of the inverter 21 to the ground point via the P-channel MOS transistor of the inverter 21 and the MOS transistors Q4 and Q2 of the noise elimination circuit, or from the power supply Vcc of the noise elimination circuit to the MoS transistor Ql.

A temporary DC bus is generated at the ground point via Q3 and the N-channel MOS transistor of the inverter 21, causing a new problem in that a through current flows and current consumption increases.

(Problems to be Solved by the Invention) As mentioned above, in conventional noise removal circuits, when the potential at the output terminal should be dynamically maintained, charge moves, and there is a risk of malfunction under certain conditions. However, attempts to prevent this have the disadvantage of increasing current consumption.

This invention was made in view of the above circumstances,
The purpose is to provide a noise removal circuit that can provide stable operation without increasing current consumption.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides a first switch, one of which is controlled on/off by an input signal. A first series circuit is provided in which second switch means are connected in series, one end of which is connected to the first potential supply source, and one end of the series circuit is connected to the above-mentioned input source between the other end of the series circuit and the second potential supply source. The third one is controlled on/off by a signal. A second series circuit configured by connecting fourth switch means in series is provided, and the input signal is delayed by the delay means to delay the input signal from the first switch means. The other switch means constituting the second series circuit is controlled on/off, respectively, and the first switch means is controlled to turn on/off. The connection point of the second series circuit and the connection point of the first series circuit. The connection point with the second switch means is on/off controlled by the same signal as one of the switch means constituting the first series circuit, and the switch means is turned on/off in response to a signal of the same level. A fifth switch means whose state is reversed is connected, and the first switch means is connected. The connection point of the second series circuit and the third. Between the connection points with the fourth switch means, on/off control is performed using the same signal as one of the switch means constituting the second series circuit, and the switch means is turned on/off in response to a signal at the same level. A sixth switch means whose state is reversed is connected to the first switch means of the first series circuit.
3. of the second switch means and the second series circuit. The fourth switch means has an on/off state reversed for signals of the same level, and obtains an output from a connection point between the first series circuit and the second series circuit.

(Function) In the above configuration, the first. The fourth switch means performs a complementary switching operation, and the fourth switch means performs a complementary switching operation, and the fourth switch means performs a switching operation complementary to the second switch means. The third switch means also performs a complementary switching operation, and the second
The output is obtained from the connection point between the switch means and the third switch means, and the signal passing through the delay means is delayed by a predetermined time with respect to a change in the input signal.
When noise is input, the output end is set to a high impedance state using the first to fourth switch means, thereby holding the immediately previous output data. When the first switch means is in the OFF state, the output terminal and the first switch means are connected to each other. The connection point of the second switch means is electrically connected to the connection point of the third switch means by the fifth switch means, and when the fourth switch means is in the off state, the output terminal and the third switch means are electrically connected to each other. The connection point of the fourth switch means is electrically connected to the connection point of the fourth switch means by the sixth switch means. By doing this, 1.
between the connection point and the output end of the second switch means; and the third switch means.
Since the movement of charge between the connection point of the fourth switch means and the output terminal can be prevented, the load capacitance connected to the output terminal and the first switch means can be prevented from moving.
The capacitance at the connection point of the second switch means, the load capacitance connected to the output terminal, and the third. Stable operation can be obtained regardless of the magnitude relationship with the capacitance of the connection point of the fourth switch means.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In FIG. 1, the same components as in FIG. 7 are given the same reference numerals, and the input terminal 18 to which the input signal ei is supplied has one end connected to the power supply VCC (first potential supply source). P-channel type MOS transistor Ql
(the first switch means), and one end is the ground point (the second
The gates of the N-channel MOS transistors Q2 (fourth switch means) connected to the potential supply source (potential supply source) are respectively connected, and the input end of the delay circuit 19 is also connected. A P-channel type MOS transistor Q3 (second switch means) and an N-channel type MOS transistor Q4 (third switch means) are connected in series between the other ends of the MOS transistors Ql and Q2. The output end of the delay circuit 19 is connected to the gates of Q3°Q4. In addition, the above MO
Connection point between S transistors Q1 and 03 (intermediate drain)
An N-channel MoS transistor (fifth switch means) Q5 is connected between the connection point between N1 and MOS transistors Q3 and 04, and the input terminal 18 is connected to the gate of this MOS transistor Q5.

On the other hand, the connection point between the MOS transistors Q4 and 02 (
Between the connection point of intermediate drain) N2 and MOS transistors Q3 and 04, there is a P-channel MOS transistor (
A sixth switch means) Q6 is connected, and the input terminal 18 is connected to the gate of this MOS transistor Q6. The output signal eo is obtained from the output terminal 20 connected to the connection point between the MOS transistors Q3 and 04.

Next, the operation of the above configuration will be explained with reference to the timing chart of FIG. 2. First, input signal e1
is at the power supply voltage level (“H” level), the ground level (
The operation when “L” level noise is superimposed (time tl) will be described.

In this state, Mo3 transistors Q1, Q4
.

Q6 is on, MoS transistor Q2. Q3゜Q5
is in the off state. In this state, the output terminal 20 is
Since it lacks a DC path to v cc and the ground point, L +
t level is maintained dynamically. Also, the connection point N
1 is charged to the power supply voltage because the MOS transistor Q1 is in the on state, but the MoS transistor Q1 is charged to the power supply voltage.
3. Since both Q5 and Q5 are in the off state, the output terminal 20
The L” level can be dynamically maintained on the side.

At time t2, the input signal ei returns to "H" level,
MOS transistor 5: Z registers Q1, Q3, and Q6 are in the off state, Q2, Q4, and Q5 are in the on state, and the output signal e
O becomes "L" level. At this time, the connection point N1 is a MOS
Since transistor Q5 is in the on state, the MOS
Transistors Q5, Q4.

It is discharged to the ground level through the path of Q2.

At the next time t3, when the signal ea, which is the input signal e1 delayed by the delay circuit 19, goes to "L" level, the MOS transistors Q1, Q4, and Q6 are turned off, and Q2, Q3, and Q5 are turned off.
turns on. The output terminal 20 then lacks a DC bus to power and ground, and is held dynamically at 11 lbs. At this time, since the MoS transistor Q3 is in the on state, the output terminal 20 and the connection point N1 are electrically connected, but at time t2. Since the connection point N1 is discharged to the ground potential due to the on state of the MoS transistor Q5 during t3, the connection point N1 and the output terminal 20 are at the same potential, and no charge transfer occurs and the output terminal 20 "
L” level can be maintained dynamically.

When the output signal ea of the delay circuit 19 returns to the "H" level at time t4, the MOS transistors Q1, Q3, Q6
is turned off, Q2, Q4, and Q5 are turned on, and the output signal eo goes to "L" level.

In this way, when the input signal ei is at the power supply voltage level, even if ground level noise is superimposed, this noise can be removed, and the logic level can be changed by the movement of charge between the connection point N1 and the output terminal 20. Reversal can be prevented.

Next, when the input signal ei is at the ground level (L” level),
The operation when noise at the power supply voltage level (“H” level) is superimposed will be described. At time t5, input signal ei
When becomes “H” level, MOS transistor Q1,
Q4 and Q6 are in the off state, and Q2, Q3 and Q5 are in the on state. Therefore, the output terminal 20 is dynamically held at the "H" level since it lacks a DC bus to the power source and ground. Here, the connection point N2 is the MOS transistor Q2
It is discharged to ground potential due to the on state of
Since the MoS transistors Q4 and Q6 are in the off state, the potential of the output terminal 20 can be held dynamically.

The input signal ei returns to the "L" level at time t6,
The MOS transistors Q1, Q3, Q6 I, I, Q2, Q4, and Q5 are turned off, and the output signal eO becomes "H" level. At this time, the connection point N2 is M
When the oS transistor Q6 is turned on, it is charged to the power supply voltage level through the MOS transistors Ql, Q3, and Q6 in sequence.

At time t7, when the output signal ea of the delay circuit 19 becomes H'' level, the MoS transistors Ql and Q4.

Q6 is turned on, and Q2, Q3, and Q5 are turned off. As a result, the H" level is dynamically maintained at the output terminal 20. At this time, since the MoS transistor Q4 is turned on, the connection point N2 and the output terminal 20 are electrically connected, but between times t6 and t7, M.O.S.
Since it is charged to the power supply voltage by the transistor Q5 and the connection point N2 is at the same potential as the output terminal 20, no charge movement occurs, and the "H level" is dynamically maintained at the output terminal 20.

At the next time t8, the output signal ea of the delay circuit 19 becomes "L".
When the level returns, MOS transistors Q1 and Q3
, Q6 are in the on state, Q2, Q4, and Q5 are in the off state, and the output signal eO becomes "H level".

As mentioned above, when the input signal ei is at the ground level, even if noise at the power supply voltage level is superimposed, this noise can be removed, and the logic level can be changed by the movement of charge between the connection point N2 and the output terminal 20. There is no reversal.

Therefore, according to such a configuration, stable operation is obtained regardless of the capacitance ratio between the capacitance of the connection point N1°N2 and the load capacitance connected to the output terminal 20, and reliability is high. Furthermore, since it is composed of six MOS transistors except for the delay circuit 19, the pattern area can be reduced compared to the circuit shown in FIG. The current consumption can be reduced compared to the previous circuit.

FIG. 3 shows another embodiment of the present invention.
In the circuit shown in the figure, MOS transistor Q1. Q2,
Supply the input signal ei to the gates of Q5 and Q6, and
, the output signal ea of the delay circuit 19 is supplied to the gate of MOS transistor Q4 to control conduction.
, Q4, and input signal ei to the gates of Ql, Q2.
, Q5, and Q6 are configured to supply the output signal ea of the delay circuit 19 to the gates thereof to control conduction. In FIG. 3, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. Even in this configuration, basically the same operation as the circuit shown in FIG. 1 is performed and the same effect can be obtained.

4 and 5 respectively show still other embodiments of the present invention. In the circuit of FIG. 4, the input signal ei is applied to the gates of MOS transistors Q1, Q4, and Q5.
is configured to control conduction by supplying the output signal ea of the delay circuit 19 to the gates 1- of Q2, Q3, and Q6, respectively, and in the circuit shown in FIG.
3, input signal e1 to the gate of Q6, Ql, Q4
, Q5 are configured to supply the output signal ea of the delay circuit 19 to the gates of the transistors Q5 to control conduction. Even with such a configuration, the same operation as the circuits shown in FIGS. 1 and 3 can be performed and the same effects can be obtained.

[Effect of the Invention 1] As explained above, according to the present invention, it is possible to provide a noise removal circuit that can obtain stable operation without increasing current consumption.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a noise removal circuit according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1, and FIGS. A circuit diagram for explaining another embodiment of
6, 7, and 9 are circuit diagrams for explaining conventional noise removal circuits, respectively, and FIG. 8 is the circuit diagram for explaining the conventional noise removal circuit.
3 is a timing chart for explaining the operation of the circuit shown in the figure. ycc...power supply (first potential supply source), el...input signal, Q1-Q6...MOS transistor (switch means), 19...delay circuit (M delay means), eo
...output signal, ea...output signal of the delay circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3?

Claims (2)

[Claims] (1) A first series circuit configured by connecting first and second switch means in series, one of which is controlled on/off by an input signal, and one end of which is connected to a first potential supply source; are configured by connecting in series third and fourth switch means whose on/off is controlled by the input signal, and a second switch means connected between the other end of the first series circuit and a second potential supply source. a series circuit, a delay means for delaying the input signal and controlling on/off of the other switch means constituting the first and second series circuits, and the first and second series circuits; and the connection point of the first and second switch means, and is controlled on/off by the same signal as one of the switch means constituting the first series circuit;
The second switch means is a fifth switch means whose on/off state is reversed for signals of the same level, and the first switch means.
, connected between the connection point of the second series circuit and the connection point of the third and fourth switch means, and controlled on/off by the same signal as one of the switch means constituting the second series circuit. and a sixth switch means whose on/off state is reversed for signals of the same level as the third and fourth switch means, and the first and second switch means of the first series circuit are
The switch means and the third and fourth switch means of the second series circuit have opposite on/off states for signals of the same level, and the connection between the first series circuit and the second series circuit is established. A noise removal circuit characterized by obtaining an output from a point. (2) The first, second and sixth switch means each include a first conductivity type field effect transistor, and the third, fourth and fifth switch means each include a second conductivity type field effect transistor.
2. The noise removal circuit according to claim 1, comprising a conductive field effect transistor.