JPS63167753U - - Google Patents
Info
- Publication number
- JPS63167753U JPS63167753U JP5931287U JP5931287U JPS63167753U JP S63167753 U JPS63167753 U JP S63167753U JP 5931287 U JP5931287 U JP 5931287U JP 5931287 U JP5931287 U JP 5931287U JP S63167753 U JPS63167753 U JP S63167753U
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- grounding
- pad
- power supply
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案の一実施例を説明するためのＧ
ａＡｓＭＥＳＦＥＴを用いた集積回路の平面図で
、第１図ａはチツプ全体の概略図、第１図ｂは同
図ａ中のＡで示した部分の部分拡大図である。
１……チツプ、２１……接地配線パツド、２２
……第一ソース電源パツド、２３……第二ソース
電源パツド、２４……電圧モニタパツド、３１…
…接地母配線、３２……第一ソース電源母配線、
３３……第二ソース電源母配線、３４……電圧モ
ニタ用配線、４１，４２，４３，４４……ＭＥＳ
ＦＥＴ、５１……シヨツトキ障壁型ダイオード。
FIG. 1 is a diagram for explaining one embodiment of the present invention.
FIG. 1A is a schematic diagram of the entire chip, and FIG. 1B is a partially enlarged view of the portion indicated by A in FIG. 1A. 1... Chip, 21... Ground wiring pad, 22
...First source power pad, 23...Second source power pad, 24...Voltage monitor pad, 31...
...Ground bus wiring, 32...First source power supply wiring,
33...Second source power supply bus wiring, 34...Voltage monitor wiring, 41, 42, 43, 44...MES
FET, 51...Shotki barrier diode.
Claims (1)
て給電が行なわれ、又は接地パツドより接地母配
線および接地配線を経て接地が行なわれた半導体
集積回路に於て、該電源用配線系又は接地用配線
系の少なくとも一方の配線系の配線電位をモニタ
するための配線の一端が該配線系の配線に接続さ
れ、モニタするための配線の他端が電圧モニタパ
ツドに引き出されて成ることを特徴とする半導体
集積回路。 In a semiconductor integrated circuit where power is supplied from a power pad through a power supply wiring and power supply wiring, or where grounding is performed from a grounding pad through a grounding wiring and a grounding wiring, the power supply wiring system or the grounding wiring system A semiconductor integrated circuit characterized in that one end of a wiring for monitoring the wiring potential of at least one wiring system is connected to the wiring of the wiring system, and the other end of the wiring for monitoring is drawn out to a voltage monitor pad. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5931287U JPS63167753U (en) | 1987-04-21 | 1987-04-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5931287U JPS63167753U (en) | 1987-04-21 | 1987-04-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63167753U true JPS63167753U (en) | 1988-11-01 |
Family
ID=30890687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5931287U Pending JPS63167753U (en) | 1987-04-21 | 1987-04-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63167753U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126932A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Analysis of defect |
-
1987
- 1987-04-21 JP JP5931287U patent/JPS63167753U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56126932A (en) * | 1980-03-12 | 1981-10-05 | Hitachi Ltd | Analysis of defect |