JPH0262741U - - Google Patents

Info

Publication number
JPH0262741U
JPH0262741U JP14131788U JP14131788U JPH0262741U JP H0262741 U JPH0262741 U JP H0262741U JP 14131788 U JP14131788 U JP 14131788U JP 14131788 U JP14131788 U JP 14131788U JP H0262741 U JPH0262741 U JP H0262741U
Authority
JP
Japan
Prior art keywords
constant voltage
integrated circuit
signal pad
circuit device
current source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14131788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14131788U priority Critical patent/JPH0262741U/ja
Publication of JPH0262741U publication Critical patent/JPH0262741U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のチツプ概略平面図、第2図は
、従来のチツプ概略平面図、第3図は、ECL回
路構成図である。 1,2,3,7,8,9,10,11,16,
17,18,22,23,24,25,26……
信号パツド、4,6,19,21……電源パツド
、5,20……電源配線、12,27……定電流
源用定電圧配線、13,28……定電流源用定電
圧発生回路、14,15……定電流源用定電圧取
り出し配線、G1……基準ベース電圧発生回路、
G2……定電流源用定電圧発生回路、Q1,Q2
,Q3……回路構成トランジスタ、R1,R2…
…コレクタ抵抗、ICS……定電流源。
FIG. 1 is a schematic plan view of a chip according to the present invention, FIG. 2 is a schematic plan view of a conventional chip, and FIG. 3 is an ECL circuit configuration diagram. 1, 2, 3, 7, 8, 9, 10, 11, 16,
17, 18, 22, 23, 24, 25, 26...
Signal pad, 4, 6, 19, 21... Power supply pad, 5, 20... Power supply wiring, 12, 27... Constant voltage wiring for constant current source, 13, 28... Constant voltage generation circuit for constant current source, 14, 15... Constant voltage extraction wiring for constant current source, G1... Reference base voltage generation circuit,
G2... Constant voltage generation circuit for constant current source, Q1, Q2
, Q3...Circuit configuration transistor, R1, R2...
...Collector resistance, ICS... Constant current source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 集積回路装置内で発生されている定電圧を信号
パツドに取り出す接続配線により任意の信号パツ
ドに出力することを特徴とする集積回路装置。
An integrated circuit device characterized in that a constant voltage generated within the integrated circuit device is output to an arbitrary signal pad through connection wiring that takes out the constant voltage to the signal pad.
JP14131788U 1988-10-28 1988-10-28 Pending JPH0262741U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14131788U JPH0262741U (en) 1988-10-28 1988-10-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14131788U JPH0262741U (en) 1988-10-28 1988-10-28

Publications (1)

Publication Number Publication Date
JPH0262741U true JPH0262741U (en) 1990-05-10

Family

ID=31406271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14131788U Pending JPH0262741U (en) 1988-10-28 1988-10-28

Country Status (1)

Country Link
JP (1) JPH0262741U (en)

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