JPS6316322U - - Google Patents

Description

[Brief explanation of the drawing]

1 to 4 are for explaining one embodiment of the present invention, of which FIG. 1 is a block diagram of a clock circuit of an image editing processing device, and FIG. 2 is a main part of the image editing processing device. 3 is a block diagram specifically showing the clock circuit, FIG. 4 is various timing diagrams for explaining the operation of the image editing processing device using this clock circuit, and FIG. 5 is the image processing device. FIG. 2 is a block diagram showing the overall configuration of the device. 1... Host processor, 4... Image editing processing device, 12... Oscillator, 13... Clock, 1
4...Master clock generation circuit, 15...Slave clock generation circuit, 16...Master clock, 17...Slave clock, 18...Phase detection circuit, 21...Power-on reset circuit.

Claims (1)

[Scope of utility model registration request] An apparatus for performing image editing processing under microprogram control, comprising: a master clock generation circuit for generating a master clock as a constantly operating clock; a phase detection circuit for detecting the phase of the master clock; A slave clock generating circuit for generating a slave clock as a clock whose interval can be arbitrarily controlled, synchronizing the phase with the master clock at the start of operation of the slave clock, and microprogram control operation. 1. A clock circuit for an image editing processing device, comprising a control circuit for controlling the operation and stop of a slave clock so that the operation is stopped at a desired phase that does not affect the slave clock.