JPS58101266U - digital electronic controller - Google Patents

digital electronic controller

Info

Publication number
JPS58101266U
JPS58101266U JP19625281U JP19625281U JPS58101266U JP S58101266 U JPS58101266 U JP S58101266U JP 19625281 U JP19625281 U JP 19625281U JP 19625281 U JP19625281 U JP 19625281U JP S58101266 U JPS58101266 U JP S58101266U
Authority
JP
Japan
Prior art keywords
block
digital electronic
cpu block
control device
electronic control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19625281U
Other languages
Japanese (ja)
Inventor
利雄 高橋
石毛　康夫
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP19625281U priority Critical patent/JPS58101266U/en
Publication of JPS58101266U publication Critical patent/JPS58101266U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案に係るデジタル電子制御装置の８一実施
例を示すブロック図、第２図は第１図の動作説明のため
に示すタイミング図である。 １・・・ＣＰＵブロック、２・・・メモリブロック、３
１〜３ｎ・・・機能ブロック、４・・・電源ブロック、
５・・・電源制御ブロック、７・・・スイッチ回路。FIG. 1 is a block diagram showing an 81st embodiment of a digital electronic control device according to the present invention, and FIG. 2 is a timing diagram shown to explain the operation of FIG. 1. 1...CPU block, 2...Memory block, 3
1 to 3n...Function block, 4...Power supply block,
5...Power control block, 7...Switch circuit.

Claims (2)

【実用新案登録請求の範囲】[Scope of utility model registration request] （１）デジタル中央処理装置を用いたＣＰＵブロックを
内部の複数の機能ブロックの１つとして有するデジタル
電子制御装置において、上記ＣＰＵブロックの稼動期間
を装置の制御サイクルに比べて短かくなるように設定し
てなるデジタル電子制御装置。(1) In a digital electronic control device having a CPU block using a digital central processing unit as one of the plurality of internal functional blocks, the operating period of the CPU block is set to be shorter than the control cycle of the device. A digital electronic control device. （２）前記ＣＰＵブロック以外の内部機能ブロックであ
る電源制御ブロックによりＣＰＵブロックの電源起動を
制御し、ＣＰＵブロックの内蔵するプログラムにしたが
ってＣＰＵブロックから前記電源制御ブロックに停止信
号を出力して　゛ＣＰＵブ皐ツクベック源供給を遮断さ
せるようにしてなることを特徴とする実用新案登録請求
の範囲第１項記載のデジタル電子制御装置。(2) A power supply control block, which is an internal functional block other than the CPU block, controls power activation of the CPU block, and outputs a stop signal from the CPU block to the power supply control block according to the program built into the CPU block. 2. The digital electronic control device according to claim 1, wherein the digital electronic control device is configured to cut off the supply of a power source.
JP19625281U 1981-12-26 1981-12-26 digital electronic controller Pending JPS58101266U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19625281U JPS58101266U (en) 1981-12-26 1981-12-26 digital electronic controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19625281U JPS58101266U (en) 1981-12-26 1981-12-26 digital electronic controller

Publications (1)

Publication Number Publication Date
JPS58101266U true JPS58101266U (en) 1983-07-09

Family

ID=30109499

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19625281U Pending JPS58101266U (en) 1981-12-26 1981-12-26 digital electronic controller

Country Status (1)

Country Link
JP (1) JPS58101266U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02272615A (en) * 1989-04-14 1990-11-07 Toshiba Corp Digital electronic controller

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4725942U (en) * 1971-04-20 1972-11-24
JPS5383428A (en) * 1976-12-07 1978-07-22 Fujitsu Ltd Automatic power throw-in system for data transmission system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4725942U (en) * 1971-04-20 1972-11-24
JPS5383428A (en) * 1976-12-07 1978-07-22 Fujitsu Ltd Automatic power throw-in system for data transmission system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02272615A (en) * 1989-04-14 1990-11-07 Toshiba Corp Digital electronic controller

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