JPS61196346U - - Google Patents

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Publication number
JPS61196346U
JPS61196346U JP8002785U JP8002785U JPS61196346U JP S61196346 U JPS61196346 U JP S61196346U JP 8002785 U JP8002785 U JP 8002785U JP 8002785 U JP8002785 U JP 8002785U JP S61196346 U JPS61196346 U JP S61196346U
Authority
JP
Japan
Prior art keywords
control signal
computer system
program
detection device
abnormality detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8002785U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP8002785U priority Critical patent/JPS61196346U/ja
Publication of JPS61196346U publication Critical patent/JPS61196346U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例のブロツク図、第2
図乃至第4図は本考案の一実施例の動作を説明す
るためのタイミングチヤートである。 1……カウンタ、2……クロツク発生回路、3
……アンドゲート、4……オアゲート。
Fig. 1 is a block diagram of an embodiment of the present invention;
4 through 4 are timing charts for explaining the operation of one embodiment of the present invention. 1...Counter, 2...Clock generation circuit, 3
...and gate, 4...or gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] プログラム制御方式のコンピユータシステムの
異常検出装置において、プログラムの実行時に所
定時間毎に前記プログラムにより制御信号を発生
する制御信号発生手段と、前記制御信号が、前記
所定時間を経過する前に発生されることと、前記
所定時間を経過しても発生されないことを検出す
る制御信号検出手段を設けたことを特徴とするコ
ンピユータシステムの異常検出装置。
In an abnormality detection device for a computer system using a program control method, a control signal generating means generates a control signal according to the program at predetermined time intervals when the program is executed, and the control signal is generated before the predetermined time elapses. An abnormality detection device for a computer system, characterized in that the abnormality detection device for a computer system is further provided with a control signal detection means for detecting that the abnormality does not occur even after the predetermined period of time has elapsed.
JP8002785U 1985-05-30 1985-05-30 Pending JPS61196346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8002785U JPS61196346U (en) 1985-05-30 1985-05-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8002785U JPS61196346U (en) 1985-05-30 1985-05-30

Publications (1)

Publication Number Publication Date
JPS61196346U true JPS61196346U (en) 1986-12-08

Family

ID=30625493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8002785U Pending JPS61196346U (en) 1985-05-30 1985-05-30

Country Status (1)

Country Link
JP (1) JPS61196346U (en)

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