JPS63158894A - Manufacture of ceramic wiring circuit board - Google Patents
Manufacture of ceramic wiring circuit boardInfo
- Publication number
- JPS63158894A JPS63158894A JP30678986A JP30678986A JPS63158894A JP S63158894 A JPS63158894 A JP S63158894A JP 30678986 A JP30678986 A JP 30678986A JP 30678986 A JP30678986 A JP 30678986A JP S63158894 A JPS63158894 A JP S63158894A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- circuit board
- plating
- glass
- wiring circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims description 62
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims description 49
- 239000011521 glass Substances 0.000 claims description 38
- 238000007747 plating Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 230000004913 activation Effects 0.000 claims description 11
- 239000000654 additive Substances 0.000 claims description 7
- 230000000996 additive effect Effects 0.000 claims description 7
- 238000007772 electroless plating Methods 0.000 claims description 7
- 238000010304 firing Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 19
- 238000001994 activation Methods 0.000 description 10
- 238000007789 sealing Methods 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000004020 conductor Substances 0.000 description 7
- 238000007796 conventional method Methods 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 239000005394 sealing glass Substances 0.000 description 5
- 230000003746 surface roughness Effects 0.000 description 5
- 239000003054 catalyst Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 239000012298 atmosphere Substances 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 239000011368 organic material Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- GNTDGMZSJNCJKK-UHFFFAOYSA-N divanadium pentaoxide Chemical compound O=[V](=O)O[V](=O)=O GNTDGMZSJNCJKK-UHFFFAOYSA-N 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000001235 sensitizing effect Effects 0.000 description 2
- -1 steatite Chemical compound 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 1
- 150000001339 alkali metal compounds Chemical class 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910021538 borax Inorganic materials 0.000 description 1
- 229910052878 cordierite Inorganic materials 0.000 description 1
- JSKIRARMQDRGJZ-UHFFFAOYSA-N dimagnesium dioxido-bis[(1-oxido-3-oxo-2,4,6,8,9-pentaoxa-1,3-disila-5,7-dialuminabicyclo[3.3.1]nonan-7-yl)oxy]silane Chemical compound [Mg++].[Mg++].[O-][Si]([O-])(O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2)O[Al]1O[Al]2O[Si](=O)O[Si]([O-])(O1)O2 JSKIRARMQDRGJZ-UHFFFAOYSA-N 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052574 oxide ceramic Inorganic materials 0.000 description 1
- 239000011224 oxide ceramic Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000004328 sodium tetraborate Substances 0.000 description 1
- 235000010339 sodium tetraborate Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［技術分野］
この発明は、電子基材として使用されるセラミックス配
線回路板に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a ceramic wiring circuit board used as an electronic substrate.
［背景技術］
セラミックス配線回路板を作製するにあたり、最近、ス
ルーホール部のメタライジングの信鯨性が高（、金属部
の厚みの制御が容易であるという利点から、めっきによ
る回路形成法が注目されている。中でも、低コスト化の
要望に対しては１、フルアディティブ法が有効であると
して注目されている。従来、この方式でセラミックス配
線回路板を作成するには、たとえば第５図に示すような
工程で実施されていた。[Background technology] Recently, when producing ceramic wiring circuit boards, the method of forming circuits by plating has been attracting attention due to the high reliability of metallizing of through-hole parts (and the easy control of the thickness of the metal parts). Among them, the full additive method is attracting attention as being effective in meeting the demand for cost reduction. Conventionally, in order to create a ceramic wiring circuit board using this method, for example, the method shown in Fig. 5 is The process was carried out as shown.
すなわち、先ずセラミックスと、後に処理するめっきと
の密着性を強固なものとするために、その表面を化学的
に粗面化したセラミックス基板を用意する。つぎにその
表面に、金属を受容するようにパラジウム（Ｐｄ）など
の核付は処理を施した後、めっきレジストとして感光性
の有機材料を使用して、露光現象により所定のパターニ
ングを行う。That is, first, a ceramic substrate whose surface is chemically roughened is prepared in order to strengthen the adhesion between the ceramic and the plating that will be treated later. Next, the surface is treated with a nucleus such as palladium (Pd) to accept metal, and then a predetermined patterning is performed by exposure using a photosensitive organic material as a plating resist.
つぎに、めっきレジスト形成部以外のＰｄ等の核付は処
理を施されたセラミックス部に無電解めっきを施し、必
要ならば、さらに電解めっきを施し回路形成した後、め
っきレジストを除去して所定の回路板を得るのである。Next, to remove nuclei such as Pd in areas other than the plating resist forming area, electroless plating is applied to the treated ceramic area, and if necessary, after further electrolytic plating is applied to form a circuit, the plating resist is removed and the predetermined area is formed. circuit board.
このように従来法では、パターニングから、回路保護工
程に至るまでの工程数が多く、低コスト化のために工程
数の削減が望まれていた。As described above, the conventional method requires a large number of steps from patterning to a circuit protection step, and it has been desired to reduce the number of steps in order to reduce costs.
［発明の目的］
この発明は、以上のような現状に鑑みてなされたもので
あり、セラミックス配線回路板をめっきによるアディテ
ィブ法で製造するに当たり、バターニングから回路保護
工程に至るまでの工程数を削減し、低コストで製造でき
るセラミックス配線回路板の製造方法を提供することを
目的としている。[Purpose of the Invention] This invention was made in view of the above-mentioned current situation, and it is possible to reduce the number of steps from buttering to the circuit protection process when manufacturing ceramic wiring circuit boards by an additive method using plating. The purpose of the present invention is to provide a method for manufacturing a ceramic printed circuit board that can be manufactured at low cost.
［発明の開示］
この発明は、回路部をめっきによるアディティブ法によ
って形成するセラミックス配線回路板の製法において、
粗面化されたセラミックス基板を用意し、つぎにセラミ
ックス基板面に金属が受容されるように活性化処理を施
した後、回路部となる部分以外の部分にめっきレジスト
としてガラスペーストを付けて焼成するか、または用意
されたセラミックス基板の回路部となる部分以外の部分
に、先ずめっきレジストとしてガラスペーストを付けて
焼成した後、金属が受容されるように活性化処理を施し
、しかる後無電解めっきによって回路部を形成し、必要
ならば、さらに電解めっきを施すことを特徴とするセラ
ミックス配線回路板の製法を提供するものである。[Disclosure of the Invention] The present invention provides a method for manufacturing a ceramic wiring circuit board in which a circuit portion is formed by an additive method using plating.
A roughened ceramic substrate is prepared, and then activated to allow metal to be received on the ceramic substrate surface. Glass paste is applied as a plating resist to the parts other than the parts that will become the circuit part, and then fired. Alternatively, glass paste is first applied as a plating resist to the parts of the prepared ceramic substrate other than the part that will become the circuit part, and then fired, and then activated to accept the metal, and then electroless plated. The present invention provides a method for manufacturing a ceramic printed circuit board, characterized in that a circuit portion is formed by plating, and if necessary, further electrolytic plating is applied.
なお、本発明を実施するに先立って、焼結セラミックス
基板の準備が必要であるが、焼結基板の材質としては、
アルミナ、フォルステライト、ステアタイト、ジルコニ
ア、ムライト、コージェライト、チタニア等の酸化物系
セラミックスが主として使用されるが、炭化物系および
、窒化物系セラミックス基板もあり、これらの何れも対
象となし得る。Note that prior to carrying out the present invention, it is necessary to prepare a sintered ceramic substrate, and the material of the sintered substrate is as follows:
Oxide ceramics such as alumina, forsterite, steatite, zirconia, mullite, cordierite, and titania are mainly used, but carbide and nitride ceramic substrates are also available, and any of these can be used.
第１図（ａｌ、（ｂ）は、本発明にかかるセラミックス
配線回路板の製造工程の、それぞれ異なる実施例を示す
ブロック図である。以下、第１図＋８１、（ｂｌにそれ
ぞれ示したブロック図に従って詳しく説明する。FIGS. 1(al) and (b) are block diagrams showing different embodiments of the manufacturing process of a ceramic wiring circuit board according to the present invention.Hereinafter, the block diagrams shown in FIGS. 1+81 and (bl), respectively. This will be explained in detail.
本発明において使用するセラミックス基板は、後に施す
めっき層との密着性を強固なものとするために、予じめ
、その表面を粗面化する必要がある。粗面化法としては
、サンドブラスト法のように物理的に行う方法、あるい
は、アルカリ金属化合物、フッ化水素（ＨＦ）、五酸化
バナジウム（ＶｇＯｓ） 、ホウ砂、リン酸などの溶液
、融液を用いて化学的に行うものとがあるが、スルーホ
ール部や、大面積の基板に亙って均一に粗面化が行える
化学的手法を用いる方が好ましい。The surface of the ceramic substrate used in the present invention must be roughened in advance in order to ensure strong adhesion with the plating layer to be applied later. Surface roughening methods include physical methods such as sandblasting, or solutions and melts of alkali metal compounds, hydrogen fluoride (HF), vanadium pentoxide (VgOs), borax, phosphoric acid, etc. However, it is preferable to use a chemical method that can uniformly roughen the surface of a through-hole portion or a large area of the substrate.
〈第１図（ａ）による方法〉
前述のいずれかの方法で粗面化されたセラミックス基板
に先ず、金属を受容するように活性化処理を施す、この
活性化処理は、無電解めっきの活性核となり得る金属を
付ける処理である。活性核となり得る金属としては、そ
のような機能を有するものであれば使用可能であり、限
定するものではない。活性化処理の方法としては、従来
より用いられているセンシタイジング＝アクチベーショ
ン法またはキャタライジング＝アクセレーシゴン法によ
り、活性核としてたとえば、Ｐｄを基板表面に付与する
。<Method according to Fig. 1 (a)> First, the ceramic substrate whose surface has been roughened by any of the methods described above is subjected to an activation treatment so as to receive metal. This is a process that attaches metals that can become cores. Any metal that can serve as an active nucleus can be used as long as it has such a function, and is not limited to any particular metal. As a method of activation treatment, for example, Pd is applied as an active nucleus to the substrate surface by a conventionally used sensitizing=activation method or catalyzing=accelerating method.
つぎに、ガラスペーストを回路導体部となる部分以外の
部分にスクリーン印刷し、焼成する。このガラスがめつ
きレジストとして作用する。Next, glass paste is screen printed on the parts other than the parts that will become the circuit conductor parts, and fired. This glass acts as a plating resist.
従来法では、前述の如く有機材料をめっきレジストとし
て使用するため、高信幀性を要求される場合は、セラミ
ックス配線回路板に対して、熱に弱い有機材料をそのま
ま基板上に残存させておくことができず、したがってア
ディティブ法で回路導体部を形成後、有機系めっきレジ
ストを剥離除去しなければならなかった。 しかし、本
発明にかかる方法では、無機材料であるガラスをレジス
トとして用いるため、熱等によって信顛性が損なわれる
ことはないので、レジスト除去の工程が削減される。ま
た、回路部分をセラミックスで封着するような場合は、
さらに効果的である。In the conventional method, as mentioned above, an organic material is used as a plating resist, so if high reliability is required, the heat-sensitive organic material can be left as is on the ceramic printed circuit board. Therefore, the organic plating resist had to be peeled off after forming the circuit conductor part using an additive method. However, in the method according to the present invention, since glass, which is an inorganic material, is used as a resist, the reliability is not impaired by heat or the like, so that the process of removing the resist is reduced. In addition, when sealing the circuit part with ceramics,
Even more effective.
すなわち、セラミックスで封着する場合、第３図に示す
ように、回路形成がなされたセラミ・ノクス基板４およ
び、封着用セラミックス基板５の両面にガラスペースト
を塗布して仮焼成した後、両基板を重ね合わせて本焼成
し、封着を行うが、本方法では、第４図に示したように
アディティブ法による回路形成時にレジストとして用い
るガラスをそのまま封着剤としても利用できるため、さ
らに１工程を削減できる。第４図（ａ）は、封着用セラ
ミックス５の断面図であり、この図で２は封着用のガラ
ス層である。第４図（ｂ）はセラミックス封着されたセ
ラミックス配線回路板の一例を示す断面図である。That is, in the case of sealing with ceramics, as shown in FIG. 3, glass paste is applied to both sides of the ceramic NOx substrate 4 on which the circuit is formed and the ceramic substrate 5 for sealing, and after temporary firing, both substrates are bonded. This method requires one additional step because the glass used as a resist during circuit formation by the additive method can also be used as a sealant as is, as shown in Figure 4. can be reduced. FIG. 4(a) is a sectional view of the sealing ceramic 5, and in this figure, 2 is a sealing glass layer. FIG. 4(b) is a sectional view showing an example of a ceramic wiring circuit board sealed with ceramics.
なお、ここで使用するガラスペーストには特に指定はな
いが、エネルギーコストの点から、低温焼結ガラスを用
いるのが好ましい。Note that although there is no particular specification for the glass paste used here, it is preferable to use low-temperature sintered glass from the point of view of energy cost.
ガラスペーストには、空気中で焼成するものと、窒素雰
囲気中でも焼成可能なものがあるが、空気焼成タイプの
ガラスを用いた場合には、つぎの「核の活性化工程」を
行う必要がある。すなわち、空気中での焼成は、予じめ
セラミックス基板に核付けされたＰｄを酸化してしまい
、その活性度を奪ってしまうためである。これに対して
窒素中で焼成する場合は、予じめセラミックス基板に核
付けされたＰｄは、何らその活性度を失うことはないの
で活性化工程は不要である。There are glass pastes that can be fired in air and those that can be fired in a nitrogen atmosphere, but when using air-fired type glass, it is necessary to perform the following "nucleus activation process". . That is, firing in air oxidizes Pd that has been nucleated on the ceramic substrate in advance, thereby depriving it of its activity. On the other hand, when firing in nitrogen, the Pd that has been nucleated on the ceramic substrate in advance does not lose any of its activity, so no activation step is necessary.
なお、核の活性化工程では、例えば、５〜５０％濃度の
硫酸に１〜３０分間浸漬して処理すればよい。In addition, in the nuclear activation step, for example, the core may be immersed in 5 to 50% concentration of sulfuric acid for 1 to 30 minutes.
つぎに、無電解めっきを行う。無電解めっきで付ける金
属については特に指定はなく、用途に応じて選ばれるが
、低コスト、高導電性という点から、銅を使用するのが
好ましい。銅をめっきするためには無電解消めっき浴を
用いるのが一般的である。Next, electroless plating is performed. The metal to be applied by electroless plating is not particularly specified and is selected depending on the application, but it is preferable to use copper because of its low cost and high conductivity. To plate copper, it is common to use an electroless plating bath.
なお、めっき皮膜の厚みが要求される場合には、さらに
電解めっきを行ってめっき厚を増し、セラミックス配線
回路板を得る。In addition, when the thickness of the plating film is required, electrolytic plating is further performed to increase the plating thickness to obtain a ceramic wiring circuit board.
く第１図（ｂ）による方法〉
前述のいずれかの方法で粗面化されたセラミックス基板
に、ガラスペーストを回路導体部となる部分以外の部分
にスクリーン印刷で焼成する。このガラスがめつきレジ
ストとして作用する。Method according to FIG. 1(b)> On a ceramic substrate whose surface has been roughened by any of the methods described above, glass paste is fired by screen printing on the portions other than the portions that will become the circuit conductor portions. This glass acts as a plating resist.
ガラスペーストの種類については特に指定はないが、エ
ネルギーコストの点から低温焼成ガラスを用いることが
好ましい、また、焼成後の表面が平滑となるガラスペー
ストを用いるとさらに好ましい結果が得られる。Although there is no particular specification regarding the type of glass paste, it is preferable to use low-temperature fired glass from the point of view of energy cost, and more preferable results can be obtained by using a glass paste that provides a smooth surface after firing.
つぎに核付は処理を行う。その方法としては、キャタラ
イジング−アクセレーション法を用いる。Next, the core is processed. As the method, a catalyzing-acceleration method is used.
なお、キャタリスト中のＰｄの濃度を適正範囲に管理す
ることにより、核付けする基板の表面粗さの程度に応じ
て選択的な活性化が可能となる。すなわち、本工程にお
ける基板面は、粗面化されたセラミックス面と、めっき
レジストとして用いる表面平滑なガラス面を有しており
、Ｐｄの濃度を適正範囲に調整したキャタリスト中に浸
漬した場合、粗面化されているセラミックス面にＰｄが
付与され、表面平滑なガラス面にはほとんどＰｄが付着
し、い。Note that by controlling the concentration of Pd in the catalyst within an appropriate range, selective activation can be performed depending on the degree of surface roughness of the substrate to which nuclei are attached. That is, the substrate surface in this step has a roughened ceramic surface and a smooth glass surface used as a plating resist, and when it is immersed in a catalyst whose Pd concentration is adjusted to an appropriate range, Pd is applied to the roughened ceramic surface, and most of the Pd adheres to the smooth glass surface.
したがって、次工程の無電解めっき処理の際には、Ｐｄ
が付与されたセラミックス面（すなわち、回路部）のみ
に、選択的に金属が析出することになる。なお、キャタ
リストによりＰｄを付与した後、アクセレータにより、
Ｐｄの活性化を行う。Therefore, during the next step of electroless plating, Pd
Metal is selectively deposited only on the ceramic surface (that is, the circuit portion) provided with the metal. In addition, after adding Pd by the catalyst, the accelerator
Activate Pd.
つぎに無電解めっきを行い、必要ならばさらに電解めっ
きを施してセラミックス配線回路板を得る。Next, electroless plating is performed, and if necessary, further electrolytic plating is performed to obtain a ceramic wiring circuit board.
以上のようにして得られたセラミックス配線回路板の例
を断面図で示したのが第２図である。この図で１は粗面
化されたセラミックス基板、２はガラス層、３は回路部
であり、導体層で形成されている。FIG. 2 shows a cross-sectional view of an example of the ceramic wiring circuit board obtained as described above. In this figure, 1 is a ceramic substrate with a roughened surface, 2 is a glass layer, and 3 is a circuit section, which is formed of a conductor layer.
以上に説明したように、たとえば第１図（ａ）、（ｂ）
のいずれかの方法をとることにより、従来法に比ベニ程
数を削減でき、製造コストが低減できる効果が得られる
、なお、めっきレジストとして、無機質のガラスを使用
するので、信頼性が改善される効果もある。As explained above, for example, FIGS. 1(a) and (b)
By using either of these methods, the number of bending coefficients can be reduced compared to the conventional method, and the manufacturing cost can be reduced.In addition, since inorganic glass is used as the plating resist, reliability is improved. It also has the effect of
以下に本発明に係るセラミックス配線回路板の製法を、
実施例に基づき説明する。The manufacturing method of the ceramic printed circuit board according to the present invention will be described below.
This will be explained based on an example.
〔実施例１〕
第１図（ａ）に示したプロセスに従って実施し、第２図
に示した構成のセラミックス配線回路板を得た。以下、
図面に基づいて説明する。[Example 1] The process shown in FIG. 1(a) was followed to obtain a ceramic wiring circuit board having the configuration shown in FIG. 2. below,
The explanation will be based on the drawings.
まず高温リン酸溶液にて、表面粗さＲｍａ ｘが３〜５
μｍになるように化学的に粗面化した９６％Ａ１゜０、
基板１を用意し、センシタイジング＝アクチベーション
法により、Ｐｄの核付は処理を行った。First, with a high temperature phosphoric acid solution, the surface roughness Rmax is 3 to 5.
96% A1゜0 chemically roughened to a μm diameter,
A substrate 1 was prepared, and Pd nucleation was performed using a sensitizing/activation method.
つぎに、めっきレジストとして用いるガラスペーストを
＃２５０〜３２５メツシュのスクリーンで印刷し、空気
中４５０℃で焼成し、膜厚１２μｍのガラス層２を形成
した。そして酸化されたＰｄを活性化するために、１５
％硫酸に約１５分間浸漬した後、高速無電解銅めっき液
によって１０μｍの厚みの導体層３を形成し、セラミッ
クス配線回路板を得た。Next, a glass paste used as a plating resist was printed on a #250-325 mesh screen and fired in air at 450°C to form a glass layer 2 with a thickness of 12 μm. And in order to activate the oxidized Pd, 15
% sulfuric acid for about 15 minutes, a conductor layer 3 having a thickness of 10 μm was formed using a high-speed electroless copper plating solution to obtain a ceramic wiring circuit board.
本性により、従来法に比べ１工程を削減することができ
た。Due to its nature, it was possible to reduce one step compared to conventional methods.
〔実施例２〕 第２図（ａ）に示したプロセスに従って実施した。[Example 2] It was carried out according to the process shown in FIG. 2(a).
まず、水酸化ナトリウムの高温融液にて、表面粗さＲ＋
＋＋ａｘが２〜３μｍになるように化学的に粗面化した
９６％／１，０．基板ｌを用意し、センシタイジング＝
アクチベーション法により、Ｐｄの核付は処理を行った
。First, with a high temperature melt of sodium hydroxide, the surface roughness R+
96%/1,0. Prepare the substrate l and sensitize =
Nucleation of Pd was performed using an activation method.
つぎに、めっきレジストとして用いるガラスペーストを
＃２５０〜３２５メツシュのスクリーンで印刷し、Ｎ、
雰囲気中５００℃で焼成し、膜厚１２ｐｍのガラス層２
を形成した。つぎに高速無電解銅めっき液を使用して銅
膜厚ｌＯμｍの回路部３を形成し、セラミックス配線回
路板を得た。Next, the glass paste used as a plating resist was printed with a #250-325 mesh screen,
Glass layer 2 is baked at 500°C in an atmosphere and has a thickness of 12 pm.
was formed. Next, a circuit portion 3 having a copper film thickness of 10 μm was formed using a high-speed electroless copper plating solution to obtain a ceramic wiring circuit board.
このプロセスでは、ガラスペーストとしてＮｔ雰囲気中
で焼成可能なものを用いたので、Ｐｄ核が、その活性度
を保持しており、実施例１のプロセスよりさらに「核の
活性化工程」を削減することができた。In this process, since a glass paste that can be fired in an Nt atmosphere was used, the Pd nuclei maintain their activity, and the "nucleus activation step" is further reduced than in the process of Example 1. I was able to do that.
〔実施例３〕 第１図（ｂ）に示したプロセスに従って実施した。[Example 3] It was carried out according to the process shown in FIG. 1(b).
まず、高温リン酸溶液にて、表面粗さＲｍａ ｘが、３
〜５μｍになるように化学的に粗面化したＡｊ！０、基
板１を用意し、めっきレジストとして使用するガラスペ
ーストを、＃２５０〜３２５メツシュのスクリーンで印
刷し、Ｎ２雰囲気中５００℃で焼成し、膜厚１２μｍの
ガラス層２を得た。First, in a high temperature phosphoric acid solution, the surface roughness Rmax is 3
Aj chemically roughened to ~5μm! 0. A substrate 1 was prepared, a glass paste used as a plating resist was printed on a #250 to 325 mesh screen, and baked at 500° C. in an N2 atmosphere to obtain a glass layer 2 with a thickness of 12 μm.
つぎにキャタライジング−アクセレーション法によりＰ
ｄの核付けを行った。このとき、キャタリスト中のＰｄ
の濃度を標準の７５％程度に希釈したものを用いた。ア
クセレータとして、１０％濃度の硫酸を用い、これに３
〜１０分間浸漬した。前述のようにＰｄは、粗面化され
たセラミックス面にのみ付与された。Next, P by the catalyzing-acceleration method
Nucleation of d was carried out. At this time, Pd in the catalyst
A diluted concentration of about 75% of the standard was used. As an accelerator, 10% sulfuric acid was used, and 3
Soaked for ~10 minutes. As mentioned above, Pd was applied only to the roughened ceramic surface.
つぎに、高速無電解銅めっきを施し、導体層３の厚みが
１０μｍのセラミックス配線回路板を得た。Next, high-speed electroless copper plating was performed to obtain a ceramic printed circuit board with a conductor layer 3 having a thickness of 10 μm.
このとき、ガラス面には全く銅は析出しなかった。At this time, no copper was deposited on the glass surface.
このプロセスにより、実施例２と同じ工程数でセラミッ
クス配線回路板が作成できた。Through this process, a ceramic printed circuit board could be produced using the same number of steps as in Example 2.
〔実施例４〕
ガラスペーストとして空気中焼成タイプのものを用いた
他は、実施例３と同様の方法、すなわち第１回申）のプ
ロセスでセラミックス配線回路板を得た。第２回申）の
プロセスでは、ガラスペーストの焼成雰囲気の如何を問
わず、従来法に比べて２工程削減できた。[Example 4] A ceramic wiring circuit board was obtained by the same method as in Example 3, ie, the process of the first test, except that an air-fired type glass paste was used. In the process described in the second paper, two steps could be reduced compared to the conventional method, regardless of the firing atmosphere of the glass paste.
〔実施例５〕
１〜２ ｍ ｏ １ ／ １の水酸化ナトリウム溶液に
て表面粗さＲｍａｘが、３〜５μｍになるように化学的
に粗面化したＡＩＮ基板を用いた他は、実施例３と同様
のプロセスで、第４図（ａ）に示したような、予じめガ
ラス層２を塗布形成し、仮焼成した封着用セラミックス
５を用意し、第４図（ｂ）に示した構造になるように封
着を行った。このプロセスでは、めっきレジストとして
使用したガラスを封着用ガラスとしても利用できるため
、従来法では必要であった、有機のめっきレジストを剥
離した後、新たに封着用ガラスをセラミックス配線回路
板に塗布する工程が削減された。[Example 5] Example 5 was used except that an AIN substrate was chemically roughened with a 1 to 2 m o 1/1 sodium hydroxide solution so that the surface roughness Rmax was 3 to 5 μm. In the same process as in 3, a sealing ceramic 5 shown in FIG. 4(a) on which a glass layer 2 was coated and pre-fired was prepared. Sealing was performed to form a structure. In this process, the glass used as a plating resist can also be used as a sealing glass, so after peeling off the organic plating resist, which was necessary in the conventional method, a new sealing glass is applied to the ceramic printed circuit board. Processes have been reduced.
なお、めっきレジストとして用いるガラスを封着用ガラ
スとしても利用する場合は、ガラス層２の厚みは、導体
層３の厚みよりも厚いことが必要である。Note that when the glass used as the plating resist is also used as the sealing glass, the thickness of the glass layer 2 needs to be thicker than the thickness of the conductor layer 3.
［発明の効果］
本発明にかかるセラミックス配線回路板の製法では、ガ
ラスをめっきレジストとして使用するため、有機系のめ
っきレジストのように剥離する必要がなく、必要ならば
、さらに封着用ガラスとしても利用できるので従来法に
比ベニ程数を削減でき、低コスト化が実現できる効果が
ある。[Effects of the Invention] In the method for manufacturing a ceramic wiring circuit board according to the present invention, glass is used as a plating resist, so there is no need to peel it off unlike organic plating resists, and if necessary, it can also be used as a sealing glass. Since it can be used, the Beni divisor can be reduced compared to the conventional method, which has the effect of realizing cost reduction.
第１図（ａ）、山）は本発明にかかるセラミックス配線
回路板の製造プロセスを示したブロック図、第２図は、
本発明にかかるプロセスで作成したセラミックス配線回
路板の一例を示す断面図、第３図は、従来の封止セラミ
ックス配線回路板の製法の概要を示す断面図、第４図（
ａ）は、本発明にかかるセラミックス配線回路板の封着
用セラミックスの概要を示す断面図、第４図（ｂ）は、
本発明にかかるセラミックス配線回路板の封着状態を示
す断面図、第５図は、従来のアディティブ法によるセラ
ミックス配線回路板の製造プロセスの一例を示したブロ
ック図である。
１は粗面化セラミックス基板
２はガラス層
３は回路部
４はセラミックス基板
５は封着用セラミックスFIG. 1(a), crest) is a block diagram showing the manufacturing process of the ceramic wiring circuit board according to the present invention, and FIG.
FIG. 3 is a sectional view showing an example of a ceramic wiring circuit board produced by the process according to the present invention, and FIG.
a) is a sectional view showing an outline of the sealing ceramic for a ceramic wiring circuit board according to the present invention, and FIG. 4(b) is a
FIG. 5, which is a sectional view showing the sealed state of the ceramic wiring circuit board according to the present invention, is a block diagram showing an example of the manufacturing process of the ceramic wiring circuit board by the conventional additive method. 1 is a roughened ceramic substrate 2 is a glass layer 3 is a circuit section 4 is a ceramic substrate 5 is a sealing ceramic
Claims (1)
成するセラミックス配線回路板の製法において、粗面化
されたセラミックス基板を用意し、つぎにセラミックス
基板面に金属が受容されるように活性化処理を施した後
、回路部となる部分以外の部分にめっきレジストとして
ガラスペーストを付けて焼成するか、または用意された
セラミックス基板の回路部となる部分以外の部分に、先
ずめっきレジストとしてガラスペーストを付けて焼成し
た後、金属が受容されるように活性化処理を施し、しか
る後無電解めっきによって回路部を形成し、必要ならば
、さらに電解めっきを施すことを特徴とするセラミック
ス配線回路板の製法。(1) In the manufacturing method of ceramic wiring circuit boards in which the circuit portion is formed by an additive method using plating, a roughened ceramic substrate is prepared, and then an activation treatment is performed so that the metal is received on the ceramic substrate surface. After that, glass paste is applied as a plating resist to parts other than the part that will become the circuit part and fired, or glass paste is first applied as a plating resist to the part of the prepared ceramic substrate other than the part that will become the circuit part. A method for manufacturing a ceramic wiring circuit board, which comprises firing, performing an activation treatment to accept metal, then forming a circuit part by electroless plating, and further performing electrolytic plating if necessary.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30678986A JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30678986A JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63158894A true JPS63158894A (en) | 1988-07-01 |
| JPH0357636B2 JPH0357636B2 (en) | 1991-09-02 |
Family
ID=17961266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30678986A Granted JPS63158894A (en) | 1986-12-23 | 1986-12-23 | Manufacture of ceramic wiring circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63158894A (en) |
-
1986
- 1986-12-23 JP JP30678986A patent/JPS63158894A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0357636B2 (en) | 1991-09-02 |
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