JP3069476B2 - Multilayer printed wiring board and method of manufacturing the same - Google Patents

Multilayer printed wiring board and method of manufacturing the same

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Publication number
JP3069476B2
JP3069476B2 JP24779893A JP24779893A JP3069476B2 JP 3069476 B2 JP3069476 B2 JP 3069476B2 JP 24779893 A JP24779893 A JP 24779893A JP 24779893 A JP24779893 A JP 24779893A JP 3069476 B2 JP3069476 B2 JP 3069476B2
Authority
JP
Japan
Prior art keywords
wiring board
layer
printed wiring
mol
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP24779893A
Other languages
Japanese (ja)
Other versions
JPH06283860A (en
Inventor
雅人 川出
彰彦 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP24779893A priority Critical patent/JP3069476B2/en
Publication of JPH06283860A publication Critical patent/JPH06283860A/en
Application granted granted Critical
Publication of JP3069476B2 publication Critical patent/JP3069476B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は多層プリント配線板およ
びその製造方法に関し、特に、耐ヒートサイクル特性に
優れる多層プリント配線板およびその製造方法について
提案する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method for manufacturing the same, and more particularly, to a multilayer printed wiring board excellent in heat cycle resistance and a method for manufacturing the same.

【0002】[0002]

【従来の技術】配線の高密度化あるいは演算機能の高速
化に好適な多層プリント配線板は、近年、導体回路と層
間絶縁材層とを交互にビルドアップし、バイアホールな
どによって内・外装回路を接続,導通させてなるビルド
アップ多層配線板が注目を浴びている。このビルドアッ
プ多層配線板は、主としてアディティブ法により製造さ
れている。
2. Description of the Related Art In recent years, multilayer printed wiring boards suitable for high-density wiring or high-speed arithmetic functions have recently been constructed by alternately building up conductive circuits and interlayer insulating layers, and providing internal and external circuits through via holes and the like. The build-up multilayer wiring board which connects and conducts is attracting attention. This build-up multilayer wiring board is mainly manufactured by an additive method.

【0003】このアディティブ法は、ガラスエポキシ等
の絶縁基板上に無電解めっき用樹脂絶縁材を塗布するこ
とにより絶縁材層を形成し、次いでこの絶縁材層の表面
を粗化した後、その粗化面にめっきレジストを形成し、
その後、無電解めっきによって導体回路となる金属を付
着させる方法である。
In the additive method, an insulating material layer is formed by applying a resin insulating material for electroless plating on an insulating substrate such as glass epoxy, and then the surface of the insulating material layer is roughened. Forming a plating resist on the surface
Thereafter, a method of attaching a metal to be a conductor circuit by electroless plating.

【0004】このような方法によると、粗化された絶縁
材層上に導体回路をめっき等によって付着させることか
ら、層間絶縁材層とその上に設けられる導体回路との密
着性を向上させることができる。
According to such a method, since a conductor circuit is deposited on the roughened insulating material layer by plating or the like, the adhesion between the interlayer insulating material layer and the conductor circuit provided thereon is improved. Can be.

【0005】一方で、上記方法において、導体回路とそ
の上に設けられる層間絶縁材層との密着性を改善する手
段としては、従来、導体回路表面を酸化、還元して、表
面を粗化する、いわゆる黒化・還元処理が行われてい
る。このような黒化・還元処理を行うと、導体回路の表
面が粗化され、この粗化面がアンカーとなって、層間絶
縁材層と導体回路との結合を物理的に強化させることが
できる。
On the other hand, in the above method, as means for improving the adhesion between the conductor circuit and the interlayer insulating material layer provided thereon, conventionally, the surface of the conductor circuit is oxidized and reduced to roughen the surface. That is, a so-called blackening / reducing treatment is performed. When such a blackening / reducing treatment is performed, the surface of the conductor circuit is roughened, and the roughened surface serves as an anchor, thereby physically strengthening the connection between the interlayer insulating material layer and the conductor circuit. .

【0006】[0006]

【発明が解決しようとする課題】しかしながら、導体回
路とその上に設けられる層間絶縁材層との密着性は、上
述したような黒化・還元処理技術を用いても、なお不十
分であり、環境の厳しい条件下では、プリント配線板の
耐ヒートサイクル特性に欠けるという問題があった。例
えば、−6℃〜150 ℃の MIL−883 に準じた条件下での
試験によると、プリント配線板の耐ヒートサイクル特性
は、層間絶縁材層が剥離を生じない最大サイクル数で30
0 サイクル程度であった。
However, the adhesion between the conductor circuit and the interlayer insulating material layer provided thereon is still insufficient even by using the above-described blackening / reducing treatment technique. Under severe environmental conditions, there is a problem that the printed wiring board lacks heat cycle resistance. For example, according to a test under conditions according to MIL-883 at −6 ° C. to 150 ° C., the heat cycle resistance of the printed wiring board is 30 cycles at the maximum number of cycles at which the interlayer insulating layer does not peel.
It was about 0 cycles.

【0007】そこで本発明の目的は、従来技術が抱える
上記問題を解決することにあり、特に、耐ヒートサイク
ル特性に優れる多層プリント配線板およびその製造技術
を提供することにある。
An object of the present invention is to solve the above-mentioned problems of the prior art, and in particular, to provide a multilayer printed wiring board having excellent heat cycle resistance and a manufacturing technique therefor.

【0008】[0008]

【課題を解決するための手段】発明者らは、上記目的の
実現に向け鋭意研究した結果、導体回路と層間絶縁材層
との界面に針状結晶の無電解めっき皮膜からなる粗化層
を設けることにより、上記目的を実現できることを見出
し、本発明に想到した。
Means for Solving the Problems The inventors of the present invention have conducted intensive studies for realizing the above object, and as a result, have found that a roughened layer made of an electroless plating film of needle-like crystals is provided at the interface between a conductor circuit and an interlayer insulating material layer. It has been found that the above-mentioned object can be realized by providing, and the present invention has been reached.

【0009】すなわち、本発明は、基板上に、表面の少
なくとも一部に粗化層を有する導体回路が設けられ、さ
らにこの導体回路を含む基板上には層間絶縁材層が設け
られ、そしてさらに、この層間絶縁材層上には他の導体
回路が設けられてなる多層プリント配線板において、前
記粗化層は、Cu,NiおよびP、好ましくは90<Cu<100m
ol%,0<Ni< 10mol%および0<P< 10mol%からな
る共晶化合物を含む層で構成されていることを特徴とす
る多層プリント配線板であり、前記粗化層は、針状結晶
の被膜であり、その厚さが5μm以下の被膜であること
が望ましい。そして、上記多層プリント配線板の製造方
法は、基板上に設けられた導体回路表面の少なくとも一
部に粗化層を形成し、次いで、前記基板上に層間絶縁材
層を形成し、その後、その層間絶縁材層上に導体回路を
設ける多層プリント配線板の製造方法において、導体回
路が設けられた基板を、少なくともCu化合物、Ni化合物
および次亜リン酸塩を含有する無電解めっき浴中に浸漬
することにより、前記導体回路表面の少なくとも一部
に、Cu,NiおよびPからなる共晶化合物を含む粗化層を
形成することを特徴とする多層プリント配線板の製造方
法であり、浴中のCuイオン濃度,Niイオン濃度および次
亜リン酸イオン濃度が、それぞれ、 2.2×10-2〜 4.1×
10-2 mol/l,2.2 ×10-3〜 4.1×10-3 mol/l,0.20
〜0.25 mol/lであるめっき浴を用いる無電解めっき
(共晶めっき)を施すことにより、導体回路表面の少な
くとも一部に、90<Cu<100mol%,0<Ni< 10mol%お
よび0<P< 10mol%からなる共晶化合物を含む粗化層
を形成することが望ましく、また、前記Cu化合物、Ni化
合物および次亜リン酸塩は、それぞれ硫酸銅、硫酸ニッ
ケルおよび次亜リン酸ナトリウムであることが望まし
い。なお、本発明では、導体回路が設けられた基板は、
多層基板であっても差支えない。
That is, according to the present invention, a conductive circuit having a roughened layer on at least a part of the surface is provided on a substrate, and an interlayer insulating material layer is provided on the substrate including the conductive circuit. In the multilayer printed wiring board in which another conductive circuit is provided on the interlayer insulating material layer, the roughened layer is made of Cu, Ni and P, preferably 90 <Cu <100 m
ol%, 0 <Ni <10 mol%, and 0 <P <10 mol% comprising a layer containing a eutectic compound, wherein the roughened layer is a needle-shaped crystal. It is desirable that the film has a thickness of 5 μm or less. The method for manufacturing a multilayer printed wiring board includes forming a roughened layer on at least a part of the surface of a conductive circuit provided on a substrate, and then forming an interlayer insulating material layer on the substrate, In the method for manufacturing a multilayer printed wiring board in which a conductor circuit is provided on an interlayer insulating material layer, the substrate provided with the conductor circuit is immersed in an electroless plating bath containing at least a Cu compound, a Ni compound, and hypophosphite. Thereby forming a roughened layer containing a eutectic compound composed of Cu, Ni and P on at least a part of the surface of the conductor circuit, thereby producing a multilayer printed wiring board. Cu ion concentration, Ni ion concentration and hypophosphite ion concentration are 2.2 × 10 -2 to 4.1 ×, respectively.
10 -2 mol / l, 2.2 × 10 -3 to 4.1 × 10 -3 mol / l, 0.20
By applying electroless plating (eutectic plating) using a plating bath of 0.20.25 mol / l, 90 <Cu <100 mol%, 0 <Ni <10 mol% and 0 <P It is desirable to form a roughened layer containing a eutectic compound of <10 mol%, and the Cu compound, Ni compound and hypophosphite are copper sulfate, nickel sulfate and sodium hypophosphite, respectively. It is desirable. In the present invention, the substrate provided with the conductor circuit is:
A multilayer substrate may be used.

【0010】[0010]

【作用】黒化還元処理による粗化層は、銅表面を酸化し
て酸化銅を形成させることにより得られるが、この粗化
層を構成する酸化銅の強度が低く、それ故に、熱衝撃に
より破壊されて層間剥離を起こしやすい。この点、本発
明の共晶めっきによる粗化層は、この粗化層を構成する
Cu,NiおよびPからなる共晶化合物自体の強度が高く、
しかも、針状結晶であるためにアンカーとしての効果に
優れ、導体回路と層間絶縁材層とを強固に密着させるこ
とができ、それ故に、熱衝撃による層間剥離が生じにく
く、耐ヒートサイクル特性が向上する。さらに、黒化還
元処理による粗化層は、酸化銅または銅が表面に曝露さ
れているために、化学銅めっき浴のアルカリ液で溶解
し、いわゆるハローイング現象を生じやすく、しかも、
銅表面が酸化されたりする。この点、本発明の共晶めっ
きによる粗化層は、Cuに比べて耐薬品性・耐酸化性が高
いCu−Ni−P共晶化合物で形成されているため、化学銅
めっき浴中で溶解したり酸化したりせず、高い密着力を
確保できる。以上説明したように本発明の多層プリント
配線板は、導体回路と層間絶縁材層の界面に設けられる
無電解めっき膜からなる粗化層が、Cu,NiおよびPから
なる共晶化合物である点に特徴がある。
The roughened layer formed by the blackening reduction treatment is obtained by oxidizing the copper surface to form copper oxide. However, the strength of the copper oxide constituting the roughened layer is low, and therefore, the roughened layer is formed by thermal shock. It is easily broken and delaminated. In this regard, the roughened layer formed by the eutectic plating of the present invention constitutes the roughened layer.
The strength of the eutectic compound itself consisting of Cu, Ni and P is high,
In addition, the needle-like crystal has an excellent effect as an anchor, and the conductor circuit and the interlayer insulating material layer can be firmly adhered to each other. Therefore, delamination due to thermal shock hardly occurs and heat cycle resistance is improved. improves. Furthermore, since the copper oxide or copper is exposed to the surface, the roughened layer formed by the blackening reduction process is dissolved in the alkaline solution of the chemical copper plating bath, so that a so-called haloing phenomenon easily occurs.
The copper surface is oxidized. In this regard, since the roughened layer formed by the eutectic plating of the present invention is formed of a Cu-Ni-P eutectic compound having higher chemical resistance and oxidation resistance than Cu, the roughened layer is dissolved in a chemical copper plating bath. High adhesion can be secured without dripping or oxidation. As described above, the multilayer printed wiring board of the present invention is characterized in that the roughened layer made of the electroless plating film provided at the interface between the conductor circuit and the interlayer insulating material layer is a eutectic compound made of Cu, Ni and P. There is a feature.

【0011】ここに、本発明において、上記共晶化合物
は、図1の斜線で示した範囲、すなわち、90<Cu<100m
ol%,0<Ni< 10mol%および0<P< 10mol%からな
ることが好ましい。この理由は、Cuが90 mol%以下だと
析出皮膜の結晶が粉状になり、Niが 10mol%以上だと析
出皮膜の結晶が粉状になると共に導電性が悪くなり、P
が 10mol%以上だと抵抗値が高くなり針状結晶となりに
くいからである。すなわち、上記組合せにおいて、析出
被膜の結晶が針状構造になり、アンカー効果に優れる構
造となるからである。
Here, in the present invention, the above-mentioned eutectic compound is in a range shown by hatching in FIG. 1, that is, 90 <Cu <100 m
ol%, 0 <Ni <10 mol% and 0 <P <10 mol%. The reason is that if the Cu content is 90 mol% or less, the crystals of the deposited film become powdery, and if the Ni content is 10 mol% or more, the crystals of the deposited film become powdery and the conductivity deteriorates.
If the content is more than 10 mol%, the resistance value increases and it is difficult to form needle-like crystals. That is, in the above combination, the crystals of the deposited film have a needle-like structure and a structure having an excellent anchor effect.

【0012】本発明において、上記粗化層は、その厚さ
が5μm以下の皮膜であることが望ましく、特に0.5 μ
m〜2μmの範囲が好適である。この理由は、0.5 μm
未満では、アンカー効果が低く、一方、5μm超では、
表面粗度が大きくなりすぎ、却って密着強度が低下して
しまうからである。
In the present invention, the roughened layer is desirably a film having a thickness of 5 μm or less, particularly 0.5 μm.
The range from m to 2 μm is preferred. The reason is 0.5 μm
Below 5 μm, the anchor effect is low, while above 5 μm
This is because the surface roughness becomes too large, and the adhesion strength is rather reduced.

【0013】なお、本発明の多層プリント配線板は、基
板上の導体回路と層間絶縁材層上に設けられた他の導体
回路とが、バイアホールやスルーホールで電気的に接続
されていてもよい。バイアホールで接続する場合、接続
箇所に粗化層があると、わずかではあるが、抵抗値が高
くなる。しかしながら、先に説明した黒化還元処理のよ
うな酸化銅が形成されるわけではないので、電気的に絶
縁されることがなく、黒化還元処理に比べて有利であ
る。なお、接続箇所の粗化層は、予め除去されている
か、粗化層を設けない構成でもよい。
In the multilayer printed wiring board of the present invention, even if a conductor circuit on a substrate and another conductor circuit provided on an interlayer insulating material layer are electrically connected to each other through via holes or through holes. Good . If you want to connect in the bus Iahoru, connection
If there is a roughened layer in the area, the resistance value will be high, albeit slightly.
It becomes. However, the blackening reduction process described above
Copper oxide is not formed,
It is not edged and is advantageous compared to the blackening reduction process.
You. Note that the roughened layer at the connection point may be removed in advance or may be configured without the roughened layer .

【0014】本発明において、層間絶縁材層として用い
る樹脂絶縁材は、酸もしくは酸化剤に対して難溶性の樹
脂からなるマトリックス中に酸もしくは酸化剤に対して
可溶性の硬化処理された耐熱性樹脂粉末を分散してなる
ものであることが望ましい。この理由は、上記樹脂絶縁
材を用いて得られる層間絶縁材層は、酸あるいは酸化剤
によって容易に粗化面を設けることができ、層間絶縁材
層とその上に無電解めっきにより設けられる導体回路と
の密着性を向上させることができるからである。このよ
うな粗化面を形成するためのアンカー形成用耐熱性樹脂
粉末は、例えば、平均粒径10μm以下の耐熱性樹脂粉
末、平均粒径2μm以下の耐熱性樹脂粉末を凝集させ
て平均粒径2〜10μmの大きさとした凝集粒子、平均
粒径2〜10μmの耐熱性樹脂粉末と平均粒径2μm以下
の耐熱性樹脂粉末との混合物、平均粒径2〜10μmの
耐熱性樹脂粉末の表面に、平均粒径2μm以下の耐熱性
樹脂粉末もしくは平均粒径2μm以下の無機粉末のいず
れか少なくとも1種を付着させてなる擬似粒子、から選
ばれることが好適である。なお、形成されるアンカーの
形状や深さについては、粒径の異なる樹脂粉末にて表面
粗度が1〜20μmの範囲内になるようにすることが望ま
しく、かかる場合に、導体の十分な密着強度が得られ
る。また、上記樹脂絶縁材を構成するマトリックス樹脂
は、感光特性を示すものであることが望ましい。これ
は、感光特性を示す樹脂を用いることにより、露光、現
像で容易にバイアホールを形成できるからである。
In the present invention, the resin insulating material used as the interlayer insulating material layer is a hardened heat-resistant resin which is soluble in an acid or an oxidizing agent in a matrix made of a resin which is hardly soluble in an acid or an oxidizing agent. It is desirable that the powder be dispersed. The reason for this is that the interlayer insulating material layer obtained using the above resin insulating material can be easily provided with a roughened surface by an acid or an oxidizing agent, and the interlayer insulating material layer and a conductor provided thereon by electroless plating. This is because adhesion to a circuit can be improved. The heat-resistant resin powder for forming an anchor for forming such a roughened surface is, for example, a heat-resistant resin powder having an average particle diameter of 10 μm or less, and a heat-resistant resin powder having an average particle diameter of 2 μm or less is aggregated. Agglomerated particles having a size of 2 to 10 μm, a mixture of a heat-resistant resin powder having an average particle size of 2 to 10 μm and a heat-resistant resin powder having an average particle size of 2 μm or less, on the surface of the heat-resistant resin powder having an average particle size of 2 to 10 μm It is preferable to select pseudo particles obtained by adhering at least one of a heat-resistant resin powder having an average particle diameter of 2 μm or less and an inorganic powder having an average particle diameter of 2 μm or less. The shape and depth of the formed anchor are desirably adjusted so that the surface roughness is in the range of 1 to 20 μm using resin powders having different particle diameters. Strength is obtained. Further, it is desirable that the matrix resin constituting the resin insulating material has photosensitive characteristics. This is because a via hole can be easily formed by exposure and development by using a resin exhibiting photosensitive characteristics.

【0015】次に、本発明の多層プリント配線板の製造
方法について説明する。本発明の製造方法は、導体回路
が設けられた基板を、少なくともCu化合物、Ni化合物お
よび次亜リン酸塩を含有するめっき浴中に浸漬して無電
解めっきを施すことにより、前記導体回路表面の少なく
とも一部に、Cu,NiおよびPからなる共晶化合物を含む
粗化層を形成する点に特徴がある。これによれば、無電
解めっきによって析出する皮膜の結晶は、針状結晶構造
のCu、NiおよびPからなる共晶化合物となり、この針状
結晶構造が、導体回路とその上に設けられる層間絶縁材
層との密着性を向上させるアンカー効果として作用す
る。
Next, a method for manufacturing a multilayer printed wiring board according to the present invention will be described. The production method of the present invention is characterized in that the substrate provided with the conductor circuit is immersed in a plating bath containing at least a Cu compound, a Ni compound and hypophosphite and subjected to electroless plating, whereby the surface of the conductor circuit is provided. Is characterized in that a roughened layer containing a eutectic compound composed of Cu, Ni and P is formed on at least a part of the layer. According to this, the crystal of the film deposited by the electroless plating is a eutectic compound composed of Cu, Ni and P having a needle-like crystal structure, and this needle-like crystal structure forms a conductor circuit and an interlayer insulating film provided thereon. It acts as an anchor effect for improving the adhesion to the material layer.

【0016】ここで、上記無電解めっき浴中のCuイオン
濃度,Niイオン濃度および次亜リン酸イオン濃度は、そ
れぞれ、 2.2×10-2〜 4.1×10-2 mol/l,2.2 ×10-3
〜 4.1×10-3 mol/l,0.20〜0.25 mol/lであること
が望ましい。この理由は、上記範囲内で、析出する皮膜
の結晶構造が針状構造になるため、アンカー効果に優れ
るからである。なお、無電解めっき浴には、上記化合物
の他に錯化剤や添加剤等を適宜添加してもよい。また、
無電解めっきを施す前には、Pdなどの触媒核を予め付与
しておいてもよい。
[0016] Here, the Cu ion concentration in an electroless plating bath, Ni ion concentration and hypophosphite ion concentration, respectively, 2.2 × 10 -2 ~ 4.1 × 10 -2 mol / l, 2.2 × 10 - Three
Desirably, it is about 4.1 × 10 −3 mol / l and 0.20 to 0.25 mol / l. The reason for this is that, within the above range, the crystalline structure of the deposited film has a needle-like structure, so that the anchor effect is excellent. In addition, a complexing agent, an additive, and the like may be appropriately added to the electroless plating bath in addition to the above compounds. Also,
Before performing the electroless plating, a catalyst nucleus such as Pd may be applied in advance.

【0017】上記無電解めっきの条件は、浴温度が60〜
80℃、析出速度が1〜1.5 μm/10分、浴比が0.5 〜1.
0 dm2 /l、浴pHが8〜10、めっき時間が5〜20分で
あることが望ましい。これは、上記条件を逸脱すると、
析出するめっき被膜が、緻密にならず、耐ヒートサイク
ル特性が著しく低下してしまうからである。
The conditions of the above electroless plating are as follows.
80 ° C., deposition rate 1-1.5 μm / 10 min, bath ratio 0.5-1.
0 dm 2 / l, bath pH is preferably 8 to 10, and plating time is preferably 5 to 20 minutes. This means that if you deviate from the above conditions,
This is because the deposited plating film does not become dense and the heat cycle resistance is significantly reduced.

【0018】本発明方法においては、基板上の導体回路
表面に粗化層を形成する上記処理を終えた後、この導体
回路を含む基板上に層間絶縁材層を設け、これにバイア
ホール用の凹部やスルーホール用の貫通孔を形成し、そ
してさらに、この層間絶縁材層上に、必要に応じてめっ
きレジストを形成し、無電解めっきにより他の導体回路
を設け、多層プリント配線板を得る。ここで、バイアホ
ールにより上層と下層の導体回路を接続する場合には、
接続箇所の粗化層は、予め除去されているか、粗化層を
下層の導体回路に設けない構成でもよい。このような場
合では、無電解めっきにより導体回路表面に粗化層を設
ける前に、バイアホールにより接続される部分をマスク
しておく方法がよい。なお、本発明における上層ならび
に内層の導体回路は、常法に従い設けることができる。
以下、実施例について詳細に説明する。
In the method of the present invention, after the above-described process of forming a roughened layer on the surface of a conductive circuit on a substrate is completed, an interlayer insulating material layer is provided on the substrate including the conductive circuit, and a via hole Form a through hole for a concave portion or a through hole, and further form a plating resist on this interlayer insulating material layer as necessary, provide another conductive circuit by electroless plating, and obtain a multilayer printed wiring board . Here, when connecting the upper and lower conductor circuits by via holes,
The roughened layer at the connection point may be removed in advance, or the roughened layer may not be provided in the lower conductive circuit . Such a place
In case, prior to providing a roughened layer on the conductor circuit surface by electroless plating, it is a method to keep masking part component that will be connected by via holes. Note that the conductor circuits of the upper layer and the inner layer in the present invention can be provided according to a conventional method.
Hereinafter, examples will be described in detail.

【0019】[0019]

【実施例】(実施例1) ビルドアップ法による多層プリント配線板を、以下に示
す製造工程(1) 〜(10)にしたがって得た。 (1) 銅張積層板をエッチングして内層回路1を形成した
後、その基板を酸性脱脂し、ソフトエッチングし、Cu上
にPd触媒を置換付与し、活性化した後、表1に示す組成
の無電解めっき浴にてめっきを施し、図2(a) に示すよ
うに導体回路の側面を含む全面にNi−P−Cu共晶の厚さ
1μmの粗化層2を得た (図2(a) 参照)。この粗化層
2の組成は、EPMA(蛍光X線分析器)で分析した結果、
Cu;98 mol%、Ni;1.5mol%、P;0.5mol%であった。
EXAMPLES (Example 1) A multilayer printed wiring board by a build-up method was obtained according to the following manufacturing steps (1) to (10). (1) After etching the copper-clad laminate to form the inner layer circuit 1, the substrate is acid degreased, soft-etched, substituted with a Pd catalyst on Cu, activated, and then subjected to the composition shown in Table 1. Plating in the electroless plating bath shown in Fig. 2 (a)
Thus, a roughened layer 2 of Ni-P-Cu eutectic having a thickness of 1 μm was obtained on the entire surface including the side surfaces of the conductor circuit (see FIG. 2A) . The composition of the roughened layer 2 was analyzed by EPMA (X-ray fluorescence analyzer),
Cu: 98 mol%, Ni: 1.5 mol%, P: 0.5 mol%.

【0020】[0020]

【表1】 [Table 1]

【0021】(2) クレゾールノボラック型エポキシ樹脂
(油化シェル製,商品名:エピコート180S)50%アク
リル化物60重量部に、ビスフェノールA型エポキシ樹脂
(油化シェル製,商品名:E-1001)40重量部、ジアリル
テレフタレート15重量部、2−メチル−1−〔4−(メ
チルチオ)フェニル〕2−モルフォリノプロパノン−1
(チバ・ガイギー製,商品名:イルガキュア−907 )4
重量部、粒径が5.5 μmのエポキシ樹脂微粉末(東レ
製)10重量部、および粒径が0.5 μmのエポキシ樹脂微
粉末(東レ製)25重量部を配合した。そして、この混合
物にブチルセロソルブを適量添加しながらホモディスパ
ー攪拌機で攪拌し、樹脂絶縁材のワニスを作成した。
(2) Cresol novolak type epoxy resin (manufactured by Yuka Shell, trade name: Epicoat 180S) Bisphenol A type epoxy resin (manufactured by Yuka Shell, trade name: E-1001) is added to 60 parts by weight of 50% acrylate. 40 parts by weight, diallyl terephthalate 15 parts by weight, 2-methyl-1- [4- (methylthio) phenyl] 2-morpholinopropanone-1
(Ciba Geigy, trade name: Irgacure-907) 4
10 parts by weight of an epoxy resin fine powder (manufactured by Toray) having a particle diameter of 5.5 μm and 25 parts by weight of an epoxy resin fine powder (manufactured by Toray) having a particle diameter of 0.5 μm were blended. Then, the mixture was stirred with a homodisper stirrer while adding an appropriate amount of butyl cellosolve to prepare a varnish of a resin insulating material.

【0022】(3) ロールコータを用いて内層回路1上に
上記のワニスを塗布した後、塗布されたワニスを100 ℃
で1時間乾燥硬化させ、厚さ50μmの感光性の層間絶縁
材層3を形成した(図2(b) 参照)。
(3) After applying the varnish on the inner layer circuit 1 using a roll coater, the applied varnish is heated to 100 ° C.
For 1 hour to form a photosensitive interlayer insulating material layer 3 having a thickness of 50 μm (see FIG. 2B).

【0023】(4) 前記工程(3) の処理を施した配線板
に、直径100 μmの黒円および打ち抜き切断部位が黒く
印刷されたフォトマスクフィルムを密着させ、超高圧水
銀灯により500 mj/cm2 で露光した。これをクロロ
セン溶液で超音波現像処理することにより配線板上に直
径100 μmのバイアホールとなる開口4を形成した。
(4) A black circle having a diameter of 100 μm and a photomask film in which a punched and cut portion is printed in black are brought into close contact with the wiring board subjected to the treatment in the step (3), and 500 mj / cm is applied by an ultrahigh pressure mercury lamp. Exposure at 2 . This was subjected to ultrasonic development with a chlorocene solution to form an opening 4 serving as a via hole having a diameter of 100 μm on the wiring board.

【0024】(5) 前記配線板を超高圧水銀灯により約30
0 mj/cm2 で露光し、さらに100℃で1時間および1
50 ℃で3時間加熱処理した。これらの処理により、フ
ォトマスクフィルムに相当する寸法精度に優れた開口4
を有する層間絶縁材層3を形成した(図2(c) 参照)。
(5) The wiring board is moved for about 30
Exposure at 0 mj / cm 2 and further at 100 ° C. for 1 hour and 1 hour
Heat treatment was performed at 50 ° C. for 3 hours. Through these processes, the opening 4 having excellent dimensional accuracy equivalent to a photomask film can be obtained.
(See FIG. 2 (c)).

【0025】(6) 前記配線板をクロム酸に10分間浸漬す
ることにより、層間絶縁材層3の表面を粗化した。さら
に、中和後に水洗および湯洗して、配線板からクロム酸
を除去した。
(6) The surface of the interlayer insulating material layer 3 was roughened by immersing the wiring board in chromic acid for 10 minutes. Further, after neutralization, washing with water and hot water was performed to remove chromic acid from the wiring board.

【0026】(7) 前記配線板を市販のPd−Snコロイド触
媒に浸漬して、開口4の内壁面および粗化された層間絶
縁材層3の表面にPd−Snコロイド5を吸着させ、120 ℃
で30分間加熱処理した。(図2(d) 参照)。
(7) The wiring board is immersed in a commercially available Pd—Sn colloid catalyst to allow the Pd—Sn colloid 5 to be adsorbed on the inner wall surface of the opening 4 and the surface of the roughened interlayer insulating material layer 3. ° C
For 30 minutes. (See FIG. 2 (d)).

【0027】(8) 前記配線板上にドライフィルムフォト
レジストをラミネートすると共に、露光現像を行ってメ
ッキレジスト6を形成した。
(8) A dry film photoresist was laminated on the wiring board and exposed and developed to form a plating resist 6.

【0028】(9) 前記配線板を、還元剤である37%のホ
ルムアルデヒド水溶液に浸漬し、Pdを活性化させた。こ
のときの処理温度は40℃,処理時間は5分である。
(9) The wiring board was immersed in a 37% aqueous formaldehyde solution as a reducing agent to activate Pd. The processing temperature at this time is 40 ° C., and the processing time is 5 minutes.

【0029】(10)前記配線板を表2に示す組成の無電解
めっき液に直ちに浸漬し、その状態で15時間保持するこ
とにより、めっき膜の厚さ約35μm,L/S=75μm/
75μmの導体回路7を備える多層プリント配線板を得た
(図2(e) 参照)。
(10) Immediately immersing the wiring board in an electroless plating solution having the composition shown in Table 2 and maintaining it in that state for 15 hours, the thickness of the plating film was about 35 μm, and the L / S was 75 μm /
A multilayer printed wiring board having a conductor circuit 7 of 75 μm was obtained (see FIG. 2E).

【0030】[0030]

【表2】 [Table 2]

【0031】(実施例2)本実施例では、前記実施例1
とは異なる樹脂組成を採用し、ビルドアップ法により多
層プリント配線板を得た。 (1) フェノールアラルキル型エポキシ樹脂(三井東圧化
学製,商品名:XL−225 L)の50%アクリル化物100
重量部に、ジアリルテレフタレート15重量部、2−メチ
ル−1−〔4−(メチルチオ)フェニル〕−2−モルフ
ォリノプロパノン−1(チバ・ガイギー製,商品名イル
ガキュア−907 )4重量部、イミダゾール系硬化剤(四
国化成製,商品名:2PZ−CN)4重量部および平均粒径
が5.0 μmのメラミン樹脂微粉末(ホーネンコーポレー
ション製)10重量部を配合した。そして、この混合物に
ブチルカルビトールを適量添加して三本ローラで攪拌
し、樹脂絶縁材のワニスとした。
(Embodiment 2) In this embodiment, the first embodiment will be described.
A multilayer printed wiring board was obtained by a build-up method using a different resin composition. (1) 50% acrylate 100 of phenol aralkyl type epoxy resin (Mitsui Toatsu Chemicals, trade name: XL-225 L)
15 parts by weight of diallyl terephthalate, 4 parts by weight of 2-methyl-1- [4- (methylthio) phenyl] -2-morpholinopropanone-1 (manufactured by Ciba-Geigy, trade name Irgacure-907), and imidazole 4 parts by weight of a curing agent (trade name: 2PZ-CN, manufactured by Shikoku Chemicals) and 10 parts by weight of melamine resin fine powder having an average particle diameter of 5.0 μm (manufactured by Honen Corporation) were blended. Then, an appropriate amount of butyl carbitol was added to the mixture, and the mixture was stirred with a three-roller to obtain a varnish of a resin insulating material.

【0032】(2) 内層回路1を形成した後、実施例1と
同様の無電解めっき浴にて厚さ1.5 μmの粗化層2を形
成し、さらにその配線板上に、ギャップコータを用いて
上記のワニスを塗布した後、塗布されたワニスを80℃で
1時間乾燥硬化させ、厚さ70μmの感光性の層間絶縁材
層3を形成した。
(2) After forming the inner layer circuit 1, a roughened layer 2 having a thickness of 1.5 μm is formed in the same electroless plating bath as in Example 1, and a gap coater is formed on the wiring board. After the above varnish was applied, the applied varnish was dried and cured at 80 ° C. for 1 hour to form a photosensitive interlayer insulating material layer 3 having a thickness of 70 μm.

【0033】(3) 上記実施例1の工程(4) 〜(6) に従っ
て、バイアホールとなる開口4の形成および層間絶縁材
層3の表面粗化を行った。なお、層間絶縁材層3の表面
粗化処理には、クロム酸を使用した。
(3) According to the steps (4) to (6) of the first embodiment, the opening 4 serving as a via hole and the surface of the interlayer insulating material layer 3 were roughened. Chromic acid was used for the surface roughening treatment of the interlayer insulating material layer 3.

【0034】(4) 配線板を市販のPd−Snコロイド触媒に
浸漬して、開口4の内壁面および粗化された層間絶縁材
層3の表面にPd−Snコロイド5を吸着させた。
(4) The wiring board was immersed in a commercially available Pd—Sn colloid catalyst, and the Pd—Sn colloid 5 was adsorbed on the inner wall surface of the opening 4 and the surface of the roughened interlayer insulating material layer 3.

【0035】(5) 前記配線板上にドライフィルムレジス
トをラミネートすると共に、露光現像を行ってめっきレ
ジスト6を形成した。
(5) A dry film resist was laminated on the wiring board and exposed and developed to form a plating resist 6.

【0036】(6) 前記配線板をフッ化水素酸−ブドウ糖
水溶液に浸漬し、再度Pdを活性化させた。このときの処
理温度は30℃,処理時間は10分である。
(6) The wiring board was immersed in a hydrofluoric acid-glucose aqueous solution to activate Pd again. The processing temperature at this time is 30 ° C., and the processing time is 10 minutes.

【0037】(7) 前記配線板を、表2に示す組成の無電
解銅めっき液に直ちに浸漬し、その状態で15時間保持す
ることにより、めっき膜の厚さ約35μm,L/S=50μ
m/50μmの導体回路を形成した。
(7) The wiring board was immediately immersed in an electroless copper plating solution having the composition shown in Table 2 and kept in that state for 15 hours to obtain a plating film having a thickness of about 35 μm and L / S = 50 μm.
A conductor circuit of m / 50 μm was formed.

【0038】(8) さらに、レジスト6を除去し、レジス
ト6下に存在した触媒を除去した後、工程(1) 〜(7) を
繰り返すことにより図3に示す片面3層のビルドアップ
多層プリント配線板を得た。
(8) Further, after the resist 6 is removed and the catalyst present under the resist 6 is removed, the steps (1) to (7) are repeated to build up a multi-layer print of three layers on one side shown in FIG. A wiring board was obtained.

【0039】(実施例3)実施例2の工程(1) 〜(8) を
基板両面に繰り返し行うことにより図4に示す6層板の
ビルドアップ多層プリント配線板を得た。
Example 3 By repeating the steps (1) to (8) of Example 2 on both surfaces of the substrate, a six-layer build-up multilayer printed wiring board shown in FIG. 4 was obtained.

【0040】(比較例1)エッチングにより内層回路を
形成した基板表面を、黒化還元処理を施した後、実施例
1と同様に層間絶縁材層を形成し,さらに、粗化し、め
っきすることにより、ビルドアップ多層プリント配線板
を得た。
(Comparative Example 1) After subjecting a substrate surface on which an inner layer circuit was formed by etching to blackening reduction treatment, an interlayer insulating material layer was formed in the same manner as in Example 1, and further roughened and plated. As a result, a build-up multilayer printed wiring board was obtained.

【0041】(比較例2)内層回路形成後、黒化還元処
理を施すことにより、内層回路−黒化還元処理層−絶縁
層−内層回路−黒化還元処理層−絶縁層−外層パターン
という構成の片面3層のビルドアップ多層プリント配線
板を得た。
(Comparative Example 2) A blackening reduction process is performed after the formation of the inner layer circuit, whereby an inner layer circuit—blackening reduction layer—insulating layer—inner circuit—blackening reduction layer—insulating layer—outer layer pattern is formed. Of a single-sided, three-layer build-up multilayer printed wiring board.

【0042】(比較例3)内層回路を形成した基板の両
面に比較例2の構成を作成することにより、6層のビル
ドアップ多層プリント配線板を得た。
Comparative Example 3 A 6-layer build-up multilayer printed wiring board was obtained by forming the structure of Comparative Example 2 on both sides of the substrate on which the inner layer circuit was formed.

【0043】以上のようにして作成したビルドアップ多
層プリント配線板について、−65℃×15分,常温×10
分,125 ℃×15分の気相ヒートサイクル試験による耐ヒ
ートサイクル特性、およびハンダ浴に260 ℃で15秒間浸
漬した後の絶縁層剥離の有無等を調べた。その結果を表
3に示す。
With respect to the build-up multilayer printed wiring board prepared as described above, at −65 ° C. × 15 minutes, normal temperature × 10
The heat cycle resistance was measured by a gas phase heat cycle test at 125 ° C for 15 minutes, and the presence or absence of insulation layer peeling after immersion in a solder bath at 260 ° C for 15 seconds was examined. Table 3 shows the results.

【0044】表3に示す結果から明らかなように、本発
明にかかる多層プリント配線板は、従来技術による配線
板に比べて、耐ヒートサイクル特性が著しく向上するこ
とを確認した。
As is clear from the results shown in Table 3, it was confirmed that the multilayer printed wiring board according to the present invention had significantly improved heat cycle resistance as compared with the conventional wiring board.

【0045】[0045]

【表3】 [Table 3]

【0046】[0046]

【発明の効果】以上説明したように本発明によれば、耐
ヒートサイクル特性に優れた多層プリント配線板を極め
て容易に製造することができる。
As described above, according to the present invention, a multilayer printed wiring board having excellent heat cycle resistance can be manufactured very easily.

【図面の簡単な説明】[Brief description of the drawings]

【図1】Ni−P−Cu共晶めっきにより析出した粗化層の
組成を示す図である。
FIG. 1 is a diagram showing the composition of a roughened layer deposited by Ni-P-Cu eutectic plating.

【図2】本発明の一実施例を示す製造工程図である。FIG. 2 is a manufacturing process diagram showing one embodiment of the present invention.

【図3】実施例2で得られた多層プリント配線板を示す
図である。
FIG. 3 is a diagram showing a multilayer printed wiring board obtained in Example 2.

【図4】実施例3で得られた多層プリント配線板を示す
図である。
FIG. 4 is a diagram showing a multilayer printed wiring board obtained in Example 3.

【符号の説明】[Explanation of symbols]

1 内層回路 2 粗化層(Ni−P−Cu共晶めっき) 3 層間絶縁材層 4 開口 5 Pd−Snコロイド 6 めっきレジスト 7 導体回路 DESCRIPTION OF SYMBOLS 1 Inner layer circuit 2 Roughening layer (Ni-P-Cu eutectic plating) 3 Interlayer insulating material layer 4 Opening 5 Pd-Sn colloid 6 Plating resist 7 Conductor circuit

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 H05K 3/38 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 3/46 H05K 3/38

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基板上に、表面の少なくとも一部に粗化
層を有する導体回路が設けられ、さらにこの導体回路を
含む基板上に層間絶縁材層が設けられ、そしてさらに、
この層間絶縁材層上に他の導体回路が設けられてなる多
層プリント配線板において、 前記粗化層は、Cu,NiおよびPからなる共晶化合物を含
む層で構成されていることを特徴とする多層プリント配
線板。
1. A conductive circuit having a roughened layer on at least a part of a surface is provided on a substrate, and an interlayer insulating material layer is provided on a substrate including the conductive circuit.
In the multilayer printed wiring board in which another conductive circuit is provided on the interlayer insulating material layer, the roughened layer is constituted by a layer containing a eutectic compound composed of Cu, Ni and P. Multi-layer printed wiring board.
【請求項2】 前記粗化層は、90<Cu<100mol%,0<
Ni< 10mol%および0<P< 10mol%からなる共晶化合
物を含む層で構成されていることを特徴とする請求項1
に記載の多層プリント配線板。
2. The roughening layer according to claim 1, wherein 90 <Cu <100 mol%, 0 <
2. A layer comprising a eutectic compound comprising Ni <10 mol% and 0 <P <10 mol%.
2. The multilayer printed wiring board according to item 1.
【請求項3】 前記粗化層は、針状結晶の被膜である請
求項1または2に記載の多層プリント配線板。
3. The multilayer printed wiring board according to claim 1, wherein the roughened layer is a coating of a needle crystal.
【請求項4】 前記粗化層は、その厚さが5μm以下の
被膜である請求項1〜3のいずれか1つに記載の多層プ
リント配線板。
4. The multilayer printed wiring board according to claim 1, wherein the roughened layer is a coating having a thickness of 5 μm or less.
【請求項5】 基板上に設けられた導体回路表面の少な
くとも一部に粗化層を形成し、次いで、前記基板上に層
間絶縁材層を形成し、その後、その層間絶縁材層上に導
体回路を設ける多層プリント配線板の製造方法におい
て、 導体回路が設けられた基板を、少なくともCu化合物、Ni
化合物および次亜リン酸塩を含有する無電解めっき浴中
に浸漬することにより、前記導体回路表面の少なくとも
一部に、Cu,NiおよびPからなる共晶化合物を含む粗化
層を形成することを特徴とする多層プリント配線板の製
造方法。
5. A roughened layer is formed on at least a part of the surface of a conductor circuit provided on a substrate, and then an interlayer insulating material layer is formed on the substrate, and then a conductor is formed on the interlayer insulating material layer. In the method for manufacturing a multilayer printed wiring board provided with a circuit, the substrate provided with the conductor circuit is formed by using at least a Cu compound, Ni
Forming a roughened layer containing a eutectic compound composed of Cu, Ni and P on at least a part of the conductor circuit surface by immersion in an electroless plating bath containing a compound and hypophosphite. A method for manufacturing a multilayer printed wiring board, comprising:
【請求項6】 浴中のCuイオン濃度,Niイオン濃度およ
び次亜リン酸イオン濃度が、それぞれ、 2.2×10-2
4.1×10-2 mol/l,2.2 ×10-3〜 4.1×10-3mol/l,
0.20〜0.25 mol/lであるめっき浴を用いる無電解めっ
きを施すことにより、導体回路表面の少なくとも一部
に、90<Cu<100mol%,0<Ni< 10mol%および0<P
< 10mol%からなる共晶化合物を含む粗化層を形成する
ことを特徴とする請求項5に記載の多層プリント配線板
の製造方法。
6. The bath has a Cu ion concentration, a Ni ion concentration and a hypophosphite ion concentration of 2.2 × 10 −2 to
4.1 × 10 -2 mol / l, 2.2 × 10 -3 to 4.1 × 10 -3 mol / l,
By performing electroless plating using a plating bath of 0.20 to 0.25 mol / l, at least a part of the surface of the conductor circuit has 90 <Cu <100 mol%, 0 <Ni <10 mol% and 0 <P
The method for producing a multilayer printed wiring board according to claim 5, wherein a roughened layer containing a eutectic compound of <10 mol% is formed.
【請求項7】 前記Cu化合物、Ni化合物および次亜リン
酸塩は、それぞれ硫酸銅、硫酸ニッケルおよび次亜リン
酸ナトリウムである請求項5または6に記載の多層プリ
ント配線板の製造方法。
7. The method according to claim 5, wherein the Cu compound, the Ni compound and the hypophosphite are copper sulfate, nickel sulfate and sodium hypophosphite, respectively.
JP24779893A 1993-01-26 1993-10-04 Multilayer printed wiring board and method of manufacturing the same Expired - Fee Related JP3069476B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24779893A JP3069476B2 (en) 1993-01-26 1993-10-04 Multilayer printed wiring board and method of manufacturing the same

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3135993 1993-01-26
JP5-31359 1993-01-26
JP24779893A JP3069476B2 (en) 1993-01-26 1993-10-04 Multilayer printed wiring board and method of manufacturing the same

Publications (2)

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JPH06283860A JPH06283860A (en) 1994-10-07
JP3069476B2 true JP3069476B2 (en) 2000-07-24

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