JPH06283860A - Multilayer printed circuit board and manufacture thereof - Google Patents

Multilayer printed circuit board and manufacture thereof

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Publication number
JPH06283860A
JPH06283860A JP24779893A JP24779893A JPH06283860A JP H06283860 A JPH06283860 A JP H06283860A JP 24779893 A JP24779893 A JP 24779893A JP 24779893 A JP24779893 A JP 24779893A JP H06283860 A JPH06283860 A JP H06283860A
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layer
lt
wiring board
cu
ni
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JP3069476B2 (en )
Inventor
Akihiko Goto
Masahito Kawade
雅人 川出
彰彦 後藤
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Ibiden Co Ltd
イビデン株式会社
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Abstract

PURPOSE:To manufacture a multilayer printed circuit board having excellent heat cycle resistance characteristics by forming a roughed layer of a layer containing eutectic compound made of Cu, Ni and P. CONSTITUTION:Since the strength of eutectic compound itself made of Cu, Ni and P for constituting a roughed layer 2 of eutectic plating is high and the compound is of acicular crystal, the layer 2 has an excellent anchoring effect to bring a conductor circuit 7 into rigid contact with an layer insulating layer 3, and therefore the delamination due to thermal shock scarcely occurs, and heat cycle characteristics are improved. Further, since the layer 2 by eutectic plating is formed of Cu-Ni-P eutectic compound having higher chemical resistance. oxidation resistance, it is not dissolved in a chemical copper plating bath, and can obtain a high contact strength. After a surface of the circuit 7 is roughed, the layer 3 is provided on the board, a recess for a viahole is formed, a circuit is further provided by electroless plating thereby to obtain a multilayer printed board.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は多層プリント配線板およびその製造方法に関し、特に、耐ヒートサイクル特性に優れる多層プリント配線板およびその製造方法について提案する。 BACKGROUND OF THE INVENTION This invention relates to a multilayer printed wiring board and a manufacturing method thereof, in particular, to propose a multilayer printed wiring board and a manufacturing method excellent in heat cycle resistance.

【0002】 [0002]

【従来の技術】配線の高密度化あるいは演算機能の高速化に好適な多層プリント配線板は、近年、導体回路と層間絶縁材層とを交互にビルドアップし、バイアホールなどによって内・外装回路を接続,導通させてなるビルドアップ多層配線板が注目を浴びている。 BACKGROUND OF THE INVENTION wiring density or calculation functions suitable multilayer printed wiring board in the speed of the recent years, to build up a conductor circuit and an interlayer insulating material layer alternately, the inner and outer circuit or the like via holes the connection, the build-up multilayer wiring board formed by conduction has attracted attention. このビルドアップ多層配線板は、主としてアディティブ法により製造されている。 This build-up multilayer wiring board is mainly manufactured by an additive method.

【0003】このアディティブ法は、ガラスエポキシ等の絶縁基板上に無電解めっき用樹脂絶縁材を塗布することにより絶縁材層を形成し、次いでこの絶縁材層の表面を粗化した後、その粗化面にめっきレジストを形成し、 [0003] The additive process, the insulating material layer was formed by coating an electroless plating insulating resin material on an insulating substrate such as glass epoxy, and then after roughening the surface of the insulating material layer, the crude the plating resist is formed on the treatment side,
その後、無電解めっきによって導体回路となる金属を付着させる方法である。 Then, a method of attaching a metal to be a conductor circuit by electroless plating.

【0004】このような方法によると、粗化された絶縁材層上に導体回路をめっき等によって付着させることから、層間絶縁材層とその上に設けられる導体回路との密着性を向上させることができる。 [0004] According to this method, since the deposited by plating the conductor circuit on the roughened insulation layer, to improve the adhesion of the interlayer insulating material layer and a conductor circuit provided thereon can.

【0005】一方で、上記方法において、導体回路とその上に設けられる層間絶縁材層との密着性を改善する手段としては、従来、導体回路表面を酸化、還元して、表面を粗化する、いわゆる黒化・還元処理が行われている。 [0005] On the other hand, in the above method, as a means for improving the adhesion between the interlayer insulating material layer provided thereon a conductor circuit, conventionally, oxidizing the conductor circuit surface is reduced, roughening the surface , the so-called blackening-reduction processing is performed. このような黒化・還元処理を行うと、導体回路の表面が粗化され、この粗化面がアンカーとなって、層間絶縁材層と導体回路との結合を物理的に強化させることができる。 Doing so blackening-reduction process, the surface of the conductor circuit is roughened, the roughened surface becomes an anchor, it is possible to strengthen the bond between the interlayer insulation layer and the conductor circuit physically .

【0006】 [0006]

【発明が解決しようとする課題】しかしながら、導体回路とその上に設けられる層間絶縁材層との密着性は、上述したような黒化・還元処理技術を用いても、なお不十分であり、環境の厳しい条件下では、プリント配線板の耐ヒートサイクル特性に欠けるという問題があった。 [SUMMARY OF THE INVENTION However, adhesion between the interlayer insulating material layer provided thereon a conductor circuit, even with blackening-reduction techniques, such as described above, Note is insufficient, the severe conditions of the environment, there is a problem of lack of heat cycle resistance of the printed wiring board. 例えば、−6℃〜150 ℃の MIL−883 に準じた条件下での試験によると、プリント配線板の耐ヒートサイクル特性は、層間絶縁材層が剥離を生じない最大サイクル数で30 For example, according to the test under the conditions according to MIL-883 of -6 ° C. to 150 DEG ° C., heat cycle resistance of the printed wiring board, the maximum number of cycles interlayer insulation layer is not peeling occurred 30
0 サイクル程度であった。 0 was about cycle.

【0007】そこで本発明の目的は、従来技術が抱える上記問題を解決することにあり、特に、耐ヒートサイクル特性に優れる多層プリント配線板およびその製造技術を提供することにある。 [0007] Accordingly, an object of the present invention is to solve the above problems the prior art has faced, in particular to provide a multilayer printed circuit board and a manufacturing technique which is excellent in heat cycle resistance.

【0008】 [0008]

【課題を解決するための手段】発明者らは、上記目的の実現に向け鋭意研究した結果、導体回路と層間絶縁材層との界面に針状結晶の無電解めっき皮膜からなる粗化層を設けることにより、上記目的を実現できることを見出し、本発明に想到した。 We SUMMARY OF THE INVENTION As a result of extensive studies for the realization of the object, roughened layer made of electroless plated film interface needle crystals of the conductor circuit and the interlayer insulating material layer by providing, it found that can achieve the above object, and conceived the present invention.

【0009】すなわち、本発明は、基板上に、表面の少なくとも一部に粗化層を有する導体回路が設けられ、さらにこの導体回路を含む基板上には層間絶縁材層が設けられ、そしてさらに、この層間絶縁材層上には他の導体回路が設けられてなる多層プリント配線板において、前記粗化層は、Cu,NiおよびP、好ましくは90<Cu<100m Accordingly, the present invention has, on a substrate, at least a portion of the surface conductor circuit is provided with a roughened layer, and further on the substrate including the conductive circuit is provided an interlayer insulation layer, and further in the multilayer printed wiring board comprising other conductor circuit is provided in the interlayer insulation layer, the roughened layer, Cu, Ni and P, preferably 90 <Cu <100 m
ol%,0<Ni< 10mol%および0<P< 10mol%からなる共晶化合物を含む層で構成されていることを特徴とする多層プリント配線板であり、前記粗化層は、針状結晶の被膜であり、その厚さが5μm以下の被膜であることが望ましい。 ol%, a multilayer printed wiring board, characterized in that it is constituted by a layer containing 0 <Ni <10mol% and 0 <P <consisting 10 mol% eutectic compound, it said roughened layer is acicular crystals a coating, it is desirable that thickness is less film 5 [mu] m. そして、上記多層プリント配線板の製造方法は、基板上に設けられた導体回路表面の少なくとも一部に粗化層を形成し、次いで、前記基板上に層間絶縁材層を形成し、その後、その層間絶縁材層上に導体回路を設ける多層プリント配線板の製造方法において、導体回路が設けられた基板を、少なくともCu化合物、Ni化合物および次亜リン酸塩を含有する無電解めっき浴中に浸漬することにより、前記導体回路表面の少なくとも一部に、Cu,NiおよびPからなる共晶化合物を含む粗化層を形成することを特徴とする多層プリント配線板の製造方法であり、浴中のCuイオン濃度,Niイオン濃度および次亜リン酸イオン濃度が、それぞれ、 2.2×10 -2 〜 4.1× The method for manufacturing the multilayer printed wiring board forms a roughened layer on at least part of the conductor circuit surface provided on the substrate, then, an interlayer insulating material layer on the substrate, after which the immersion method of manufacturing a multilayer printed circuit board providing a conductor circuit on the interlayer insulation layer, the substrate on which the conductor circuit is provided, at least Cu compound, in an electroless plating bath containing Ni compound and hypophosphite by, at least a portion of the conductive circuit surface, Cu, a method for manufacturing a multilayer printed wiring board, which comprises forming a roughened layer comprising a eutectic compound of Ni and P, in the bath Cu ion concentration, Ni ion concentration and hypophosphite ion concentration, respectively, 2.2 × 10 -2 ~ 4.1 ×
10 -2 mol/l,2.2 ×10 -3 〜 4.1×10 -3 mol/l,0.20 10 -2 mol / l, 2.2 × 10 -3 ~ 4.1 × 10 -3 mol / l, 0.20
〜0.25 mol/lであるめっき浴を用いる無電解めっき(共晶めっき)を施すことにより、導体回路表面の少なくとも一部に、90<Cu<100mol%,0<Ni< 10mol%および0<P< 10mol%からなる共晶化合物を含む粗化層を形成することが望ましく、また、前記Cu化合物、Ni化合物および次亜リン酸塩は、それぞれ硫酸銅、硫酸ニッケルおよび次亜リン酸ナトリウムであることが望ましい。 By electroless plating (eutectic plating) using plating bath is to 0.25 mol / l, at least a portion of the conductor circuit surface, 90 <Cu <100mol%, 0 <Ni <10mol% and 0 <P <it is desirable to form the roughened layer comprising a eutectic compound consisting of 10 mol%, also the Cu compound, Ni compound and hypophosphite, copper sulfate respectively, are nickel sulfate and sodium hypophosphite it is desirable. なお、本発明では、導体回路が設けられた基板は、 The substrate in the present invention, the conductor circuit is provided,
多層基板であっても差支えない。 No problem even in the multi-layer substrate.

【0010】 [0010]

【作用】黒化還元処理による粗化層は、銅表面を酸化して酸化銅を形成させることにより得られるが、この粗化層を構成する酸化銅の強度が低く、それ故に、熱衝撃により破壊されて層間剥離を起こしやすい。 [Action] roughened layer by a blackening-reduction process is by oxidizing the copper surface can be obtained by forming the copper oxide, the strength of the copper oxide constituting the roughened layer is low, therefore, the thermal shock prone to delamination been destroyed. この点、本発明の共晶めっきによる粗化層は、この粗化層を構成する In this regard, the roughened layer by the eutectic plating of the present invention constitutes the roughened layer
Cu,NiおよびPからなる共晶化合物自体の強度が高く、 Cu, high strength eutectic compound itself consisting of Ni and P,
しかも、針状結晶であるためにアンカーとしての効果に優れ、導体回路と層間絶縁材層とを強固に密着させることができ、それ故に、熱衝撃による層間剥離が生じにくく、耐ヒートサイクル特性が向上する。 Moreover, excellent effects as an anchor for a needle-like crystals, a conductor circuit and an interlayer insulating material layer can be firmly adhered, therefore, delamination does not easily occur due to thermal shock, is heat cycle resistance improves. さらに、黒化還元処理による粗化層は、酸化銅または銅が表面に曝露されているために、化学銅めっき浴のアルカリ液で溶解し、いわゆるハローイング現象を生じやすく、しかも、 Moreover, the roughened layer by a blackening-reduction process, in order to copper oxide or copper is exposed on the surface, was dissolved in an alkaline solution of chemical copper plating bath, prone to so-called haloing phenomenon, moreover,
銅表面が酸化されたりする。 The copper surface or oxidized. この点、本発明の共晶めっきによる粗化層は、Cuに比べて耐薬品性・耐酸化性が高いCu−Ni−P共晶化合物で形成されているため、化学銅めっき浴中で溶解したり酸化したりせず、高い密着力を確保できる。 In this regard, the roughened layer by the eutectic plating of the present invention, since the chemical resistance and oxidation resistance than Cu is formed with high Cu-Ni-P eutectic compound, dissolved in a chemical copper plating bath without or or oxide, it can be secured high adhesion. 以上説明したように本発明の多層プリント配線板は、導体回路と層間絶縁材層の界面に設けられる無電解めっき膜からなる粗化層が、Cu,NiおよびPからなる共晶化合物である点に特徴がある。 Above multilayer printed wiring board of the present invention as described, the point roughened layer made of an electroless plated film provided at the interface of the conductor circuit and the interlayer insulating material layer is a eutectic compound consisting of Cu, Ni and P it is characterized in.

【0011】ここに、本発明において、上記共晶化合物は、図1の斜線で示した範囲、すなわち、90<Cu<100m [0011] Here, in the present invention, the eutectic compound range shown by oblique lines in FIG. 1, i.e., 90 <Cu <100 m
ol%,0<Ni< 10mol%および0<P< 10mol%からなることが好ましい。 ol%, 0 <Ni <preferably consists of 10 mol% and 0 <P <10mol%. この理由は、Cuが90 mol%以下だと析出皮膜の結晶が粉状になり、Niが 10mol%以上だと析出皮膜の結晶が粉状になると共に導電性が悪くなり、P This is because, Cu becomes crystal powdery deposit film that it 90 mol% or less, Ni is poor conductivity with crystals of precipitated film's least 10 mol% is powdery, P
が 10mol%以上だと抵抗値が高くなり針状結晶となりにくいからである。 There is not easily become acicular crystals increases the resistance that it more than 10 mol%. すなわち、上記組合せにおいて、析出被膜の結晶が針状構造になり、アンカー効果に優れる構造となるからである。 That is because in the above combination, the deposition coating crystals become acicular structure, a structure having an excellent anchor effect.

【0012】本発明において、上記粗化層は、その厚さが5μm以下の皮膜であることが望ましく、特に0.5 μ [0012] In the present invention, the roughened layer is desirably the thickness is less film 5 [mu] m, particularly 0.5 mu
m〜2μmの範囲が好適である。 Range of m~2μm is preferred. この理由は、0.5 μm The reason for this is, 0.5 μm
未満では、アンカー効果が低く、一方、5μm超では、 In the anchor effect is low, while in 5μm greater than,
表面粗度が大きくなりすぎ、却って密着強度が低下してしまうからである。 Surface roughness becomes too large, because rather adhesion strength is lowered.

【0013】なお、本発明の多層プリント配線板は、基板上の導体回路と層間絶縁材層上に設けられた他の導体回路とが、バイアホールやスルーホールで電気的に接続されていてもよい。 [0013] Incidentally, the multilayer printed wiring board of the present invention, the other of the conductor circuit provided in the conductor circuit and the interlayer insulating material layer on the substrate, be electrically connected with via holes or through holes good. 但し、バイアホールで接続する場合、接続箇所の粗化層は、予め除去されているか、粗化層を設けないことが望ましい。 However, when connecting with the via hole, rough layer connection points are either removed in advance, it is desirable not to provide a roughened layer. その理由は、接続箇所に粗化層があると、わずかではあるが抵抗が高くなるからである。 The reason is that there is a roughened layer in the connection point, because small but the resistance is increased.

【0014】本発明において、層間絶縁材層として用いる樹脂絶縁材は、酸もしくは酸化剤に対して難溶性の樹脂からなるマトリックス中に酸もしくは酸化剤に対して可溶性の硬化処理された耐熱性樹脂粉末を分散してなるものであることが望ましい。 [0014] In the present invention, the resin insulating material is used as an interlayer insulating material layer, acid or were cured soluble in the acid or oxidizing agent in a matrix comprising a hardly soluble resin relative to the oxidant heat-resistant resin it is desirable powder is made by dispersing. この理由は、上記樹脂絶縁材を用いて得られる層間絶縁材層は、酸あるいは酸化剤によって容易に粗化面を設けることができ、層間絶縁材層とその上に無電解めっきにより設けられる導体回路との密着性を向上させることができるからである。 This is because, the resin insulating material of the interlayer insulating material layer obtained by using the acid or can be easily provided roughened surface by an oxidizing agent, a conductor provided by electroless plating interlayer insulation layer and thereon This is because it is possible to improve the adhesion between the circuit. このような粗化面を形成するためのアンカー形成用耐熱性樹脂粉末は、例えば、平均粒径10μm以下の耐熱性樹脂粉末、平均粒径2μm以下の耐熱性樹脂粉末を凝集させて平均粒径2〜10μmの大きさとした凝集粒子、平均粒径2〜10μmの耐熱性樹脂粉末と平均粒径2μm以下の耐熱性樹脂粉末との混合物、平均粒径2〜10μmの耐熱性樹脂粉末の表面に、平均粒径2μm以下の耐熱性樹脂粉末もしくは平均粒径2μm以下の無機粉末のいずれか少なくとも1種を付着させてなる擬似粒子、から選ばれることが好適である。 Anchor formation for heat-resistant resin powder for forming such roughened surface, for example, an average particle diameter of 10μm or less of the heat-resistant resin powder, by aggregating the following heat-resistant resin powder having an average particle size of 2μm average particle size the size and the agglomerated particles of 2 to 10 [mu] m, a mixture of heat-resistant resin powder and the average particle size 2μm or less of the heat-resistant resin powder having an average particle size of 2 to 10 [mu] m, the surface of the heat-resistant resin powder having an average particle diameter of 2 to 10 [mu] m , it is preferred that is selected from the pseudo-particles comprising by adhering at least one one of the average particle size of 2μm or less of the heat-resistant resin powder or an average particle size of 2μm or less of the inorganic powder. なお、形成されるアンカーの形状や深さについては、粒径の異なる樹脂粉末にて表面粗度が1〜20μmの範囲内になるようにすることが望ましく、かかる場合に、導体の十分な密着強度が得られる。 Note that the shape and depth of anchor formed, it is desirable that the surface roughness at different particle sizes resin powder is set to be in the range of 1 to 20 [mu] m, according to the case, sufficient adhesion of the conductor strength can be obtained. また、上記樹脂絶縁材を構成するマトリックス樹脂は、感光特性を示すものであることが望ましい。 Further, the matrix resin constituting the resin insulating material is desirably shows the photosensitive characteristics. これは、感光特性を示す樹脂を用いることにより、露光、現像で容易にバイアホールを形成できるからである。 This can be achieved by using a resin that shows a photosensitive characteristic, exposure, because easily form via holes in development.

【0015】次に、本発明の多層プリント配線板の製造方法について説明する。 [0015] Next, a method for manufacturing a multilayer printed wiring board of the present invention. 本発明の製造方法は、導体回路が設けられた基板を、少なくともCu化合物、Ni化合物および次亜リン酸塩を含有するめっき浴中に浸漬して無電解めっきを施すことにより、前記導体回路表面の少なくとも一部に、Cu,NiおよびPからなる共晶化合物を含む粗化層を形成する点に特徴がある。 Production method of the present invention, the substrate on which the conductor circuit is provided, at least Cu compound, by subjecting the immersion to the electroless plating in a plating bath containing Ni compound and hypophosphite, said conductor circuit surface at least a portion, Cu, is characterized in that to form a roughened layer comprising a eutectic compound of Ni and P of. これによれば、無電解めっきによって析出する皮膜の結晶は、針状結晶構造のCu、NiおよびPからなる共晶化合物となり、この針状結晶構造が、導体回路とその上に設けられる層間絶縁材層との密着性を向上させるアンカー効果として作用する。 According to this, the crystal of the film deposited by electroless plating, Cu needles structure becomes a eutectic compound of Ni and P, the needle-like crystal structure, an interlayer insulating provided thereon a conductor circuit It acts as an anchor effect of improving the adhesion to the wood layer.

【0016】ここで、上記無電解めっき浴中のCuイオン濃度,Niイオン濃度および次亜リン酸イオン濃度は、それぞれ、 2.2×10 -2 〜 4.1×10 -2 mol/l,2.2 ×10 -3 [0016] Here, the Cu ion concentration in an electroless plating bath, Ni ion concentration and hypophosphite ion concentration, respectively, 2.2 × 10 -2 ~ 4.1 × 10 -2 mol / l, 2.2 × 10 - 3
〜 4.1×10 -3 mol/l,0.20〜0.25 mol/lであることが望ましい。 ~ 4.1 × 10 -3 mol / l , it is desirable that 0.20 to 0.25 mol / l. この理由は、上記範囲内で、析出する皮膜の結晶構造が針状構造になるため、アンカー効果に優れるからである。 This is because, within the above range, the crystal structure of the precipitated coating to become a needle-like structure, is excellent in the anchor effect. なお、無電解めっき浴には、上記化合物の他に錯化剤や添加剤等を適宜添加してもよい。 Note that the electroless plating bath in addition to may be appropriately added a complexing agent and additives such as the above-mentioned compounds. また、 Also,
無電解めっきを施す前には、Pdなどの触媒核を予め付与しておいてもよい。 Before electroless plating may be previously granted catalyst nucleus such as Pd.

【0017】上記無電解めっきの条件は、浴温度が60〜 [0017] The above-mentioned electroless plating conditions, the bath temperature is 60
80℃、析出速度が1〜1.5 μm/10分、浴比が0.5 〜1. 80 ° C., the deposition rate is 1 to 1.5 [mu] m / 10 min, the bath ratio is 0.5-1.
0 dm 2 /l、浴pHが8〜10、めっき時間が5〜20分であることが望ましい。 0 dm 2 / l, the bath pH is 8 to 10, it is desirable that the plating time is 5-20 minutes. これは、上記条件を逸脱すると、 This is because out of the above condition,
析出するめっき被膜が、緻密にならず、耐ヒートサイクル特性が著しく低下してしまうからである。 Plating film to be deposited is not dense because the heat cycle resistance decreases significantly.

【0018】本発明方法においては、基板上の導体回路表面に粗化層を形成する上記処理を終えた後、この導体回路を含む基板上に層間絶縁材層を設け、これにバイアホール用の凹部やスルーホール用の貫通孔を形成し、そしてさらに、この層間絶縁材層上に、必要に応じてめっきレジストを形成し、無電解めっきにより他の導体回路を設け、多層プリント配線板を得る。 In [0018] The present invention method, after finishing the process of forming a roughened layer on the conductor circuit surface of the substrate, provided an interlayer insulating material layer on a substrate including the conductive circuit, to which the via-hole forming a through hole in the recess and the through hole, and further, in the interlayer insulation layer, a plating resist is formed as needed, provided the other conductor circuit by electroless plating, to obtain a multilayer printed circuit board . ここで、バイアホールにより上層と下層の導体回路を接続する場合には、 Here, in the case of connecting the conductor circuits of the upper and lower layers by the via holes,
接続箇所の粗化層は、予め除去されているか、粗化層を下層の導体回路に設けないことが必要である。 Roughened layer connection points are either previously removed, it is necessary not to provide a roughened layer in the lower layer of conductor circuit. このためには、無電解めっきにより導体回路表面に粗化層を設ける前に、バイアホールにより接続される導体回路部分をマスクしておく方法がよい。 For this purpose, prior to providing a roughened layer on the conductor circuit surface by electroless plating, it is a method to keep masks the conductor circuit portions connected by via holes. なお、本発明における上層ならびに内層の導体回路は、常法に従い設けることができる。 Incidentally, the conductor circuit of the upper layer and the inner layer in the present invention can be provided in a conventional manner. 以下、実施例について詳細に説明する。 It will be described in detail for Example.

【0019】 [0019]

【実施例】(実施例1)ビルドアップ法による多層プリント配線板を、以下に示す製造工程(1) 〜(10)にしたがって得た。 EXAMPLES (Example 1) a multilayer printed circuit board according to the build-up method, obtained according to the manufacturing steps described below (1) to (10). (1) 銅張積層板をエッチングして内層回路1を形成した後、その基板を酸性脱脂し、ソフトエッチングし、Cu上にPd触媒を置換付与し、活性化した後、表1に示す組成の無電解めっき浴にてめっきを施し、Ni−P−Cu共晶の厚さ1μmの粗化層2を得た。 (1) forming an inner layer circuit 1 a copper clad laminate by etching, the substrate was acidic degreasing and soft etching, the Pd catalyst was replaced applied on Cu, after activation, the composition shown in Table 1 the plating performed in an electroless plating bath to obtain a roughened layer 2 having a thickness of 1μm of the Ni-P-Cu eutectic. この粗化層2の組成は、 The composition of the roughened layer 2,
EPMA(蛍光X線分析器)で分析した結果、Cu;98 mol Was analyzed by EPMA (fluorescent X-ray analyzer), Cu; 98 mol
%、Ni;1.5mol%、P;0.5mol%であった。 %, Ni; 1.5mol%, P; was 0.5 mol%.

【0020】 [0020]

【表1】 [Table 1]

【0021】(2) クレゾールノボラック型エポキシ樹脂(油化シェル製,商品名:エピコート180S)50%アクリル化物60重量部に、ビスフェノールA型エポキシ樹脂(油化シェル製,商品名:E-1001)40重量部、ジアリルテレフタレート15重量部、2−メチル−1−〔4−(メチルチオ)フェニル〕2−モルフォリノプロパノン−1 [0021] (2) a cresol novolak type epoxy resin (made by Yuka Shell Co., Ltd. trade name: Epikote 180S) to 60 parts by weight of 50% acrylated product of a bisphenol A type epoxy resin (made by Yuka Shell Co., Ltd. trade name: E-1001) 40 parts by weight, 15 parts by weight of diallyl terephthalate, 2-methyl-1- [4- (methylthio) phenyl] 2-morpholinopropanone--1
(チバ・ガイギー製,商品名:イルガキュア−907 )4 (Manufactured by Ciba-Geigy Ltd., trade name: Irgacure -907) 4
重量部、粒径が5.5 μmのエポキシ樹脂微粉末(東レ製)10重量部、および粒径が0.5 μmのエポキシ樹脂微粉末(東レ製)25重量部を配合した。 Parts by weight, particle size 5.5 [mu] m of epoxy resin fine powder (made by Toray) 10 parts by weight, and particle size were blended with 0.5 [mu] m of epoxy resin fine powder (made by Toray) 25 parts by weight. そして、この混合物にブチルセロソルブを適量添加しながらホモディスパー攪拌機で攪拌し、樹脂絶縁材のワニスを作成した。 Then, butyl cellosolve to the mixture and stirred with an appropriate amount while adding a homodisper stirrer to prepare a varnish of the insulating resin.

【0022】(3) ロールコータを用いて内層回路1上に上記のワニスを塗布した後、塗布されたワニスを100 ℃ [0022] (3) After applying the varnish on the inner layer circuit 1 using a roll coater, 100 ° C. The coated varnish
で1時間乾燥硬化させ、厚さ50μmの感光性の層間絶縁材層3を形成した(図2(b) 参照)。 In one hour of dry cured to form a photosensitive interlayer insulating material layer 3 having a thickness of 50 [mu] m (see Figure 2 (b)).

【0023】(4) 前記工程(3) の処理を施した配線板に、直径100 μmの黒円および打ち抜き切断部位が黒く印刷されたフォトマスクフィルムを密着させ、超高圧水銀灯により500 mj/cm 2で露光した。 [0023] (4) in the circuit board process subjected to the step (3), is adhered a photomask film black circles and punching cleavage sites diameter 100 [mu] m is printed in black, the ultra-high pressure mercury lamp 500 mj / cm It was exposed by two. これをクロロセン溶液で超音波現像処理することにより配線板上に直径100 μmのバイアホールとなる開口4を形成した。 This was to form openings 4 as a via-hole having a diameter of 100 [mu] m on a wiring board by ultrasonic developed in Kurorosen solution.

【0024】(5) 前記配線板を超高圧水銀灯により約30 [0024] (5) about 30 to the wiring board to a super-high pressure mercury lamp
0 mj/cm 2で露光し、さらに100℃で1時間および1 0 exposed with mj / cm 2, 1 hour and 1 for a further 100 ° C.
50 ℃で3時間加熱処理した。 It was heat-treated for 3 hours at 50 ° C.. これらの処理により、フォトマスクフィルムに相当する寸法精度に優れた開口4 By these processes, an opening 4 having excellent dimensional accuracy corresponding to the photomask film
を有する層間絶縁材層3を形成した(図2(c) 参照)。 Forming an interlayer insulating material layer 3 having a (see FIG. 2 (c)).

【0025】(6) 前記配線板をクロム酸に10分間浸漬することにより、層間絶縁材層3の表面を粗化した。 [0025] (6) by dipping for 10 minutes in chromic acid the wiring board, to roughen the surface of the interlayer insulation layer 3. さらに、中和後に水洗および湯洗して、配線板からクロム酸を除去した。 Furthermore, it washed with water and hot water after neutralization to remove chromic acid from the circuit board.

【0026】(7) 前記配線板を市販のPd−Snコロイド触媒に浸漬して、開口4の内壁面および粗化された層間絶縁材層3の表面にPd−Snコロイド5を吸着させ、120 ℃ [0026] (7) The wiring board was immersed in a commercially available Pd-Sn colloid catalyst to adsorb the Pd-Sn colloid 5 on the inner wall surface and roughened surface of the interlayer insulation layer 3 of the opening 4, 120 ℃
で30分間加熱処理した。 In was heated for 30 minutes. (図2(d) 参照)。 (See Figure 2 (d)).

【0027】(8) 前記配線板上にドライフィルムフォトレジストをラミネートすると共に、露光現像を行ってメッキレジスト6を形成した。 [0027] (8) as well as laminating a dry film photoresist on the wiring board, thereby forming a plating resist 6 is subjected to exposure development.

【0028】(9) 前記配線板を、還元剤である37%のホルムアルデヒド水溶液に浸漬し、Pdを活性化させた。 [0028] (9) The wiring board was immersed in 37% aqueous formaldehyde solution as a reducing agent, to activate the Pd. このときの処理温度は40℃,処理時間は5分である。 Treatment temperature at this time is 40 ° C., the treatment time is 5 minutes.

【0029】(10)前記配線板を表2に示す組成の無電解めっき液に直ちに浸漬し、その状態で15時間保持することにより、めっき膜の厚さ約35μm,L/S=75μm/ [0029] (10) wherein the wiring board immediately immersed in an electroless plating solution having the composition shown in Table 2, by holding for 15 hours in this state, a thickness of about 35μm of the plating film, L / S = 75μm /
75μmの導体回路7を備える多層プリント配線板を得た(図2(e) 参照)。 To obtain a multilayer printed circuit board comprising a conductor circuit 7 of 75 [mu] m (see FIG. 2 (e)).

【0030】 [0030]

【表2】 [Table 2]

【0031】(実施例2)本実施例では、前記実施例1 [0031] (Example 2) In this example, Example 1
とは異なる樹脂組成を採用し、ビルドアップ法により多層プリント配線板を得た。 Adopt different resin composition and to obtain a multilayer printed circuit board by a build-up method. (1) フェノールアラルキル型エポキシ樹脂(三井東圧化学製,商品名:XL−225 L)の50%アクリル化物100 (1) a phenol aralkyl type epoxy resin (manufactured by Mitsui Toatsu Chemicals, trade name: XL-225 L) 50% acrylated product of 100
重量部に、ジアリルテレフタレート15重量部、2−メチル−1−〔4−(メチルチオ)フェニル〕−2−モルフォリノプロパノン−1(チバ・ガイギー製,商品名イルガキュア−907 )4重量部、イミダゾール系硬化剤(四国化成製,商品名:2PZ−CN)4重量部および平均粒径が5.0 μmのメラミン樹脂微粉末(ホーネンコーポレーション製)10重量部を配合した。 The parts by weight, 15 parts by weight of diallyl terephthalate, 2-methyl-1- [4- (methylthio) phenyl] -2-morpholinopropanone-1 (Ciba-Geigy, Irgacure -907) 4 parts by weight, imidazole curing agent (made by Shikoku Kasei Co., Ltd. trade name: 2PZ-CN) 4 parts by weight and average particle size 5.0 [mu] m of melamine resin fine powder (manufactured by Honen) was blended with 10 parts by weight. そして、この混合物にブチルカルビトールを適量添加して三本ローラで攪拌し、樹脂絶縁材のワニスとした。 Then, butyl carbitol to this mixture was stirred with a three-roller add an appropriate amount to obtain a varnish of a resin insulating material.

【0032】(2) 内層回路1を形成した後、実施例1と同様の無電解めっき浴にて厚さ1.5 μmの粗化層2を形成し、さらにその配線板上に、ギャップコータを用いて上記のワニスを塗布した後、塗布されたワニスを80℃で1時間乾燥硬化させ、厚さ70μmの感光性の層間絶縁材層3を形成した。 [0032] (2) After the formation of the inner circuit 1, Example 1 and forming the thickness 1.5 [mu] m roughened layer 2 by the same electroless plating bath, the more the wiring board, using a gap coater after coating the varnish Te, the coated varnish is dried for 1 hour curing at 80 ° C., to form a photosensitive interlayer insulating material layer 3 having a thickness of 70 [mu] m.

【0033】(3) 上記実施例1の工程(4) 〜(6) に従って、バイアホールとなる開口4の形成および層間絶縁材層3の表面粗化を行った。 [0033] (3) according to the above Example 1, step (4) to (6) was subjected to a surface roughening of the formation of the opening 4 as a via hole and the interlayer insulation layer 3. なお、層間絶縁材層3の表面粗化処理には、クロム酸を使用した。 Incidentally, the surface roughening treatment of the interlayer insulating material layer 3, was used chromic acid.

【0034】(4) 配線板を市販のPd−Snコロイド触媒に浸漬して、開口4の内壁面および粗化された層間絶縁材層3の表面にPd−Snコロイド5を吸着させた。 [0034] (4) by immersing the circuit board in a commercial Pd-Sn colloid catalyst, was on the inner wall surface and roughened surface of the interlayer insulation layer 3 of the opening 4 to adsorb Pd-Sn colloid 5.

【0035】(5) 前記配線板上にドライフィルムレジストをラミネートすると共に、露光現像を行ってめっきレジスト6を形成した。 [0035] (5) with laminating a dry film resist on the wiring board, thereby forming a plating resist 6 is subjected to exposure development.

【0036】(6) 前記配線板をフッ化水素酸−ブドウ糖水溶液に浸漬し、再度Pdを活性化させた。 [0036] (6) the wiring board hydrofluoric acid - was immersed in aqueous glucose solution was activated again Pd. このときの処理温度は30℃,処理時間は10分である。 Treatment temperature at this time is 30 ° C., the treatment time is 10 minutes.

【0037】(7) 前記配線板を、表2に示す組成の無電解銅めっき液に直ちに浸漬し、その状態で15時間保持することにより、めっき膜の厚さ約35μm,L/S=50μ [0037] (7) the wiring board, immediately immersed in an electroless copper plating solution having the composition shown in Table 2, by holding for 15 hours in this state, a thickness of about 35μm of the plating film, L / S = 50μ
m/50μmの導体回路を形成した。 To form a conductor circuit of m / 50 [mu] m.

【0038】(8) さらに、レジスト6を除去し、レジスト6下に存在した触媒を除去した後、工程(1) 〜(7) を繰り返すことにより図3に示す片面3層のビルドアップ多層プリント配線板を得た。 [0038] (8) Further, the resist 6 is removed, after removing the present catalyst under the resist 6, step (1) to the single-sided, triple-layer shown in FIG. 3 by repeating (7) build-up multilayer printed to obtain a wiring board.

【0039】(実施例3)実施例2の工程(1) 〜(8) を基板両面に繰り返し行うことにより図4に示す6層板のビルドアップ多層プリント配線板を得た。 [0039] was obtained (Example 3) Example 2 step (1) to (8) a build-up multilayer printed wiring board of six-layer board shown in FIG. 4 by repeating on both surfaces of the substrate.

【0040】(比較例1)エッチングにより内層回路を形成した基板表面を、黒化還元処理を施した後、実施例1と同様に層間絶縁材層を形成し,さらに、粗化し、めっきすることにより、ビルドアップ多層プリント配線板を得た。 [0040] (Comparative Example 1) substrate surface formed the inner layer circuit by etching, after performing blackening reduction treatment, similarly form an interlayer insulating material layer as in Example 1, further, coarse turned into, it is plated gave a build-up multi-layer printed wiring board.

【0041】(比較例2)内層回路形成後、黒化還元処理を施すことにより、内層回路−黒化還元処理層−絶縁層−内層回路−黒化還元処理層−絶縁層−外層パターンという構成の片面3層のビルドアップ多層プリント配線板を得た。 [0041] (Comparative Example 2) After inner layer circuit formed by performing blackening reduction treatment, the inner layer circuit - blackening reduction layer - insulating layer - inner layer circuit - blackening reduction layer - configuration of the outer layer pattern - insulating layer of obtaining a build-up multilayer printed wiring board of the single-sided, triple-layer.

【0042】(比較例3)内層回路を形成した基板の両面に比較例2の構成を作成することにより、6層のビルドアップ多層プリント配線板を得た。 [0042] By creating the configuration of the comparative example 2 on both surfaces of a substrate formed (Comparative Example 3) an inner layer circuit, to obtain a build-up multilayer printed wiring board of six-layer.

【0043】以上のようにして作成したビルドアップ多層プリント配線板について、−65℃×15分,常温×10 [0043] The build-up multi-layer printed wiring board was created as described above, -65 ℃ × 15 minutes, at room temperature × 10
分,125 ℃×15分の気相ヒートサイクル試験による耐ヒートサイクル特性、およびハンダ浴に260 ℃で15秒間浸漬した後の絶縁層剥離の有無等を調べた。 Min, was examined 125 ° C. × 15 minutes heat cycle resistance by the vapor phase heat cycle test, and the presence or absence of the insulating layer delamination after immersion for 15 seconds at 260 ° C. in a solder bath or the like. その結果を表3に示す。 The results are shown in Table 3.

【0044】表3に示す結果から明らかなように、本発明にかかる多層プリント配線板は、従来技術による配線板に比べて、耐ヒートサイクル特性が著しく向上することを確認した。 As it is apparent from the results shown in Table 3, the multilayer printed wiring board according to the present invention, as compared with the wiring board according to the prior art, it was confirmed that the heat cycle resistance is remarkably improved.

【0045】 [0045]

【表3】 [Table 3]

【0046】 [0046]

【発明の効果】以上説明したように本発明によれば、耐ヒートサイクル特性に優れた多層プリント配線板を極めて容易に製造することができる。 According to the present invention as described in the foregoing, it is possible to extremely easily produce a multilayer printed wiring board having excellent heat cycle resistance.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】Ni−P−Cu共晶めっきにより析出した粗化層の組成を示す図である。 1 is a diagram showing the composition of the roughened layer deposited by Ni-P-Cu eutectic plating.

【図2】本発明の一実施例を示す製造工程図である。 2 is a manufacturing process diagram showing an embodiment of the present invention.

【図3】実施例2で得られた多層プリント配線板を示す図である。 3 is a diagram showing a multilayer printed wiring board obtained in Example 2.

【図4】実施例3で得られた多層プリント配線板を示す図である。 4 is a diagram showing a multilayer printed wiring board obtained in Example 3.

【符号の説明】 DESCRIPTION OF SYMBOLS

1 内層回路 2 粗化層(Ni−P−Cu共晶めっき) 3 層間絶縁材層 4 開口 5 Pd−Snコロイド 6 めっきレジスト 7 導体回路 1 inner circuit 2 Arakaso (Ni-P-Cu eutectic plating) 3 interlayer insulation layer 4 opening 5 Pd-Sn colloid 6 plating resist 7 conductor circuit

Claims (7)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 基板上に、表面の少なくとも一部に粗化層を有する導体回路が設けられ、さらにこの導体回路を含む基板上に層間絶縁材層が設けられ、そしてさらに、 To 1. A substrate, at least a portion of the surface conductor circuit is provided with a roughened layer, and further the interlayer insulating material layer is provided on the substrate including the conductive circuit, and further,
    この層間絶縁材層上に他の導体回路が設けられてなる多層プリント配線板において、 前記粗化層は、Cu,NiおよびPからなる共晶化合物を含む層で構成されていることを特徴とする多層プリント配線板。 In the interlayer insulation layer on the other of the multilayer printed wiring board the conductor circuit is provided, wherein the roughened layer has a feature that it is constituted by a layer containing Cu, Ni and eutectic compounds consisting of P multi-layer printed wiring board to be.
  2. 【請求項2】 前記粗化層は、90<Cu<100mol%,0< Wherein said roughened layer, 90 <Cu <100mol%, 0 <
    Ni< 10mol%および0<P< 10mol%からなる共晶化合物を含む層で構成されていることを特徴とする請求項1 Ni <claim 1, characterized in that it is constituted by a layer containing 10 mol% and 0 <P <consisting 10 mol% eutectic compound
    に記載の多層プリント配線板。 Multi-layer printed wiring board according to.
  3. 【請求項3】 前記粗化層は、針状結晶の被膜である請求項1または2に記載の多層プリント配線板。 Wherein the roughened layer is a multilayer printed wiring board according to claim 1 or 2 which is coated needles.
  4. 【請求項4】 前記粗化層は、その厚さが5μm以下の被膜である請求項1〜3のいずれか1つに記載の多層プリント配線板。 Wherein said roughened layer is a multilayer printed wiring board according to the any one of claims 1 to 3 are the following coating 5μm its thickness.
  5. 【請求項5】 基板上に設けられた導体回路表面の少なくとも一部に粗化層を形成し、次いで、前記基板上に層間絶縁材層を形成し、その後、その層間絶縁材層上に導体回路を設ける多層プリント配線板の製造方法において、 導体回路が設けられた基板を、少なくともCu化合物、Ni 5. The roughened layer formed on at least a part of the conductor circuit surface provided on a substrate, then the an interlayer insulating material layer on a substrate, then the conductor on the interlayer insulation layer the method for manufacturing a multilayer printed wiring board provided with a circuit, a substrate on which a conductor circuit is provided, at least Cu compound, Ni
    化合物および次亜リン酸塩を含有する無電解めっき浴中に浸漬することにより、前記導体回路表面の少なくとも一部に、Cu,NiおよびPからなる共晶化合物を含む粗化層を形成することを特徴とする多層プリント配線板の製造方法。 By immersion in compound and in an electroless plating bath containing hypophosphite, at least a portion of the conductive circuit surface, to form a roughened layer comprising a eutectic compound consisting of Cu, Ni and P method for manufacturing a multilayer printed wiring board according to claim.
  6. 【請求項6】 浴中のCuイオン濃度,Niイオン濃度および次亜リン酸イオン濃度が、それぞれ、 2.2×10 -2 Cu ion concentration of 6. bath, Ni ion concentration and hypophosphite ion concentration, respectively, 2.2 × 10 -2 ~
    4.1×10 -2 mol/l,2.2 ×10 -3 〜 4.1×10 -3 mol/l, 4.1 × 10 -2 mol / l, 2.2 × 10 -3 ~ 4.1 × 10 -3 mol / l,
    0.20〜0.25 mol/lであるめっき浴を用いる無電解めっきを施すことにより、導体回路表面の少なくとも一部に、90<Cu<100mol%,0<Ni< 10mol%および0<P By performing electroless plating using a plating bath is 0.20 to 0.25 mol / l, at least a portion of the conductor circuit surface, 90 <Cu <100mol%, 0 <Ni <10mol% and 0 <P
    < 10mol%からなる共晶化合物を含む粗化層を形成することを特徴とする請求項5に記載の多層プリント配線板の製造方法。 <Method of manufacturing a multilayer printed wiring board according to claim 5, characterized in that to form a roughened layer comprising a eutectic compound consisting of 10 mol%.
  7. 【請求項7】 前記Cu化合物、Ni化合物および次亜リン酸塩は、それぞれ硫酸銅、硫酸ニッケルおよび次亜リン酸ナトリウムである請求項5または6に記載の多層プリント配線板の製造方法。 Wherein said Cu compound, Ni compound and hypophosphite, copper sulfate respectively, a method for manufacturing a multilayer printed wiring board according to claim 5 or 6 is nickel sulfate and sodium hypophosphite.
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WO1996017503A1 (en) * 1994-12-01 1996-06-06 Ibiden Co., Ltd. Multilayer printed wiring board and process for producing the same
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