JPS59129766A - Electroless plating method - Google Patents
Electroless plating methodInfo
- Publication number
- JPS59129766A JPS59129766A JP649083A JP649083A JPS59129766A JP S59129766 A JPS59129766 A JP S59129766A JP 649083 A JP649083 A JP 649083A JP 649083 A JP649083 A JP 649083A JP S59129766 A JPS59129766 A JP S59129766A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- resist
- catalyst
- electroless plating
- alkali
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1605—Process or apparatus coating on selected surface areas by masking
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0565—Resist used only for applying catalyst, not for plating itself
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemically Coating (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、無電解メッキ法に関し、エツチング工程なし
に、無菌、踏メンキにより、基板上に址属パターンを形
成しようとするものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electroless plating method, and is intended to form a solid pattern on a substrate by aseptic and sanding without an etching process.
従来の金属パターン形成法をプリント基板を例に挙げ、
欠点を含めて説明する。ツーリント基板の製造工程は、
接着剤塗布−銅箔貼付一穴明一洗浄一センシタイザー浸
漬−アクチベータ浸漬−スルホールメンキーレジストパ
ターン形成−エツチング−レジスト剥離−仕上メツキと
概略記載しても非常に多い工程を経なければならない。Taking the conventional metal pattern forming method as an example of a printed circuit board,
Explain including the shortcomings. The manufacturing process of Tourinto board is
A large number of steps must be performed, even if briefly described as adhesive application, copper foil pasting, hole cleaning, sensitizer dipping, activator dipping, through-hole menky resist pattern formation, etching, resist peeling, and final plating.
工程数を多り要することは、コストアンプ、納期遅延、
歩留の低下、合理化の阻害4神々の問題を発生する。Requiring a large number of processes increases costs, delays in delivery,
This causes problems such as decreased yield and impeded rationalization.
本発明はこれらの欠点ff:取り除く為のものであり、
プリント基板を例にとるならば、銅箔の無使用及び接着
剤塗布工程、銅箔貼付工程、スルホールメンキ工程、エ
ツチング工程、レジスト剥離工程を廃止し、エツチング
工程なしで無電解メッキによシ基板上に金属パターン形
成しようとするものである。以下本発明を図面に従って
詳述する。The present invention is intended to eliminate these drawbacks,
Taking printed circuit boards as an example, it is possible to eliminate the use of copper foil, eliminate the adhesive coating process, copper foil pasting process, through-hole coating process, etching process, and resist stripping process, and replace it with electroless plating without the etching process. The purpose is to form a metal pattern on a substrate. The present invention will be explained in detail below with reference to the drawings.
図1〜図5は本発明を示す製造工程図である。1 to 5 are manufacturing process diagrams showing the present invention.
原料の絶縁性の基板1はガラスエポキシ系、ポリイミド
系、ABS系、セラミック糸、ガラス糸とあらゆる絶縁
物の使用が可能である。又霊施等の導電物質を用いる時
は表面に絶縁物質を被覆すれは本発明の製造工程が適用
出来る。For the insulating substrate 1 as a raw material, any insulating material such as glass epoxy, polyimide, ABS, ceramic thread, glass thread, etc. can be used. Further, when using a conductive material such as a spiritual material, the manufacturing process of the present invention can be applied to coat the surface with an insulating material.
図2は基板1の上にアルカリ可溶タイプのレジスト2を
形成した断面図である。本製造方法による効果を生み出
すにはアルカリ可溶タイプのレジスト便用が必須の条件
である。パターン形成法はスクリーン印刷、写真製版法
等従来の方法をそのまま適用出来る。パターン形成に於
いて注意することは金属パターンを形成する部分は基板
1を露出させることにある。FIG. 2 is a cross-sectional view of an alkali-soluble type resist 2 formed on a substrate 1. As shown in FIG. In order to produce the effects of this manufacturing method, it is essential to use an alkali-soluble type resist. As a pattern forming method, conventional methods such as screen printing and photolithography can be applied as they are. In forming the pattern, care must be taken to expose the portion of the substrate 1 where the metal pattern is to be formed.
図3はキャタライザ溶液浸漬により、基板1及びレジス
ト2の上に触媒コロイド錯イオン3を形成させた断面図
である。キャタライザ溶液は無電解メッキの触媒核形成
処理液の一液タイブの使用が触媒核形成及びレジスト剥
離の為に望ましく組成は、P(1(! 12−0.2〜
5g/1.. Sn c 12−10〜40g / t
、濃F[’4 100〜200cc/l、 常温で
10秒〜10分の範囲で触媒コロイド錯イオン3を基板
1及びレジスト20表面に目に見えない薄膜で形成する
ことができる。FIG. 3 is a cross-sectional view showing catalyst colloid complex ions 3 formed on the substrate 1 and resist 2 by immersion in a catalytic solution. It is desirable to use a one-component type of catalyst nucleation treatment solution for electroless plating as the catalyzer solution for catalyst nucleation and resist stripping, and the composition is P(1(! 12-0.2 ~
5g/1. .. Snc 12-10~40g/t
, concentrated F['4 100 to 200 cc/l, the catalyst colloidal complex ions 3 can be formed as an invisible thin film on the surfaces of the substrate 1 and the resist 20 in a range of 10 seconds to 10 minutes at room temperature.
図4は触媒コロイド錯イオン3をアルカリ溶液に浸漬す
ることにより触媒核4に変え、且つアルカリ可溶のレジ
スト2を溶解すると同時にレジスト2上の触媒コロイド
イオン3を除去した図である。触媒コロイド錯イオン3
は親水性である為にアルカリ溶液は容易にレジスト2に
達し溶解され、同時にレジスト2上のコロイド錯イオン
3も除去さ1する。又、基板上の触媒核コロイド錯イオ
ン3はアルカリに接触することによシ触媒核4と変化し
基板1に強固に吸着する為、レジスト部以外の触媒核4
はアルカリ処理によシバターン通シ残留する。アルカリ
処理に用いる溶液は溶解した時にアルカリ性を示す薬品
で良く、NaoE(−10g/L〜100g/L、 1
0〜80℃で1〜10分間の処理で本発明の効果を得る
ことができる。FIG. 4 is a diagram in which the catalyst colloid complex ions 3 are immersed in an alkaline solution to convert them into catalyst nuclei 4, and the catalyst colloid ions 3 on the resist 2 are removed at the same time as the alkali-soluble resist 2 is dissolved. Catalyst colloid complex ion 3
Since is hydrophilic, the alkaline solution easily reaches the resist 2 and dissolves it, and at the same time, the colloidal complex ions 3 on the resist 2 are also removed. In addition, the catalyst core colloidal complex ions 3 on the substrate change into catalyst nuclei 4 when they come into contact with an alkali, and are strongly adsorbed to the substrate 1, so that the catalyst nuclei 4 other than the resist area
remains after alkali treatment. The solution used for alkali treatment may be a chemical that shows alkalinity when dissolved, and NaoE (-10g/L to 100g/L, 1
The effects of the present invention can be obtained by treatment at 0 to 80°C for 1 to 10 minutes.
図5は触媒核4を核として無電解メンキによα金属被膜
5を形成した断面図を示す。図4に示した基板を無電解
メッキ浴に浸漬することによ勺、触媒核4が核となシ無
電解メンキの析出が開始し、以後析出金属被膜5が触媒
となシ金属被膜5が生長を続ける。又触媒核4の形成さ
れていない部分には金属被膜の成長は起らない為に選択
メッキとな勺、所望の部分のみに金属被膜5を形成する
パターンメッキが可能である。使用する無電解メッキ浴
は自己触媒タイプの浴ならば、どの金属浴も使用可能で
ある。FIG. 5 shows a cross-sectional view of the α metal coating 5 formed by electroless coating using the catalyst core 4 as the core. By immersing the substrate shown in FIG. 4 in an electroless plating bath, electroless plating starts to be deposited using the catalyst nuclei 4 as the nuclei, and thereafter the deposited metal film 5 acts as a catalyst and the metal film 5 is formed. Continue to grow. Further, since no metal coating is grown in areas where catalyst nuclei 4 are not formed, selective plating or pattern plating in which metal coating 5 is formed only in desired areas is possible. Any metal bath can be used as the electroless plating bath as long as it is an autocatalytic type bath.
以上詳述した様に本発明による方法を用いれはエツチン
グ工程なしで基板上に@属バp−yの形成が可能である
。又、レジスト剥離と触媒核形成を同時に行なってしま
う為、工程短縮にも大きな効果を得ることができる。As described in detail above, by using the method according to the present invention, it is possible to form a @ group p-y on a substrate without an etching step. Furthermore, since resist stripping and catalyst nucleation are performed simultaneously, a great effect can be obtained in shortening the process.
プリント基板に本発明の無電解メッキ法を用いた場合の
製造工程は、尺明−洗浄−レジストパターン形成−キャ
タライザ処理−アルカリ処理−無電解メンキー仕上メッ
キと、スルホールメレキと金属パターン形成を同時に行
なう事が可能とな9、工程数も従来法の11工程から7
エ程と大幅に短縮う“ることか可能となる。工程の短縮
は合理化、コストダウンに大すく寄−与することが可能
である。The manufacturing process when using the electroless plating method of the present invention for a printed circuit board is as follows: stripping, cleaning, resist pattern formation, catalytic treatment, alkali treatment, electroless menky finish plating, through-hole metal plating, and metal pattern formation at the same time. 9, and the number of steps has been reduced from 11 in the conventional method to 7.
It is possible to significantly shorten the process.Shortening the process can greatly contribute to rationalization and cost reduction.
他の用途としては基板上に金属パターンを形成するもの
には総て適用可能であシ、7オトフアプリケーシヨン用
ハードマスク、ガラス器具の模様付、液晶パネル機能数
善用メッキ等幅広く使用することが出来る。As for other uses, it can be applied to anything that forms a metal pattern on a substrate, and can be used for a wide range of purposes, such as hard masks for 7-office applications, patterning on glassware, and plating for improving the functionality of liquid crystal panels. I can do it.
最後に本発明による無電解メッキ法の特徴を再度述べる
と、エンチング工程なしで基板上に金属パターン形成が
可能となる為に大幅なコストダウンが可能でアシ、フォ
トファブリケーション用の7オトレジストを用IAiL
はフォトレジストの解像力の許す範囲迄の細線のパター
ンメッキが可能となり将来の電子技術の発展に欠かせな
い技術である。Finally, to restate the characteristics of the electroless plating method according to the present invention, it is possible to form a metal pattern on the substrate without an etching process, resulting in a significant cost reduction. IAiL
This technology enables pattern plating of fine lines within the range allowed by the resolution of photoresist, and is an indispensable technology for the development of future electronic technology.
図面の図1から図5は1本発明の工程を示す断面図であ
る。図1は絶縁性を肩する基板を示す図。
図2はレジストによるバクーン形成図、ト15はキャタ
ライザ液による触媒コロイド錯イオン付着を示す図1図
4は触媒核扱着とレジスト及びレジメト上のコロイド錯
イオンを除去した図、図5は触媒核上に無電解メッキ被
膜を析出させパターンメッキをした図。
1・・・・・・基 板、 2・・・・・・レジ
スト、5・・・・・・触媒コロイド錯イオン。
4・・・・・・触媒核、 5・・・・・・金属被
膜。
以 上
出願人 株式会社 諏訪精工台
代理人 弁理士 最 上 務
2り2り2シ4シ2
団1
目2
回さ
51i1斗
団51 to 5 of the drawings are cross-sectional views showing one process of the present invention. FIG. 1 is a diagram showing a substrate that provides insulation. Figure 2 is a diagram of Bakun formation by the resist, Figure 15 is a diagram showing the catalyst colloid complex ion adhesion by the catalytic liquid. A diagram showing pattern plating with an electroless plating film deposited on top. 1...Substrate, 2...Resist, 5...Catalyst colloid complex ion. 4... Catalyst nucleus, 5... Metal coating. Applicant Suwa Seikodai Co., Ltd. Agent Patent Attorney Mogami Tsumu 2 2 2 2 4
Claims (1)
せる部分のみ基板を露出させた所望のパターンをアルカ
リ可溶タイプのレジストで形成し、キャタライザ浸漬に
より全面に触媒コロイド錯イオンを吸着させる。次にア
ルカリ溶液浸漬により触媒コロイド錯イオンを形媒核に
変えると同時妬、同アルカリ溶液によりアルカリ可溶レ
ジストとアルカリ可溶レジスト上の角虫媒コロイド錯イ
オンを同時に溶解除去し、基板の触媒核の吸着されてい
る部分のみに無1も、解メッキ金属を析出させることを
特徴とする無電解メッキ法。(1) Form a desired pattern on an insulating substrate with an alkali-soluble resist, exposing only the part where the electroless coating is to be deposited, and adsorb catalyst colloid complex ions on the entire surface by immersion in a catalyzer. . Next, the catalyst colloid complex ions are converted into form nuclei by immersion in an alkaline solution, and at the same time, the alkali-soluble resist and the hornworm colloid complex ions on the alkali-soluble resist are simultaneously dissolved and removed, and the catalyst colloid of the substrate is removed. An electroless plating method characterized by depositing deplated metal only on the areas where the nuclei are adsorbed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP649083A JPS59129766A (en) | 1983-01-18 | 1983-01-18 | Electroless plating method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP649083A JPS59129766A (en) | 1983-01-18 | 1983-01-18 | Electroless plating method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59129766A true JPS59129766A (en) | 1984-07-26 |
Family
ID=11639909
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP649083A Pending JPS59129766A (en) | 1983-01-18 | 1983-01-18 | Electroless plating method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59129766A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0312551A1 (en) * | 1987-04-28 | 1989-04-26 | Macdermid Incorporated | Additive method for manufacturing printed circuit boards using aqueous alkaline developable and strippable photoresists |
JP2003008179A (en) * | 2001-06-18 | 2003-01-10 | Yazaki Corp | Patterning method of printed circuit and flexible wiring |
WO2016128695A1 (en) * | 2015-02-12 | 2016-08-18 | Jet Metal Technologies | Method and device for producing metal patterns on a substrate for decorative and/or functional purposes, manufacture of objects incorporating said production and set of consumables used |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55158696A (en) * | 1979-05-30 | 1980-12-10 | Hitachi Ltd | Method of fabricating printed board |
-
1983
- 1983-01-18 JP JP649083A patent/JPS59129766A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55158696A (en) * | 1979-05-30 | 1980-12-10 | Hitachi Ltd | Method of fabricating printed board |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0312551A1 (en) * | 1987-04-28 | 1989-04-26 | Macdermid Incorporated | Additive method for manufacturing printed circuit boards using aqueous alkaline developable and strippable photoresists |
JP2003008179A (en) * | 2001-06-18 | 2003-01-10 | Yazaki Corp | Patterning method of printed circuit and flexible wiring |
JP4669631B2 (en) * | 2001-06-18 | 2011-04-13 | 矢崎総業株式会社 | Printed circuit and flexible wiring patterning method |
WO2016128695A1 (en) * | 2015-02-12 | 2016-08-18 | Jet Metal Technologies | Method and device for producing metal patterns on a substrate for decorative and/or functional purposes, manufacture of objects incorporating said production and set of consumables used |
FR3032724A1 (en) * | 2015-02-12 | 2016-08-19 | Jet Metal Tech | METHOD AND DEVICE FOR REALIZING METALLIC PATTERNS ON A SUBSTRATE FOR DECORATIVE AND / OR FUNCTIONAL PURPOSES MANUFACTURING OBJECTS INCORPORATING THIS PRODUCTION AND CONSUMABLE ASSEMBLY USING THE SAME |
CN107250442A (en) * | 2015-02-12 | 2017-10-13 | 喷射金属技术公司 | For the method and apparatus for the metal pattern that ornamental and/or feature purpose is formed on substrate, the manufacture of the article comprising the formation and consumptive material group used |
US20180030599A1 (en) * | 2015-02-12 | 2018-02-01 | Jet Metal Technologies | Method and device for producing metal patterns on a substrate for decorative and/or functional purposes, manufacture of objects incorporating said production and set of consumables used |
US11168398B2 (en) | 2015-02-12 | 2021-11-09 | Jet Metal Technologies | Method and device for producing metal patterns on a substrate for decorative and/or functional purposes, manufacture of objects incorporating said production and set of consumables used |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7993509B2 (en) | Manufacturing method of double-sided wiring glass substrate | |
JPH022949B2 (en) | ||
JPH06275933A (en) | Circuit board and manufacture thereof | |
JPH022948B2 (en) | ||
JPS59129766A (en) | Electroless plating method | |
US7951301B2 (en) | Method for producing a ceramic printed-circuit board | |
JPS6148570A (en) | Formation of conductor layer onto resin | |
JPH09307216A (en) | Manufacture of wiring board, and wiring board | |
US5246732A (en) | Method of providing a copper pattern on a dielectric substrate | |
JPS59133359A (en) | Electroless plating method | |
JPS6037794A (en) | Method of producing printed circuit board | |
JPS59106181A (en) | Method of producing printed circuit board | |
JPS59155994A (en) | Method of producing printed circuit board | |
JPS59136471A (en) | Electroless plating method | |
JPS63239997A (en) | Manufacture of board | |
JPS62238683A (en) | Formation of metal circuit pattern | |
JPS60241291A (en) | Method of producing printed circuit board | |
JPH04335593A (en) | Manufacture of flexible double-sided wiring board | |
TW201021641A (en) | Method for manufacturing embedded film resistor of printed circuit board | |
JPH05218620A (en) | Manufacture of printed wiring board | |
JPS61256688A (en) | Manufacture of circuit board | |
JPS6064496A (en) | Method of producing printed circuit board | |
JPH02103992A (en) | Manufacture of circuit board | |
JPS6064495A (en) | Method of producing printed circuit board | |
JPS62259497A (en) | Manufacture of printed circuit board |