JPS6347997A - Manufacture of ceramic double-sided wiring board - Google Patents
Manufacture of ceramic double-sided wiring boardInfo
- Publication number
- JPS6347997A JPS6347997A JP19189486A JP19189486A JPS6347997A JP S6347997 A JPS6347997 A JP S6347997A JP 19189486 A JP19189486 A JP 19189486A JP 19189486 A JP19189486 A JP 19189486A JP S6347997 A JPS6347997 A JP S6347997A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic
- substrate
- hole
- wiring board
- double
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims description 45
- 238000007747 plating Methods 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 21
- 238000007788 roughening Methods 0.000 claims description 8
- 238000010304 firing Methods 0.000 claims description 7
- 239000007788 liquid Substances 0.000 claims description 2
- 238000009966 trimming Methods 0.000 claims description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 229910052802 copper Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 235000011007 phosphoric acid Nutrition 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 229910052839 forsterite Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052574 oxide ceramic Inorganic materials 0.000 description 1
- 239000011224 oxide ceramic Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 230000001235 sensitizing effect Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- -1 steatite Chemical compound 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/381—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔技術分野〕
この発明は、電子基材として使用されるセラミック両面
配線基板の製法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] This invention relates to a method for manufacturing a ceramic double-sided wiring board used as an electronic substrate.
従来、スルホールを有するセラミック両面配線基板の製
法は、セラミック基板の両面にスクリーン印刷により、
回路パターンになるように導体ペーストを塗布乾燥後、
スルホール用穴の内部に導体ペーストを充填し、さらに
は、両面に抵抗ペーストをスクリーン印刷により塗布乾
燥し大気中で焼成すると言う方法が行われている。Conventionally, the manufacturing method for double-sided ceramic wiring boards with through holes is to screen print on both sides of the ceramic board.
After applying conductive paste to form a circuit pattern and drying,
A method is used in which the inside of the through-hole is filled with a conductive paste, and then a resistive paste is applied to both sides by screen printing, dried, and fired in the atmosphere.
このスルホール用穴の内部へ導体ペーストを充填する方
法として、ノズルによりスルホール用穴の内部へ導体ペ
ーストを充填する方法、あるいは、スルホール内を減圧
し圧力差により４電ペーストを充填する方法等が用いら
れている。しかし、これらの充填力は、工程が煩雑であ
り、しかも、４通不良が発生しやすい。導体ペーストと
して、Ａｕ、 Ａｇ／Ｐｄ等の貴金属ペーストが主に用
いられるので、ペーストの価格が高く、コスト高となる
。As a method for filling the inside of the through-hole hole with the conductive paste, there are two methods: filling the inside of the through-hole hole with the conductive paste using a nozzle, or reducing the pressure inside the through-hole and filling the 4-volt paste using a pressure difference. It is being However, these filling forces require a complicated process, and moreover, four-pack failures are likely to occur. Since a noble metal paste such as Au or Ag/Pd is mainly used as the conductor paste, the price of the paste is high, resulting in high costs.
さらに、ガラスフリットがペースト中に含まれているた
め、はんだ付着性が劣る。Furthermore, since glass frit is included in the paste, solder adhesion is poor.
一方、セラミック基板への導体層の形成法の１つとして
、めっき法によるものがある。この方法によれば、セラ
ミック基板両面への導体層の形成およびスルホール形成
を同時に行うことができるため、スルホール信頼性の高
いセラミック両面配線基板が製造できる。しかも、形成
される導体層は、はとんど不純物を含まないため、はん
だ付着性を向上させることができ、微細配線も可能とな
る。On the other hand, one of the methods for forming a conductor layer on a ceramic substrate is a plating method. According to this method, it is possible to simultaneously form a conductor layer on both sides of the ceramic substrate and form through holes, so a double-sided ceramic wiring board with high through hole reliability can be manufactured. Moreover, since the formed conductor layer contains almost no impurities, solder adhesion can be improved and fine wiring becomes possible.
しかし、めっきによる方法では、導体層の密着力が弱く
、取り扱いによっては、スルホールに影響がおよび、ス
ルホール信頼性が悪くなるという問題がある。However, the plating method has a problem in that the adhesion of the conductor layer is weak, and depending on handling, the through-holes may be affected, resulting in poor through-hole reliability.
〔発明の目的〕
この発明は、このような問題に鑑みて、導体層の密着性
がよく、スルホール信頼性の高いセラミック両面配線基
板を安価で得ることができる製法を提供することを目的
としている。[Object of the Invention] In view of the above-mentioned problems, an object of the present invention is to provide a manufacturing method that can inexpensively obtain a ceramic double-sided wiring board with good adhesion of the conductor layer and high through-hole reliability. .
この発明は、このような目的を達成するために、スルホ
ール用穴が形成されたセラミック基板の両面およびスル
ホール用穴の内壁面にめっきにより導体層を形成し、前
記基板表面上に形成された導体層で回路パターンを描く
とともに、この回路パターン上に抵抗体を形成するセラ
ミック両面配線基板の製法であって、前記めっきに先立
ち前記セラミック基板の基板表面およびスルホール用穴
の内壁面を処理液で粗化する工程を含んでいることを特
徴とするセラミック両面配線基板の製法を要旨としてい
る。In order to achieve such an object, the present invention forms a conductor layer by plating on both surfaces of a ceramic substrate in which through-hole holes are formed and on the inner wall surface of the through-hole hole, and the conductor layer formed on the surface of the substrate is formed by plating. A method for manufacturing a double-sided ceramic wiring board in which a circuit pattern is drawn in layers and a resistor is formed on the circuit pattern, wherein, prior to the plating, the surface of the ceramic board and the inner wall surface of the through-hole hole are roughened with a processing liquid. The gist of this paper is a method for manufacturing a double-sided ceramic wiring board, which is characterized by including a step of converting the printed circuit board.
以下に、この発明を、その実施例をあられす図面を参照
しつつ詳しく説明する。Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
用いられセラミック基板としては、アルミナ。The ceramic substrate used is alumina.
フォルステライト、ステアタイト、ジルコニア。forsterite, steatite, zirconia.
チタニア等の酸化物系セラミック基板や、炭化珪素、窒
化アルミなどの炭化物、窒化物系セラミック基板が挙げ
られる。Examples include oxide ceramic substrates such as titania, and carbide and nitride ceramic substrates such as silicon carbide and aluminum nitride.
スルホール用穴の形成法は、焼成前のセラミックグリー
ンシートをパンチングによって穴あけ加工したのちに焼
成する方法、あるいは、焼成して基板を得たのち、レー
ザー加工やドリル加工により形成する方法などがあるが
、特に限定されないセラミック基板表面およびスルホー
ル用穴の粗化は、熱リン酸、溶融アルカリ、ＨＦ等の溶
液中に浸漬する方法があるが、特に、限定されない。There are two ways to form holes for through holes, such as punching a hole in a ceramic green sheet before firing and then firing it, or firing it to obtain a substrate and then forming it by laser processing or drilling. The surface of the ceramic substrate and the holes for through-holes may be roughened by, but not limited to, a method of immersing the ceramic substrate in a solution such as hot phosphoric acid, molten alkali, or HF.
粗化によって基板表面に凹部が形成され、この凹部にめ
っきによって形成される導体が入り込んでアンカー効果
が生じ、基板と４体層との密着力が向上するのである。The roughening forms recesses on the substrate surface, and the conductor formed by plating enters the recesses, creating an anchor effect and improving the adhesion between the substrate and the four-layer structure.
めっき法による導体層の形成は、セラミック基板表面お
よびスルホール内壁面を粗化したのち、回路パターンの
逆パターン状にめっきレジストを塗布したのち、公知の
センシタイジングーアクチベーションを行い、スルホー
ル用穴の内壁面を含む基板表面の露出部にパラジウムの
核付けを行う。つぎに、化学めっき液中にこの基板を浸
漬し、化学めっき処理を行う。必要に応じて、さらに、
電気めっきによって厚付けを行う。導体層形成後レジス
ト膜を除去する。以上のようにして回路形成と同時にス
ルホールも形成されるようになっている。 抵抗体の形
成は、回路パターンの上に抵抗ペーストをスクリーン印
刷などで所望のパターンとなるように塗布乾燥し、基板
とともに焼成して得るのであるが、酸化性雰囲気で焼成
したのでは、導体層が酸化してしまうので、非酸化性雰
囲気で焼成を行わなければならない。そこで、抵抗ペー
ストも非酸化性雰囲気で焼成できるものを選ぶ必要があ
る。この抵抗ペーストとしては、Ｓｎ、ＬａＢ、系、Ｔ
ａ系窒化物、５ｒＲｕＯ４系のものが挙げられる。なお
、焼成温度は、抵抗ペーストに含まれるガラスフリット
が溶融接合する温度で、好ましくは、５００°Ｃ−７１
１００°Ｃの範囲で行う。To form a conductor layer using the plating method, after roughening the ceramic substrate surface and the inner wall surface of the through-hole, a plating resist is applied in the reverse pattern of the circuit pattern, and then a well-known sensitizing-activation is performed to form the inside of the through-hole hole. Palladium is nucleated on the exposed parts of the substrate surface, including the walls. Next, this substrate is immersed in a chemical plating solution to perform chemical plating treatment. In addition, if necessary,
Thickening is done by electroplating. After forming the conductor layer, the resist film is removed. As described above, through holes are also formed at the same time as circuit formation. A resistor is formed by applying a resistor paste onto a circuit pattern using screen printing to form the desired pattern, drying it, and firing it together with the substrate. However, if it is fired in an oxidizing atmosphere, the conductor layer oxidizes, so firing must be performed in a non-oxidizing atmosphere. Therefore, it is necessary to select a resistance paste that can be fired in a non-oxidizing atmosphere. This resistance paste includes Sn, LaB, T
Examples include a-based nitrides and 5rRuO4-based ones. The firing temperature is the temperature at which the glass frit contained in the resistance paste is melted and bonded, and is preferably 500°C-71°C.
Perform at a temperature of 100°C.
抵抗体の抵抗値の調整が必要であれば、レーザ−やサン
ドブラストによるトリミングによって行う。If it is necessary to adjust the resistance value of the resistor, trimming is performed by laser or sandblasting.
以上のように、この発明の製法によれば、スルホールが
めっきにより形成されるので、貴金属の導体ペーストを
用いる場合に比べて製造コストが低減できる。しかも、
めっきを行う前に、基板表面を粗化しておくので、基板
とめっきによって形成された扉体層との密着性が非常に
よく、スルホールの信頼性も高いものが得られる。As described above, according to the manufacturing method of the present invention, the through holes are formed by plating, so manufacturing costs can be reduced compared to the case where a conductive paste of noble metal is used. Moreover,
Since the surface of the substrate is roughened before plating, the adhesion between the substrate and the door layer formed by plating is very good, and the reliability of the through holes is also high.
つぎに、実施例を説明する。Next, an example will be explained.
（実施例１）
９６％焼結アルミナ基板（２’Ｘ２“ｘｏ、６３５龍）
にレーザーで２００〜４００−φのスルホール用穴をあ
けた。この基板を３３０℃に加熱した８５％オルトリン
酸粗化液中に５分間浸漬し、基板表面およびスルホール
用穴内壁面を均一に粗化した。粗化処理した基板を充分
に洗浄して乾燥したのち、回路パターンとは逆のパター
ン形状にめっきレジストを基板両面に塗布した。この基
板をセンシタイジングおよびアクチベーションの処理液
に順に浸漬して基板の露出部にパラジウムの核付けを行
った。この基板を市販の化学銅めっき液に浸漬し、約１
−の銅層を形成し、さらに、この上に電気硫酸銅めっき
を行い、銅層を１０Ｊ１ｍにした。こののち、めっきレ
ジスト膜を剥離した。(Example 1) 96% sintered alumina substrate (2'X2"xo, 635 dragon)
A through hole with a diameter of 200 to 400 mm was drilled using a laser. This substrate was immersed for 5 minutes in an 85% orthophosphoric acid roughening solution heated to 330° C. to uniformly roughen the substrate surface and the inner wall surface of the through hole. After the roughened substrate was sufficiently washed and dried, a plating resist was applied to both sides of the substrate in a pattern shape opposite to that of the circuit pattern. This substrate was sequentially immersed in sensitizing and activation treatment solutions to nucleate palladium onto the exposed portions of the substrate. This board was immersed in a commercially available chemical copper plating solution for about 1
A copper layer of - was formed, and further electrolytic copper sulfate plating was performed on this to make the copper layer 10J1m. After this, the plating resist film was peeled off.
このとき、スルホール部の断線等の不良は見られなかっ
た。このようにして得られた基板両面の回路上に５ｒＲ
ｕＯ４系の抵抗ペーストをスクリーン印刷によって所望
のパターンに塗布した。これを９００℃の窒素雰囲気中
で焼成し抵抗体を形成した。最後に抵抗体が、所望の抵
抗値となるようにレーザートリマーでトリミングして、
第１図にみるような抵抗体５を有するセラミック両面配
線基板を得た。第１図中、１はセラミック基板、２は導
体回路、３はスルホール、４はスルホールの導体層であ
る。なお、銅層および抵抗体の基板に対する密着力は、
いずれも２．０〜３．０ｋｇ／龍２の高い値を示し、し
かも、スルホール信頼性は、従来のペースト法に比べて
非常に高い値を示した。At this time, no defects such as disconnection in the through-hole portion were observed. 5rR on the circuits on both sides of the board thus obtained.
A uO4-based resistive paste was applied in a desired pattern by screen printing. This was fired in a nitrogen atmosphere at 900°C to form a resistor. Finally, the resistor is trimmed with a laser trimmer to the desired resistance value.
A ceramic double-sided wiring board having a resistor 5 as shown in FIG. 1 was obtained. In FIG. 1, 1 is a ceramic substrate, 2 is a conductor circuit, 3 is a through hole, and 4 is a conductor layer of the through hole. The adhesion of the copper layer and resistor to the substrate is
All of them showed high values of 2.0 to 3.0 kg/dragon 2, and in addition, the through-hole reliability showed a very high value compared to the conventional paste method.
（実施例２）
９６％アルミナグリーンシートにパンチングにより穴を
あけたのち、焼成して２００〜４０〇−φのスルホール
穴を有する焼結アルミナ基板を得た。この基板を実施例
１と同様にして粗化し、パラジウムを核付けしたのち、
厚付はタイプの化学銅めっき液に浸漬して１０ハの導体
層を形成した。電気めっきは行わなかった。以下実施例
１と同様にしてセラミック両面配線基板を得た。(Example 2) A 96% alumina green sheet was punched and then fired to obtain a sintered alumina substrate having through-holes of 200 to 400 mm. After roughening this substrate in the same manner as in Example 1 and nucleating palladium,
The conductor layer was immersed in a type of chemical copper plating solution to form a thick conductor layer. No electroplating was performed. Thereafter, a ceramic double-sided wiring board was obtained in the same manner as in Example 1.
特性は、実施例１と同様であった。The characteristics were similar to those in Example 1.
（実施例３）
焼結ジルコニア基板（２“×２“Ｘ ０．６３５ ｍｕ
）を用いた以外は、実施例１と同様にしてセラミック両
面配線基板を得た。(Example 3) Sintered zirconia substrate (2" x 2" x 0.635 mu
) A ceramic double-sided wiring board was obtained in the same manner as in Example 1, except that a ceramic double-sided wiring board was used.
特性は、実施例１と同様であった。The characteristics were similar to those in Example 1.
（実施例４）
焼結窒化アルミ基板（２“×２“Ｘ ０．６３５ ｍｍ
）を用い、粗化処理液温度を３００℃とした以外は実施
例１と同様にしてセラミック両９面配線基板を得た。(Example 4) Sintered aluminum nitride substrate (2" x 2" x 0.635 mm
), and a ceramic double-sided nine-sided wiring board was obtained in the same manner as in Example 1, except that the roughening solution temperature was 300°C.
特性は、実施例１と同様であった。The characteristics were similar to those in Example 1.
（実施例５）
焼結窒化アルミ基板（２″Ｘ２’Ｘ０．６３５ｍ鳳）を
用い、粗化処理液温度を３００℃とした以外は実施例２
と同様にしてセラミック両面配線基板を得た。(Example 5) Example 2 except that a sintered aluminum nitride substrate (2″ x 2′ x 0.635 m) was used and the roughening treatment solution temperature was 300°C.
A ceramic double-sided wiring board was obtained in the same manner as above.
特性は、実施例１と同様であった。The characteristics were similar to those in Example 1.
この発明にかかるセラミック両面配Ｈｉ’Ａ ａ ＋反
の製法は、上記実施例に限定されない。実施例では、め
っき前に基板表面にめっきレジストを施すようにしてい
るが、まず、基板表面全体にめっきにより導体層を形成
し、回路パターンおよびスルホールにレジストを塗布し
、エツチング加工により回路を形成するようにしても構
わない。実施例では抵抗体を抵抗ペーストを基板ととも
に焼成することにより形成していたが、抵抗体を後で回
路に接合するようにしてもよい。しかしながら、抵抗ペ
ーストを用いるようにした方が、基板全体の厚みが薄く
て済むので好ましいと言える。The method for manufacturing the ceramic double-sided Hi'A a + fabric according to the present invention is not limited to the above embodiments. In the example, a plating resist is applied to the substrate surface before plating. First, a conductive layer is formed on the entire substrate surface by plating, resist is applied to the circuit pattern and through holes, and a circuit is formed by etching. You may do as you please. In the embodiment, the resistor was formed by baking the resistor paste together with the substrate, but the resistor may be bonded to the circuit later. However, it can be said that it is preferable to use a resistance paste because the thickness of the entire substrate can be reduced.
この発明のセラミック両面配線基板の製法は、以上のよ
うに、スルホール用穴が形成されたセラミック基板の両
面およびスルホール用穴の内壁面にめっきにより導体層
を形成し、前記基板表面上に形成された導体層で回路パ
ターンを描くとともに、この回路パターン上に抵抗体を
形成するセラミック両面配線基板の製法であって、前記
めっきに先立ち前記セラミック基板の基板表面およびス
ルホール用穴の内壁面を処理液で粗化する工程を含んで
いるので、導体層の密着性がよく、スルホール信頼性の
高いセラミック′両面配線基板を安価で得ることができ
ろ。As described above, the method for manufacturing a double-sided ceramic wiring board of the present invention involves forming conductor layers by plating on both sides of a ceramic substrate in which through-hole holes are formed and on the inner wall surface of the through-hole holes, and then forming a conductor layer on the surface of the substrate. A method for manufacturing a double-sided ceramic wiring board, in which a circuit pattern is drawn using a conductor layer formed on the ceramic substrate, and a resistor is formed on the circuit pattern. Since the method includes a roughening step, it is possible to obtain a ceramic double-sided wiring board with good adhesion of the conductor layer and high through-hole reliability at a low cost.
４、 ｌ］面の筒車な説明
第１図は、この発明にかかる製法で得られるセラミック
両面配線基板の１実施例をあられす側断面図である。Figure 1 is a side sectional view of an embodiment of a ceramic double-sided wiring board obtained by the manufacturing method according to the present invention.
１・・・セラミック基板 ２・・・導体回路 ３・・・
スルホール ５・・・抵抗体
代理人 弁理士 松 本 武 彦
第１図1...Ceramic board 2...Conductor circuit 3...
Through Hole 5...Resistance body agent Patent attorney Takehiko Matsumoto Figure 1
Claims (3)
面およびスルホール用穴の内壁面にめっきにより導体層
を形成し、前記基板表面上に形成された導体層で回路パ
ターンを描くとともに、この回路パターン上に抵抗体を
形成するセラミック両面配線基板の製法であって、前記
めっきに先立ち前記セラミック基板の基板表面およびス
ルホール用穴の内壁面を処理液で粗化する工程を含んで
いることを特徴とするセラミック両面配線基板の製法。(1) A conductor layer is formed by plating on both sides of the ceramic substrate in which through-hole holes are formed and on the inner wall surface of the through-hole hole, and a circuit pattern is drawn using the conductor layer formed on the surface of the substrate, and the circuit pattern is A method for manufacturing a ceramic double-sided wiring board on which a resistor is formed, the method comprising the step of roughening the substrate surface of the ceramic substrate and the inner wall surface of the through-hole hole with a treatment liquid prior to the plating. A manufacturing method for ceramic double-sided wiring boards.
のパターンとなるように塗布し、セラミック基板ととも
に焼成することによって形成される特許請求の範囲第１
項記載のセラミック両面配線基板の製法。(2) Claim 1 in which the resistor is formed by applying a resistor paste onto a circuit pattern in a desired pattern and firing it together with a ceramic substrate.
A method for producing a ceramic double-sided wiring board as described in Section 1.
調整がなされる特許請求の範囲第１項または第２項記載
のセラミック両面配線基板の製法。(3) The method for manufacturing a double-sided ceramic wiring board according to claim 1 or 2, wherein the resistance value of the resistor is adjusted by trimming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19189486A JPS6347997A (en) | 1986-08-15 | 1986-08-15 | Manufacture of ceramic double-sided wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19189486A JPS6347997A (en) | 1986-08-15 | 1986-08-15 | Manufacture of ceramic double-sided wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6347997A true JPS6347997A (en) | 1988-02-29 |
Family
ID=16282215
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19189486A Pending JPS6347997A (en) | 1986-08-15 | 1986-08-15 | Manufacture of ceramic double-sided wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6347997A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03141662A (en) * | 1989-10-26 | 1991-06-17 | Matsushita Electric Works Ltd | Manufacture of ceramic wiring circuit board |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59159592A (en) * | 1983-03-03 | 1984-09-10 | オ−ケ−プリント配線株式会社 | Method of producing ceramic board |
| JPS6059764A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
-
1986
- 1986-08-15 JP JP19189486A patent/JPS6347997A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59159592A (en) * | 1983-03-03 | 1984-09-10 | オ−ケ−プリント配線株式会社 | Method of producing ceramic board |
| JPS6059764A (en) * | 1983-09-13 | 1985-04-06 | Mitsubishi Electric Corp | Manufacture of hybrid integrated circuit substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03141662A (en) * | 1989-10-26 | 1991-06-17 | Matsushita Electric Works Ltd | Manufacture of ceramic wiring circuit board |
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